Sequential Logic
• Combinatorial components: the output values
are computed only from their present input
values.
• Sequential components: their output values
are computed using both the present and past
input values.
• Sequential circuits can contain only a finite
number of states finite state machines
• Synchronous and Asynchronous
Sequential Circuits
• Contains Memory Elements
• Asynchronous sequential circuits change their state
and output values when input changes
• Synchronous sequential circuits change their output
values at fixed points of time, which are specified by the
rising or falling edge of a clock signal
• Clock period is the time between successive transitions
in the same direction
• Active high – state changes occur at the clock’s rising
edge( on higher voltage)
• Active low – state changes occur at the clock’s falling
edge( on lower voltage)
4 Basic types of Flip-Flops
• SR, JK, D, and T
• JK ff has 2 inputs, J and K need to be
asserted at the same time to change the
state
• D ff has 1 input D (DATA), which sets the ff
when D = 1 and resets it when D = 0
• T ff has1 input T (Toggle), which forces the
ff to change states when T = 1
• SR ff has 2 inputs, S (set) and R (reset)
that set or reset the output Q when
asserted
Gated D-Latch
• Ensures S and R inputs never equal to 1 at the
same time
• Useful in control application where setting or
resetting a flag to some condition is needed
• Stores bits of information
• Constructed from a gated SR latch and a Data
latch
D Flip-Flop
D Q+
0 0
1 1
Characteristics :
Q+ = Next State
Synchronous
Avoids the instability of RS flip-flop
Retains its last input value
To set the ff, place 1 on D input and pause the CK input
To reset, place 1 on D input and pause the CK input
JK – Flip Flop
J – Set
K – Reset
J = K = 0 – output does not change
J = K = 1 – invert the outputs
Clocked JK – Flip Flop
T Flip-Flop
T
D
SET
CLR
T
0
1
T = 1 force the state change
T = 0 state remain the same
Q
Q
Q+
Q
Q’
D and JK Flip-Flop
D
SET
CLR
J
K
SET
CLR
Q
Q
Q
Q
Q+
0
1
D
0
1
J
K
Q+
0
0
1
1
0
1
0
1
Q
0
1
Q’
How to use JK to implement D Flip-Flop
D
Q+
0
1
0
1


D
J
0
0
1
1
K
0
1
0
1
Q+
Q
0
1
Q’
D ff’s property:
When in = 0, the out(Q+) = 0.
When in = 1, the out(Q+) is 1
 invert K
 invert K
J
K
SET
CLR
Q
Q
How to use JK to implement T Flip-Flop
J
0
0
1
1
T
0
1
K
0
1
0
1
Q+
Q
0
1
Q’
Q+
Q
Q’
T ff’s property:
When in = 0, the out(Q+) = no change
When in = 1, the out(Q+) is = complement
 No change
 State change
J
SET
Q
T
K
CLR
Q
How to use D to implement JK Flip-Flop
J
0
0
1
1
D
0
1
K
0
1
0
1
Q+
Q
0
1
Q’
Q+
0
1
KQ
J
0
1
00
01
11
10
0(Q) 1(Q) 0
0
1
1
0(Q’) 1(Q’)
(Q ) = no state change
(Q’) = state change
D = JQ’ + K’Q
How to use D to implement JK Flip-Flop
D = JQ’ + K’Q
J
D
SET
Q
K
CLR
Q
How to use T to implement JK Flip-Flop
J
0
0
1
1
T
0
1
K
0
1
0
1
Q+
Q
0
1
Q’
Q+
Q
Q’
J
0
1
KQ 00
01
11
10
0
1
0
0
1
1
0
1
T = KQ + JQ’
How to use T to implement JK Flip-Flop
T = KQ + JQ’
T
D
SET
CLR
Q
Q
How to use D to implement T Flip-Flop
Q+
D
0
1
Q+
0
1
T
0
1
Q+
Q
Q’
T0
1
0 1
0 1
1 0
D = TQ’ + T’Q
How to use D to implement T Flip-Flop
D = TQ’ + T’Q
T
D
SET
CLR
Q
Q
How to use T to implement D Flip-Flop
T
0
1
D
0
1
Q+
Q
Q’
Q+
0
1
D
0
1
Q+ 0
1
0
1
1
0
T = DQ’ + D’Q
How to use T to implement D Flip-Flop
T = DQ’ + D’Q
T
D
SET
Q
D
CLR
Q
SR-Flip Flop
S
R
Q
Q’
0
1
0
1
0
0
1
1
Q
1
0
0
Q’
0
1
0
S
R
Q
Q’
1
0
1
0
1
1
0
0
Q
1
0
1
Q’
0
1
1
SET
RESET
SET
RESET
SR-Flip Flop
• Asynchronous
• If S=0 and R=1, Q is set to 1, and Q’ is
reset to 0
• IF R=0 and S=1, Q is reset to 0, and Q’
is set to 1
• If S=1 and R=1, Q and Q’ maintain their
previous state
• If S=0 and R=0, a transition to S=1,
R=1 will cause oscillation
S
R
SET
CLR
Q
Q
Clocked SR Flip-Flop
Similar to SR Flip-flop but
with extra control input C,
which enables or disables
the operation of S and R
inputs.
C=1 Enabled
S
R
SET
CLR
Q
Q
C=0 Disabled,
circuit persists in
preceding state
Instability
• RS flip-flops can become unstable if both
R and S are set to 0
• All sequential elements are fundamentally
unstable under certain conditions
– Invalid transitions
– Transitions too close together
– Transitions at the wrong time
Edge and level-triggered Flip Flop
• Digital circuit often form loops, flip-flops
oscillations can
• Oscillation will not occur because by
the time an output change cause an
input change, the activating edge of the
CK signal will be gone
• Positive edge triggered – ff responds to
a positive going edge of clock
• Negative edge triggered – responds to
a negative-going edge
Positive-edge-triggered D Flip-Flop
When CLK=0 the
master latch is open
and the content of D is
transferred to QM
When CLK=1 the
master is closed and
its output is transferred
to the slave
Master and slave
latches are never
enabled at the same
time
References
• www.play-hookey.com/digital
• www.infopad.eecs.berkeley.edu/~icdesign/
SLIDES/slides6.pdf
• www.cs.mun.ca/~paul/cs3724/material/we
b/notes/node14.html
• Dos Reis, Assembly Language and
Computer Architecture Using C++ and
Java