Convex Delay Models for
Transistor Sizing
Mahesh Ketkar, Kishore Kasamsetty, and
Sachin Sapatnekar
June 8, 2000
Outline

Introduction

Generalized posynomials

Delay estimation

Precharacterization of a set of primitives

Primitive and gate validation

Optimization using
generalized posynomial models

Conclusion and future directions
Introduction
Transistor sizing: An important problem in the
development of high performance circuits.
Key Point: Quality of solution depends on the models
used for delay and area/power estimation.
The models used should possess two properties
• Accuracy acceptable in the current
deep sub-micron (DSM) technologies.
• Suitability for continuous optimization techniques,
and preferably convexity.
Contribution: Development of delay models having
acceptable accuracy and convexity properties.
Convex optimization
Convex Programming problem:
min
f ( x)
such that
gi ( x)  0, 1  i  m, x  R n
where f(x) and gj(x)  0, 1  j  m, are convex functions.
For a convex function secant joining two points
lies above the function.
f(x)
Every Local minimum is
also a global minimum.
Convex
function
x2 x
x1+(1- )x2
x1
Y
Use of a convex function avoids any hill climbing efforts.
Posynomial functions
A posynomial function is defined as
n
ij
p( x)    j  xi , ij  R,  j  R 
j
i 1
Advantage:
A posynomial function can be converted to a convex
function by the transformation xi = ezi provided xi  0.
For Example: Elmore delay given by the equation
n
n b
xi
D( x)   ij
  i  K has the posynomial form.
xj
i, j 1
i 1 xi
Refer: Fishburn, ICCAD 85
Existing delay models
1. Elmore Delay Model [Elmore,JAP48. Rubinstein,TCAD83]
• Posynomial form , continuous derivative
• Inaccurate for current DSM technologies
2. Closed form expressions
a) Analytical Models [Chatzigeorgiou,TCAD99]
• Accurate
• Lack of convexity properties
b) Fitted Models
• May not have continuous derivative
• Lack of convexity properties
3. Look-Up table models [Rao, ICCD83]
• No continuous derivative
• Accuracy depends on the fineness of grid.
Hence, there is a trade-off between memory
requirement and accuracy.
Generalized posynomial
Motivation:
What we want?
Functions with convexity properties.
Which type of functions have convexity properties?
Posynomials
So, can we extend posynomials and still retain
convexity property?
Yes!
What have we got?
A class of functions called generalized posynomials.
Posynomials form a proper subset of the class
functions we have developed.
Generalized posynomial (Contd.)
A generalized posynomial function is defined recursively
as follows:
1. A generalized posynomial of order, G0, is defined as
n
ij
G0 ( x)    j  xi , ij  R,  j  R 
j
i 1
Note: G0 is a regular posynomial.
2. A generalized posynomial of order k  1 is defined as
n
ij
Gk ( x)    j  [Gk 1,i ( x)]
j
i 1
, ij  R  ,  j  R 
For Example: 4(x2.5+y-2+z3)0.3(x-0.5y0.4+x0.3y3)0.6
is a first order generalized posynomial.
Delay estimation
rise
wp1
Characterization variables:
Parameters with visible effect on delay.
wp2
wn1
wn2
CL
Loading capacitance (CL),
Input transition time (rise),
Transistors on the resistive path (wn1, wn2),
Width of the opposing transistor (wp1).
Generalized posynomial function that lead us to
maximum accuracy has the form
m
n
j 1
i 1
Delay   Pj  ( xi  Cij )
ij
C
xi’s: characterization variables (CL, rise, wn1, wn2, wp1),
Pj,Cij,ij, and C: characterization constants.
Posynomial model for full custom design
Generation of posynomial delay models for every
possible gate has two problems:
1. Exponential increase in number of SPICE data points,
2. Number of delay models may be prohibitively large.
Solution:
• Develop a set of primitives
• Each gate mapped to a primitive.
Primitives for simple gates
Gates which will be mapped to this primitive.
1. Inverter (Direct mapping)
2. NAND gate for RISE delay.
Inverter
Primitive
(Rising Output)
Contribute
to output
capacitance.
Primitives for simple gates (Contd.)
Gates which will be mapped to this primitive.
1. Inverter (Direct mapping)
2. NOR gate for FALL delay.
Inverter
Primitive
(Falling Ouput)
0
0
0
Contribute
to output
capacitance.
0
Primitives for simple gates (Contd.)
Complete set of primitives for simple gates
PrimFallA
PrimRiseA
PrimCoFall
0
1
1
PrimFallB
1
PrimRiseB
PrimCoRise
0
1
0
0
Primitives for complex gates
Additional primitives are necessary to accurately
consider internal node capacitances on the
nonconducting transistor chain.
Pull Up
Out
1
1
1
0
Charged Internal capacitances.
These would be neglected if
simple gate primitives are used.
Primitives for complex gates (Contd)
Additional primitives are necessary to accurately
consider internal node capacitances on the
nonconducting transistor chain.
Primitives for simple gates can be easily extended to
accommodate complex gates.
An example:
1
1
0
The nonconducting chain can be
replaced by a single conducting
transistor followed by an OFF
(nonconducting) transistor.
If this accuracy is not acceptable
more models can be developed.
Primitive for sequential element
A static sequential element consists of a set of pass
transistors and a few inverters.
An example sequential element
Primitive
Only one more primitive, channel-connected-component
formed by inverter followed by pass transistor logic.
Additional advantage:
• Facilitates simultaneous transistor sizing and clock
skew optimization
Results of primitive development
Why primitive validation?
accurately model the nonlinearities.
Characterization, validation on a disjoint data set.
Criteria used: mean error and deviation.
1. Mean error:
Acceptable fit
Error < 2% for simple gates
Error < 8% for complex gates
Example: inverter primitive - mean error = 0.31%.
Results on primitives (Contd.)
2. Deviation
Very small value of deviation is desirable for
predicting behavior of the circuit accurately.
Acceptable deviation < 5%
25
20
Example:
PrimFallB
Mean error: 1.07%.
Deviation: 2.95%.
15
10
5
0
-9 -7 -5 -3 -1
1
3
% error 
5
7
9
Results of gate validation
Gate validation shows
1. we can accurately model delay of all kinds of
static gates,
2. accuracy of the mapping procedure.
Same two criteria used.
All possible mappings for a gate are considered.
Example:
NAND3 (Fall Delay)  PrimFallA,
PrimFallB,
PrimCoFall
NAND3 (Rise Delay)  InvRise
Nand3 validation
1
PrimFallA
1
wp1
wp1
wn1
CL
wn1 CL + Cdp2,3
1 wn2
1
1 wn3
1
weq
Weq = Wn3*wn2/(wn3+wn2)
wp2
InvRise
1
CL
1
wn2
1
wn2
Ceq
Ceq = CL + Cdp1,2+ Cdn1,2 + Csn1
Results of NAND3 validation
To give an example,
Consider mapping to PrimCoFall.
Mean Error: 1.26%.
Deviation: 2.29%.
35
% points 
30
25
20
15
10
5
0
-9
-7
-5
-3
-1
1
3
% error 
5
7
9
Computational Efficacy of the model
A TILOS-like optimizer is used.
One transistor on the critical path is updated in each
iteration.
ISCAS85 circuits are optimized for target delay
varying from 70% to 95% of unsized delay.
All the execution times are less than 10 minutes.
Accuracy of delay model is also tested for the whole
circuit.
C17 benchmark  Optimization 
Comparison with SPICE.
Conclusion and future work

Introduced a new class of functions called
generalized posynomials which are shown to
possess convexity properties.

Convex and accurate delay models for various
kinds of static gates. Errors within acceptable limit
(<5%).

Computational efficacy shown by optimizing
ISCAS85 benchmark circuits.

Generalized posynomials can be used for
modeling not only delay but other circuit
parameters like short-circuit power etc.
Thank You!