CSCE 489-689 Quiz -1
(Each question carries equal weight; Keep your answer brief.)
1. Assume that you have 24 bit address. 64KB cache. 16 Byte lines. Segregate address bits into
offset, index and tag as necessary and explain what each segment is responsible for. Write
your answer for following configurations.
a. Direct mapped cache
b. 2 way set associative
c. 4 way set associative
2. The following cache represents a 2-way set associative cache, i.e., there are two lines per set.
Notice that the set ID values start at 011011012 and increment every other row. There are 14
bits for the tag, 8 bits for the set id, and 2 bits for the word id. Answer the following 3
questions based on this cache.
a. A copy of the data from memory address 5A49CA (HEX) is contained in the portion of the
cache shown above. What data will be retrieved from that address? Give your answer in
HEX format.
b. What is the minimum and maximum number of unique tags that could be contained in
this cache?
c. What percentage of the total memory space (as defined by the full memory address
width) can be held in the cache system defined above?
3. The simple, bus-based multiprocessor illustrated in the following figure represents a symmetric
shared-memory architecture. Each processor has a single, private cache with coherence maintained
using the snooping coherence protocol. Each cache is direct-mapped, with four blocks each holding
two words. To simplify the figure, the cache-address tag contains the full address and each word
shows only two hex characters, with the least significant word on the right. The coherence states are
denoted M, E, S and I for Modified, Exclusive, Shared and Invalid.
For each part of this exercise, assume the initial cache and memory state is as illustrated in the below
figure. Each part of this exercise specifies a sequence of one or more CPU operations of the form:
P#: <op> <address> [<-- <value>]
Where P# designates the CPU (e.g. P0), <op> is the operation, <address> denotes the memory
address, and <value> indicates the new word to be assigned on a write operation.
Treat each action as independently applied to the initial state. What is the resulting state (i.e.
coherence state, tags and data) of the caches and memory after the given action? Show only blocks
that change, e.g.: P0.B0: (I, 120, 00 01) indicates that CPU P0’s block B0 has the final state of I, tag of
120 and data words 00, 01. Also, what value is returned by each read operation?
a. P0: read 128
b. P0: write 128  80
c. P15: write 108  80
d. P1: read 108
e. P0: write 138  48
f.
P1: write 138  78
g. P15: write 110  78
4. Suppose we have an 8-way set with resident blocks denoted by letters as shown in the picture
below. Show the content of the set after each of the following access pattern:
AB
A  D  K. Assume LRU replacement mechanism. Show the LRU count of all ways after each
access. [Hint: After the 1st access (A), the LRU values remain unchanged as shown below; after
the 2nd access (B) the LRU count for B will become 7 and A will go down to 6 as shown below;
at this point think about the LRU count for other ways, then fill the entries for remaining
accesses.
INITIAL
A
B
A
Block LRU
Block LRU
Block LRU
A
7
A
7
A
6
B
3
B
3
B
7
C
2
C
2
C
D
6
D
6
D
E
5
E
5
E
F
1
F
1
F
G
4
G
4
G
H
0
H
0
H
Block LRU
D
Block LRU
K
Block LRU
5. A 2-way SMP configuration implements write-back cache using the MESI (Modified Exclusive Shared
Invalid) algorithm for cache coherency. Each processor has 16 megabytes of addressable memory and
a 2-way set-associative write-back cache with 256 sets and 16 bytes per line. The Pseudo-LRU
replacement policy is used. Assume that each cache is empty when we start executing programs on
the two processors, and they make the following sequence of references. Generate the tables as
shown below to give the tag, set, line number, MESI state, and data for non-empty cache lines, and
the contents of memory after each step of the sequence. Be sure to fill in the complete contents of
occupied cache lines and memory at each step. Use hexadecimal notation for all numbers.
e.g.: Processor 0 writes 1111 to location 8C34
Continuing with the example’s state table, update the table for below operations
a. Processor 0 reads from location 7C34
b. Processor 1 writes 2222 to location 8C30
c. Processor 1 reads from location 7C34
d. Processor 1 reads from location 9C38
e. Processor 0 reads from location 8C3C