ECE2030
Introduction to Computer Engineering
Lecture 20: Datapath and Microcode Control
Prof. Hsien-Hsin Sean Lee
School of Electrical and Computer Engineering
Georgia Tech
ISA Implementation
• Putting everything together
• A Datapath Unit
– Register File  A Collection of Registers
– Operation Control
•Decoding Instruction
•Generating Control Signals to Orchestrate Hardware
– Functional Units
•Arithmetic Units
•Logical Units
•Memory Units
2
2
Register File (32 32-bit Registers)
Data In
0
1
2
Reg
encoding
En
3
31
30
31
Write
Data Out
0
w
32-bit register R0
w
32-bit register R1
w
32-bit register R2
w
32-bit register R30
w
32-bit register R31
0
1
2
Reg
encoding
En
read
30
31
Read
3
Register File with Multiple Ports
5
Clock
32
Zwa
5
Xra
RegFile
Zdi
5
Yra
Ydo
Xdo
we
32
32
• Xra: X read address
• Yra: Y read address
• Xdo: X data out
• Ydo: Y data out
• Zwa: Z write address
• Zdi: Z data in
• we: write enable
• This register file has
– 2 read ports
– 1 write port
– 32 registers, each 32-bit
4
4
Adder/Subtractor Unit
32
Carry in
En
32
A
B
ā/s
AU
0: add
1: subtract
32
Flags Carry F
Overflow out
Zero flag
5
5
Logical Unit
32
32
A
B
LF
LU
En
4
32
F
A
B
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
F11
F12
F13
F14
F15
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
AB
A
A·B
6
B
B
A+B
A+B
Ā
A·B
AB
6
Logical Unit Bit Slice Implementation
0
0
0
1
1
LF0
LF1
LF2
4-to-1
Mux
LF3
An
7
Bn
An·Bn
0
0
1
LF0
LF1
LF2
4-to-1
AnBn
Mux
LF3
An
Bn
7
Logical Unit Bit Slice Alternative
An Bn
0
1
LF0
LF1
4-to-16
6
Decoder
LF2
LF3
15
Fn
8
8
Shift Unit
• B = shift amount
• Shift Type (ST)
32
32
A
En
B
ST
SD
SU
32
F
9
2
–
–
–
–
00 = no shift
01 = logical shift
10 = arithmetic shift
11 = rotate
• Shift Direction (SD)
– 0 = left
– 1 = right
9
Combined with Register File
5
Clock
32
Zwa
5
Xra
5
Yra
RegFile
Zdi
Ydo
Xdo
32
32
we
32
Cin
32
A
AU
En
Datapath
Flags
10
B
ā/s
32
Cout
10
Single Cycle Datapath
5
Clock
32
Zwa
Zdi
5
Xra
RegFile
5
Yra
32
Ydo
32
Xdo
we
Cin
A
AU
En
32
11
B
Flags
ā/s
A
B
LU
LF
A
B
ST
SU SD
Cout
11
Arithmetic and Logic Unit (ALU)
Cin
A
B
AU
En
Flags
A
ā/s
LU
A
LF
B
ST
SU SD
Cout
32
32
A
00:
01:
10:
11:
B
AU
2
LU
SU
disable ALU
ALS
ALU
B
ā/s
LF
ST
SD
4
2
I omit some input/output e.g.
carry, flags etc.
12
12
Single Cycle DataPath
5
Clock
32
Zwa
5
Xra
RegFile
Zdi
5
Yra
Ydo
Xdo
we
32
32
32
32
A
2
ALS
B
ā/s
LF
ALU ST
SD
4
2
32
13
13
DataPath with Immediate Input
Clock
32
Sign-extended
immediate
Immediate
5
5
5
32
Enable
1
Zwa Xra Yra
32
0
Ydo
RegFile
32
Zdi
Xdo
we
32
A
2
ALS
32
B
ā/s
LF
ALU ST
SD
4
2
32
14
14
DataPath with Memory
Clock
32
5
5
5
Zwa Xra Yra
Ydo
RegFile
Xdo
Zdi
Sign-extended
immediate
st enable
32
32
msel
r/w
1
Memory
0
32
we
Address
32
32
A
B
ā/s
2
ALS ALU LF
ST
SD
4
2
32
load $Z, ($X)
Data
ld enable
store $Y, ($X)
15
15
Instruction Execution
• Instruction Fetch
– Given a PC address
– Retrieve instruction from memory (or cache)
• Instruction Decode
– Instruction type, operands, etc.
– Control signals
• Instruction Execute
– Functional unit binding
• Instruction Complete
– Writeback to register or memory
• Can be done in single cycle or multiple cycles
– Instruction complexity (CISC vs. RISC)
– Pipelining
16
16
Microcode Sequencer
• For a multi-cycle implementation or a CISCy ISA
– Think about an x86 “string copy” instruction
• An ISA instruction is translated into several
microinstructions or microcode
• These microinstructions
– One per cycle
– Harness the detailed signals inside a processor
– Define low-level control signals in a given state
• Microcode Sequencer
– A finite state machine
– Generate microinstruction sequence
• Most of RISC instructions is one-to-one mapping
• Could be implemented as a ROM or a PLA
17
17
Microcode Memory
Microcode Memory
(ROM or PLA)
Datapath
Control
Signals
Combinational Logic
Instruction
Register
18
State register
Needed for a multi-cycle
instruction implementation
18
Microcode Memory
Microcode Memory
(ROM or PLA)
Datapath
Control
Signals
Combinational Logic
Instruction
Register
19
Our Single-Cycle Microcode Memory
 Assume all steps finish within one cycle
 No state needed
 Not really a microcode sequencer
19
A Simple Processor
32
Program Counter
Instruction Register
Microcode
Memory
(Single-Cycle
Implementation)
20
32
X 5
Y 5
Z 5
imm 16
imm_en
we
ALS 2
ā/s
LF 4
ST 2
SD
ld_en
st_en
ṝ/w
msel
32
Next
PC gen
32
Memory
Single Cycle
Datapath
20
A Simple Processor
add $4, $3, $2
31
26 25
21 20
16 15
11 10
6
5
0
0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0
rs
opcode
rt
rd
shamt
funct
X=00011
Y=00010
Z=00100
imm=0
Microcode
Memory
imm_en=0
we=1
ALS=00
ā/s=0
LF=0000
ST=00
SD=0
ld_en=0
Memory
Single Cycle
Datapath
st_en=0
ṝ/w=0
msel=0
21
21
Datapath Control Signals
Clock
32
5
5
5
Zwa Xra Yra
Sign-extended
immediate
Ydo
RegFile
Zdi
we
Xdo
32
32
imm enable
st enable
1
0
32
Address
32
A
22
Shift Type (ST)
00: No Shift
01: Logical
10: Arithmetic
11: Rotate
r/w
Memory
B
32
ā/s
00: AU 2
LF
ALS
ALU
ST
01: LU
SD
10: SU
11: Disable ALU
32
Logical Flag
0001: AND
0011: A
0101: B
0110: XOR
0111: OR
msel
4
2
Data
ld enable
Shift Direction (SD)
0: Left
1: Right
22
Microcode Control (1)
• Clear memory location 100, 104 (r0 hardwired to 0)
Datapath Control Signals
instruction
sequence
X (5)
Y (5)
Z (5)
w
e
Imm_en
Imm_val
ALS
ā/s
LF
ST
SD
ld_en
st_en
ṝ/w
msel
li r1,100
sw r0, (r1)
addi r1,r1,4
sw r0, (r1)
ALS
00: AU
01: LU
10: SU
11: Disable ALU
23
Logical Flag (LF)
0001: AND
0011: A
0101: B
0110: XOR
0111: OR
Shift Type (ST)
00: No Shift
01: Logical
10: Arithmetic
11: Rotate
Shift Direction (SD)
0: Left
1: Right
23
Microcode Control (1)
• Clear memory location 100, 104 (r0 hardwired to 0)
instruction
sequence
X (5)
Y (5)
Z (5)
w
e
Imm_en
Imm_val
ALS
ā/s
LF
ST
SD
ld_en
st_en
ṝ/w
msel
li r1,100
x
x
00001
1
1
0x0064
01
x
0101
x
x
0
0
x
0
sw r0, (r1)
00001
00000
x
0
0
x
11
x
x
x
x
0
1
1
1
addi r1,r1,4
00001
x
00001
1
1
0x0004
00
0
x
x
x
0
0
X
0
sw r0, (r1)
00001
00000
x
0
0
x
11
x
x
x
x
0
1
1
1
ALS
00: AU
01: LU
10: SU
11: Disable ALU
24
Logical Flag (LF)
0001: AND
0011: A
0101: B
0110: XOR
0111: OR
Shift Type (ST)
00: No Shift
01: Logical
10: Arithmetic
11: Rotate
Shift Direction (SD)
0: Left
1: Right
24
Microcode Control (2)
• copy 4-byte data from 0xF000 to 0xA100
• clear data at 0xF000
instruction
sequence
X (5)
Y (5)
Z (5)
w
e
Imm_en
Imm_val
ALS
ā/s
LF
ST
SD
ld_en
st_en
ṝ/w
msel
li r5, 0xF000
lw r6, (r5)
li r7, 0xA100
sw r6, (r7)
sw r0, (r5)
ALS
00: AU
01: LU
10: SU
11: Disable ALU
25
Logical Flag (LF)
0001: AND
0011: A
0101: B
0110: XOR
0111: OR
Shift Type (ST)
00: No Shift
01: Logical
10: Arithmetic
11: Rotate
Shift Direction (SD)
0: Left
1: Right
25
Microcode Control (2)
• copy 4-byte data from 0xF000 to 0xA100
• clear data at 0xF000
instruction
sequence
X (5)
Y (5)
Z (5)
w
e
Imm_en
Imm_val
ALS
ā/s
LF
ST
SD
ld_en
st_en
ṝ/w
msel
li r5, 0xF000
X
X
00101
1
1
0xF000
01
X
0101
X
X
0
0
X
0
lw r6, (r5)
00101
X
00110
1
0
X
11
X
X
X
X
1
0
0
1
li r7, 0xA100
X
X
00111
1
1
0xA100
01
X
0101
X
X
0
0
X
0
sw r6, (r7)
00111
00110
X
0
0
X
11
X
X
X
X
0
1
1
1
sw r0, (r5)
00101
00000
X
0
0
X
11
X
X
X
X
0
1
1
1
ALS
00: AU
01: LU
10: SU
11: Disable ALU
26
Logical Flag (LF)
0001: AND
0011: A
0101: B
0110: XOR
0111: OR
Shift Type (ST)
00: No Shift
01: Logical
10: Arithmetic
11: Rotate
Shift Direction (SD)
0: Left
1: Right
26
Microcode Control (3)
• Perform r2 = 5 *(r2 – 2*r3) + 3*r4
• store r2 to location stored in r10
instruction
sequence
X (5)
Y (5)
Z (5)
w
e
Imm_en
Imm_val
ALS
ā/s
LF
ST
SD
ld_en
st_en
ṝ/w
msel
sll r3, r3, 1
sub r2, r2, r3
sll r5, r2, 2
add r2, r5, r2
sll r6, r4, 1
add r4, r6, r4
add r2, r2, r4
sw r2, (r10)
ALS
00: AU
01: LU
10: SU
11: Disable ALU
27
Logical Flag (LF)
0001: AND
0011: A
0101: B
0110: XOR
0111: OR
Shift Type (ST)
00: No Shift
01: Logical
10: Arithmetic
11: Rotate
Shift Direction (SD)
0: Left
1: Right
27
Microcode Control (3)
• Perform r2 = 5 *(r2 – 2*r3) + 3*r4
• store r2 to location stored in r10
instruction
sequence
X (5)
Y (5)
Z (5)
w
e
Imm_en
Imm_val
ALS
ā/s
LF
ST
SD
ld_en
st_en
ṝ/w
msel
sll r3, r3, 1
00011
X
00011
1
1
0x0001
10
X
X
01
0
0
0
X
0
sub r2, r2, r3
00010
00011
00010
1
0
X
00
1
X
X
X
0
0
X
0
sll r5, r2, 2
00010
X
00101
1
1
0x0002
10
X
X
01
0
0
0
X
0
add r2, r5, r2
00101
00010
00010
1
0
X
00
0
X
X
X
0
0
X
0
sll r6, r4, 1
00100
X
00110
1
1
0x0001
10
X
X
01
0
0
0
X
0
add r4, r6, r4
00110
00100
00100
1
0
X
00
0
X
X
X
0
0
X
0
add r2, r2, r4
00010
00100
00010
1
0
X
00
0
X
X
X
0
0
X
0
sw r2, (r10)
01010
00010
X
0
0
X
11
X
X
X
X
0
1
1
1
ALS
00: AU
01: LU
10: SU
11: Disable ALU
28
Logical Flag (LF)
0001: AND
0011: A
0101: B
0110: XOR
0111: OR
Shift Type (ST)
00: No Shift
01: Logical
10: Arithmetic
11: Rotate
Shift Direction (SD)
0: Left
1: Right
28
Instruction Fetching (PC Update)
Next PC
generation
Program Counter
Instruction Register
32x32
RegFile
29
Datapath
32
32
addr
Memory
data
Microcode ROM
29
Sequential Instruction Fetch
4
+
Program Counter
Instruction Register
32x32
RegFile
30
Datapath
32
32
addr
Memory
data
Microcode ROM
30
Branch Support
Offset (from ROM)
ext
4
beq 1 mux 0
bne
(if true)
+
Program Counter
Instruction Register
32x32
RegFile
31
Datapath
32
32
addr
Memory
data
Microcode ROM
31
Branch and Jump Support
rs
ext
ext
jr/j
mux
0
jr
j
4
beq 1 mux 0
bne
(if true)
+
Target addr
(from ROM)
1
Offset (from ROM)
1 mux 0
Program Counter
Instruction Register
32x32
RegFile
32
Datapath
32
32
addr
Memory
data
Microcode ROM
32