Outline
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Finite Settling Time Design
M. Sami Fadali
Professor of Electrical Engineering
UNR
Control system synthesis.
Finite settling for DT systems.
Finite settling time controllers.
Deadbeat controllers.
Example.
Intersample behavior.
1
Control System Synthesis
2
Solve for the Controller
• Desired closed loop transfer function
is known.
• Select a controller
to achieve the
desired closed-loop transfer function.
R(z)
E(z)
+
U(z)
C(z)
Y(z)
must be realizable and must yield
an asymptotically stable system.
GZAS(z)

3
4
Causality
Non-minimum Phase Plant
• For a non-minimum phase plant zero at
• Causal controller must have
– More than or as many poles as zeros.
– No time advance.
• Closed-loop and plant TFs must have the same
(i) Pole-zero deficit (ii) Time delay.
• No unstable pole-zero cancellation for
asymptotic stability.
• Closed-loop zero at
5
Unstable Plant
6
Zero Steady-state Error
• For an unstable plant pole at
• For a unit step input, the steady-state
output is
Lim
→
• For zero steady-state error due to step
• No unstable pole-zero cancellation for asymptotic
stability.
• Zero at for
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8
Summary:
Constraints
Pole-zero Matching
• Analog filter with transfer function
• Closed-loop and plant: same pole-zero
deficits and time delays.
• Unstable plant zeros must be closedloop zeros (
zeros).
• Unstable plant poles must be zeros of
• Digital filter transfer function
• For zero steady-state error due to
step,
constant selected for equal filter gains at
a critical frequency (match DC gains for LPF)
9
10
MATLAB: Pole-Zero Matching
Procedure 6.3
>> wn=5; zeta=0.5;
>> ga=tf([wn^2],[1,2*zeta*wn,wn^2]); % Analog TF
>> g=c2d(ga,.1,'matched') % Pole-zero matching
Transfer function:
0.09634 z + 0.09634
----------------------------z^2 - 1.414 z + 0.6065
Sampling time: 0.1
• Select the desired settling time and the
desired overshoot.
• Select a suitable continuous-time 1st or 2nd
order closed-loop transfer function with unit
gain.
using pole-zero matching.
• Obtain
• Verify that
meets the conditions for
causality, stability, and steady-state error. If
not, modify
until the conditions are met.
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12
Solution
Example
Design a digital controller for the DC motor
speed control system with analog plant
transfer function to obtain:
(i) zero steady-state error due to a unit
step, and (ii) a settling time of about 4 s.
s.
Use
Z
• No poles or zeros outside the unit circle.
• Pole-zero difference =1.
• Choose closed-loop poles (2nd order) for
• Gain for zero steady-state error due to step.
13
MATLAB
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Solution (Cont.)
• Desired closed-loop transfer function
• Use pole-zero matching to get
• Desired Controller (calculate with MATLAB)
• Zero at 1 for a pole-zero difference of
1 like
[Ps=tf(1.322,[1 2.024 1.322])
[Pz=c2d(Ps,0.02,'matched')
15
16
Step Response
Finite Settling Time
Step Response
• CT systems: asymptotically (infinite time) settle
at the desired output.
• DT systems: can settle at the reference output
after a finite interval then follow it exactly.
• Finite settling time designs may exhibit
undesirable inter-sample behavior and must be
carefully checked before implementation.
• Use synthesis approach to obtain the desired
controller for finite settling time.
1
System: gcl
Settling Time (sec): 3.71
Amplitude
0.8
0.6
0.4
0.2
0
0
1
2
3
4
5
Time (sec)
6
17
Deadbeat Controller
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Example 6.22
• Finite settling time control
• Desired closed-loop transfer function
Design a deadbeat controller for the DC
motor speed control system with transfer
function
1. Use a sampling period T=0.02 s.
2. Redesign the controller with T=0.1 s.
• Simple design: only design parameter is the
sampling period T
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Solution
Sampled and analog step response for
deadbeat control of Example 6.22 (T=0.02 s)
• Discretized process transfer function
1.5
Z
1
process output
• No poles or zeros outside or on the unit circle.
• Can design a deadbeat controller.
0.5
21
Control variable for deadbeat control of
Example 6.22 (T=0.02 s)
0
0
0.2
0.4
0.6
0.8
1
time [s]
1.2
1.4
1.6
1.8
2
22
Deadbeat Control
4
1
x 10
• Large gain may saturate DAC.
• Controller causes inter-sample
oscillations.
• Controller is much worse than the error at
the sampling points would indicate.
0.8
0.6
control variable
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
0
0.2
0.4
0.6
0.8
1
time [s]
1.2
1.4
1.6
1.8
2
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Intersample Behavior
Analog Output
• Use transfer function of ZOH.
• Use block diagram manipulation.
• Consider the system with analog output
R(s) T
R*(s)
U*(s)
*
E (s)
+

Y(s)
GZOH(s)
C*(s)
∗
∗
G(s)
∗
∗
T
∗
*
Y (s)
T
∗
∗
∗
Block diagram for finite settling time design
with analog output.
∗
∗
∗
25
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Analog Output Expansion
Step Response:
•
∗
∗
Partial fraction expansion
∗
∗
27
28
Inter-sample oscillations with
deadbeat control
Limitations of deadbeat control
1- Minimum phase transfer function
(i.e. all
zeros inside the unit circle), since its zeros are
controller poles.
2-Controller may require excessively high gains
that cause DAC saturation.
3-Intersample oscillations of system analog output.
Lesson from finite settling time designs:
Check analog output of digital control system for
satisfactory intersample behavior.
1.4
1.2
process output
1
0.8
0.6
0.4
0.2
0
0
0.2
0.4
0.6
0.8
1
time [s]
1.2
1.4
1.6
1.8
2
• At the sampling points
but between
samples the output oscillates wildly
29
Eliminating Intersample
Oscillations
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Open-loop gain
• Obtain the expression for the control.
• Choose
and satisfy the gain condition for
)
zero steady-state error (for step,
• Fixed control and
(type 1 system) if and only if
i.
ii.
has a pole at
(zero
iii. No pole-zero cancellation
• Fix the control input after sampling points for
order system with zero error.
an
31
)
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Minimum-phase Stable Plant
Loop Gain Condition
• Loop gain
Case 1: Type 0 Plant, no pole at
For zero steady-state error
• Closed-loop transfer function
Case 2: Type I Plant, has a pole at
No controller pole at
• Assume no pole-zero cancellation
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Loop Gain and
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Zero Steady-state Error
• Loop Gain:
Case 1:
• For zero steady-state error
Case 2:
Both cases:
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Controller: Case 1
Case 1: Design Equations
• Equating coefficients gives
• Closed-loop characteristic polynomial
• Equate coefficients: solve for the controller.
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Controller: Case 2 (like Case 1)
with a pole at
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Case 2: Design Equations
• Equating coefficients gives
• Equate coefficients to solve for the
controller.
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Stability Condition:
Unstable Zeros
Stability Condition:
Unstable Poles
• Unstable plant zeros must be closed-loop
zeros
• Unstable plant poles must be zeros of
• Unstable plant poles
must not cancel:
• Unstable plant zeros must not cancel
must not include the unstable plant
zeros
41
Example 6.23
,
42
Solution
Design a ripple-free deadbeat controller for
the positioning system with transfer
function
• Discretized process transfer function
Z
• 2nd order Process: zero control after
samples
The sampling period is chosen as
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Controller Design
Step response for deadbeat control
1
process output
0.8
• Closed-loop transfer function
0.4
0.2
0.9672
0.50833
0.6
0
0
0.1
0.2
0.3
0.4
0.5
time [s]
0.6
0.7
0.8
0.9
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Example 6.25
Control variable for deadbeat control.
150
Design a deadbeat controller for the
isothermal chemical reactor
100
control variable
1
50
With a sampling period
0
s
-50
-100
0
0.1
0.2
0.3
0.4
0.5
time [s]
0.6
0.7
0.8
0.9
1
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Equate Coefficients
Solution
• Open-loop stable, non-minimum phase
• Unstable controller and plant but closed-loop
stable.
constraint
• Open-loop stable: No
.
• Non-minimum phase:
includes the zero outside the unit circle.
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50
Example 6.25: Step Response
Check Conditions
5
0
Process Output
-5
-10
-15
-20
-25
-30
-35
51
0
0.005
0.01
0.015
0.02
0.025
Time s
0.03
0.035
0.04
0.045
0.05
Sampled and analog step response for
deadbeat control
52
Example 6.25: Control Variable
4000
3000
Control Variable
2000
1000
0
-1000
-2000
-3000
-4000
0
0.005
0.01
0.015
0.02
0.025
Time s
0.03
0.035
0.04
0.045
0.05
Control variable for the deadbeat control
53