DOC/LP/01/28.02.02
LESSON PLAN
Sub Code & Name: EC2354 VLSI DESIGN
Unit : V
Branch : EC
Semester: VI
UNIT V SPECIFICATION USING VERILOG HDL
LP – EC2354
LP Rev. No: 04
Date: 30/12/14
Page 01 of 06
9
Syllabus:
Basic concepts- identifiers- gate primitives, gate delays, operators, timing controls,
procedural assignments conditional statements, Data flow and RTL, structural gate level, switch
level modeling, Design hierarchies, Behavioral and RTL modeling, Test benches, Structural gate
level description of decoder, equality detector, comparator, priority encoder, half adder, full
adder, Ripple carry adder, D latch and D flip flop.
Objective: To understand the concepts of modeling a digital system using Hardware Description
Language (HDL).
Session
No.
1.
Topics to be covered
Time
Page No
Teaching
Method
8,2
PPT
8
PPT
4.
Basic concepts- identifiers- gate
primitives, Design hierarchies
Gate delays, Operators, Timing
controls
Procedural assignments
,conditional statements
Data flow and RTL
5.
Structural gate level
50m
373
8
PPT
6.
Switch level modeling
Behavioral and RTL modeling,
Test benches
Gate level verilog code-Decoder,
equality detector, comparator,
priority encoder
Half adder, full adder, Ripple carry
adder, D latch and D flip flop.
50m
383
8
PPT
50m
385
8
PPT
50m
136
8
PPT
50m
452,414
2,4
PPT
2.
3.
7.
8.
9.
50m
50m
4748,72,106,388
121,138, 171178
Ref
50m
166,179
8
PPT
50m
131
8
PPT
DOC/LP/01/28.02.02
LESSON PLAN
Sub Code & Name: EC2354 VLSI DESIGN
Unit : I
UNIT I
Branch : EC
Semester: VI
LP – EC2354
LP Rev. No: 04
Date: 30/12/14
Page 02 of 06
CMOS TECHNOLOGY
9
Syllabus:
A brief History-MOS transistor, Ideal I-V characteristics, C-V characteristics, Non ideal
I-V effects, DC transfer characteristics - CMOS technologies, Layout design Rules, CMOS
process enhancements, Technology related CAD issues, Manufacturing issues.
Objective: To understand the MOS transistor theory, CMOS technologies and the Layout.
Session
Topics to be covered
No.
Introduction – VLSI Design, NMOS,
10.
PMOS Enhancement transistor
11.
MOS transistor-Ideal I-V characteristics
12.
MOS transistor-C-V characteristics
13.
14.
15.
16.
17.
18.
Non ideal I-V characteristics- velocity
saturation and mobility degradation,
channel length modulation, subthreshold
conduction
Threshold voltage, Body effect, Junction
leakage, Tunneling, temperature
dependence, Geometry dependence
CAT I
CMOS inverter DC characteristics, Beta
ratio effects
CMOS technology : n well, p well Twin
well, triple well,
Layout design rules-NAND, NOR gate
CMOS Process enhancement-SOI
Process, Interconnects, circuit elements:
Resistors, Capacitor, CAD and
Manufacturing issues
Time
Page No
Ref
Teaching
Method
50m
1-7, 40
1
PPT
50m
42-45
1
PPT
50m
45-51
1
PPT
50m
51-55
11
ICT
50m
55-60
1
PPT
90m
-
-
-
100m
60-65
1
PPT
9, 10
ICT
1
PPT
1,2
PPT
50m
50m
50m
83,
15-21
83-91
91-100,
107 – 109,
149
DOC/LP/01/28.02.02
LESSON PLAN
Sub Code & Name: EC2354 VLSI DESIGN
Unit : III
UNIT III
Branch : EC
Semester: VI
COMBINATIONAL AND SEQUENTIAL CIRCUIT DESIGN
LP – EC2354
LP Rev. No: 04
Date: 30/12/14
Page 03 of 06
9
Syllabus:
Circuit families –Low power logic design – comparison of circuit families – Sequencing
static circuits, circuit design of latches and flip flops, Static sequencing element methodologysequencing dynamic circuits – synchronizers
Objective: To understand the concepts of designing combinational and sequential circuit using
CMOS logic configuration.
Session
Topics to be covered
No.
19.
Circuit families-static CMOS, ratioed
circuit
20.
Cascode voltage swing logic, Dynamic
circuits
21.
Pass transistor, Differential circuits
22.
23.
24.
25.
26.
27.
Time
50m
50m
Page No
215224,342
225,361,
353
Ref
Teaching
Method
1,2
PPT
1,2,3
PPT
50m
233-240
1
PPT
BiCMOS, Low power logic design –
comparison of circuit families
50m
241-245
1
PPT
Sequencing static circuits
50m
252-265
1
PPT
Circuit design of latches and flip flops
50m
265-274
1
PPT
Static sequencing element
50m
275-283
1
PPT
Sequencing dynamic circuits
50m
284-289
1
PPT
Synchronizers
50m
289-294
1
PPT
DOC/LP/01/28.02.02
LP – EC2354
LP Rev. No: 04
Date: 30/12/14
Page 04 of 06
LESSON PLAN
Sub Code & Name: EC2354 VLSI DESIGN
Unit : IV
UNIT IV
Branch : EC
Semester: VI
CMOS TESTING
9
Syllabus:
Need for testing- Testers, Text fixtures and test programs- Logic verification- Silicon
debug principles- Manufacturing test – Design for testability – Boundary scan.
Objective: To understand the concepts of CMOS testing
Session
No.
28.
29.
30.
31.
32.
33.
34.
35.
36.
Time
Page No
Ref
Teaching
Method
Need for testing
50m
531-536
1
PPT
Text fixtures and test programs
50m
537-540
1
PPT
Logic verification- Silicon
debug principle
50m
541-544
1
PPT
Manufacturing test
50m
1,2,4
PPT
------------ do -------------
50m
1,2,4
PPT
CAT II
90m
-
-
-
Design for testability-adhoc testing
50m
548-550
1
PPT
Scan design
50m
550-555
1
PPT
Built in self test, IDDQ testing
50m
555-558
1
PPT
Boundary scan
50m
559-570
1
PPT
Topics to be covered
544,621,2
39
544,621,2
39
DOC/LP/01/28.02.02
LESSON PLAN
Sub Code & Name: EC2354 VLSI DESIGN
Unit : II
UNIT II
Branch : EC
Semester: VI
LP – EC2354
LP Rev. No: 04
Date: 30/12/14
Page 05 of 06
CIRCUIT CHARACTERIZATION AND SIMULATION
9
Syllabus:
Delay estimation, Logical effort and Transistor sizing, Power dissipation, Interconnect,
Design margin, Reliability, Scaling- SPICE tutorial, Device models, Device characterization,
Circuit characterization, Interconnect simulation.
Objective: To study the circuit characterization and performance estimation of CMOS
technology.
Session
Topics to be covered
No.
Delay estimation-RC delay model, Linear
37.
delay model
38.
Logical effort
39.
Transistor sizing
40.
41.
42.
43.
44.
45.
Power dissipation-Static and Dynamic power
dissipation
Interconnect –Estimation of resistance
capacitance, delay and cross talk
Design margin
Time
Page No
Ref
Teaching
Method
1,2
PPT
1,2
PPT
50m
111117,245
118,313
50m
118
1
PPT
50m
129-135
1
PPT
1,2
PPT
1
PPT
1
PPT
1
PPT
50m
Reliability, Scaling
50m
SPICE tutorial, Device models
Device & Circuit characterization,
Interconnect simulation
CAT III
50m
135145,525
145-148
148-159,
229
181-193
50m
193 -213
1
PPT
90m
-
-
-
50m
50m
DOC/LP/01/28.02.02
LP – EC2354
LP Rev. No: 04
Date: 30/12/14
Semester: VI Page 06 of 06
LESSON PLAN
Sub Code & Name: EC2354 VLSI DESIGN
Branch : EC
Course Delivery Plan:
Week
1
I II
2
I II
V
Unit
3
I II
4
I
II
5
I II
I
6
I II
7
I II
III
CAT I
8
I II
9
I
IV
II
10
I II
I
11
II
I
12
II
II
CAT II
CAT III
TEXT BOOKS:
1. Weste and Harris: CMOS VLSI DESIGN (Third edition) Pearson Education, 2005
2. Uyemura J.P: Introduction to VLSI circuits and systems, Wiley 2002.
REFERENCES:
3. D.A Pucknell & K.Eshraghian Basic VLSI Design, Third edition, PHI, 2003
4. Wayne Wolf, Modern VLSI design, Pearson Education, 2003
5. M.J.S.Smith: Application specific integrated circuits, Pearson Education, 1997
6. J.Bhasker: Verilog HDL primer, BS publication, 2001
7. Ciletti Advanced Digital Design with the Verilog HDL, Prentice Hall of India, 2003
8. Samir palnitkar, Verilog HDL , Pearson Education, second edition
9. www.youtube.com/watch?v=QO5FgM7MLGg
10. www.youtube.com/watch?v=SvU_c3cktSc
11. www.youtube.com/watch?v=CJuflldL5NM
12. www.nptel.ac.in
Prepared by
Approved by
Name
Ms.R.Kousalya / Ms.B.Sarala /
M.Anushya
Dr.S.Ganesh Vaidyanathan
Designation
Assistant Professor
HoD – EC
Date
30.12.2014
30.12.2014
Signature