JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.14, NO.5, OCTOBER, 2014
http://dx.doi.org/10.5573/JSTS.2014.14.5.673
Low Specific On-resistance SOI LDMOS Device with
P+P-top Layer in the Drift Region
Jia-Fei Yao, Yu-Feng Guo, Guang-Ming Xu, Ting-Ting Hua, Hong Lin, and Jian Xiao
Abstract—In this paper, a novel low specific onresistance SOI LDMOS Device with P+P-top layer in
the drift region is proposed and investigated using a
two dimensional device simulator, MEDICI. The
structure is characterized by a heavily-doped P+
region which is connected to the P-top layer in the
drift region. The P+ region can modulates the surface
electric field profile, increases the drift doping
concentration and reduces the sensitivity of the
breakdown voltage on the geometry parameters.
Compared to the conventional D-RESURF device, a
25.8% decrease in specific on-resistance and a 48.2%
increase in figure of merit can be obtained in the
novel device. Furthermore, the novel P+P-top device
also present cost efficiency due to the fact that the P+
region can be fabricated together with the P-type
body contact region without any additional mask.
Index Terms—LDMOS, D-RESUFR,
voltage, specific on-resistance, P+ region
breakdown
I. INTRODUCTION
The SOI lateral double-diffusion MOSFETs (LDMOS)
have been widely used in smart power IC due to its low
leakage current, superior isolation and high speed [1].
One of the main issues when designing power LDMOS is
the trade-off between the breakdown voltage (BV) and
specific on-resistance (Rsp) [2]. The REduce SURface
Field (RESURF) technique is the most widely used
Manuscript received Jun. 22, 2014; accepted Aug. 18, 2014
College of Electronic Science and Engineering, Nanjing University of
Posts and Telecommunications
E-mail : [email protected]
method for designing lateral high voltage and low onresistance MOS devices [3, 4], but Single RESURF (SRESURF) technique must ensure a low drift region
concentration to make the epitaxial layer deplete
completely, otherwise the high drift concentration will
lead to the PwellNdrift junction electric field premature
reaching the critical electric field of silicon, thus
reducing the breakdown voltage [5, 6]. Moreover, the
low drift concentration will also increase the specific onresistance [7]. To address the issue, the Double RESURF
(D-RESURF) concept has been introduced to improve
this performance of the SOI LDMOS [8]. Many studies
show that high breakdown voltage can be maintained,
while drift region doping concentration is increased by
about twice as much as that in S-RESURF devices,
realizing a good trade-off between the breakdown
voltage and specific on-resistance [9-17]. However, the
surface electric field distribution of the D-RESURF
device shows that a low valley value appears in the
positive-biased PtopNdrift junction near the channel, thus
leading to the breakdown voltage of the D-RESURF
device is lower than that of the S-RESURF [9].
Furthermore, according to the RESURF principle, DRESURF device is fairly strict with the charge control of
the P-top layer, and the breakdown voltage is sensitive
on the P-top layer doping concentration, length and depth,
which increases the complexity of the device design and
fabrication process invisibly [18].
In this paper, a novel low specific on-resistance SOI
+
P P-top LDMOS Device is proposed and studied by a 2D
semiconductor device simulator, MEDICI. The physical
models such as Shockley-Read-Hall recombination
model, Auger recombination model and carrier mobility
models are used in the simulation. The P+ region
674
JIA-FEI YAO et al : LOW SPECIFIC ON-RESISTANCE SOI LDMOS DEVICE WITH P+P-TOP LAYER IN THE DRIFT REGION
generates a new electric field peak in the drift region,
which modulates the drift region surface electric field
distribution and increases the optimal drift region doping
concentration. Hence the proposed device can obtain a
high breakdown voltage and a low specific on-resistance,
simultaneously. Moreover, the existence of the P+ region
reduces the sensitivity of the breakdown voltage on the
device parameters and results in the flexible design and
fabrication. The fabrication process of the P+P-top device
is the same as the conventional SOI D-RESURF
LDMOS device without any additional mask. Therefore,
the P+P-top device can lead to a significant improvement
in figure of merit and reduction in fabrication cost.
II. STRUCTURE
AND
Fig. 1. Cross-section of SOI P+P-top LDMOS device.
MECHANISM
Fig. 1 shows the cross-section of the SOI P+P-top
LDMOS device. The device is characterized by the
heavily-doped P+ region in the drift region. The P+ region
is connected to the P-top layer and the distance from P+
region to P-well area is L1, L2 is the distance from P-top
layer to drain region. LP, TP and NP+top are the length,
width and doping concentration of the P+ region, Ld, ts
and Nd are the length, width and doping concentration of
the drift region, LPtop, TPtop and NP-top are the length, width
and doping concentration of the P-top layer, respectively.
Fig. 2 compares the surface electric field and potential
distributions of the conventional D-RESURF and the
proposed P+P-top device when breakdown occurs. These
devices are optimized by a 2D semiconductor device
simulator MEDICI. From Fig. 2(a), the positive-biased
PtopNdrift junction near the channel leads to a low electric
field valley in drift region and a high electric field peak
at the PwellNdrift junction in the D-RESURF device. Such
a non-uniform surface electric field is the reason that the
conventional D-RESURF device presents a lower
breakdown voltage than the S-RESURF device [17]. Fig.
2(b) shows the results of the proposed P+P-top device
with the same structure parameters and applied voltage.
It is clear that P+ region generates a new electric field
peak at the P+Ptop junction, which increases the electric
field in the middle of the drift region and reduces the
electric field peak at the PwellNdrift junction, as shown in
Fig. 2(b). Therefore, the drift doping concentration can
be increased to obtain the more uniform distribution of
the surface electric field. Fig. 2(c) shows the surface
(a)
(b)
(c)
Fig. 2. Surface electric field and potential distributions for each
device (a) conventional D-RESURF device with an optimized
structure parameters when breakdown occurs, (b) P+P-top
device with the same structure parameters as the conventional
D-RESURF device, (c) P+P-top device with the optimized
structure parameters at breakdown.
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.14, NO.5, OCTOBER, 2014
675
potential and electric field distributions for the P+P-top
device with an optimized drift doping concentration at
breakdown. Compared to the conventional D-RESURF
device in Fig. 2(a), the optimized P+P-top device can lead
to an increased drift doping concentration from 4.5×1015
cm-3 to 7.3×1015 cm-3, and a higher breakdown voltage
from 405V to 430.8V. Thus, the P+P-top device can
obtain a better tradeoff between the breakdown voltage
and specific on-resistance than the conventional DRESURF device.
(a)
III. RESULTS
AND
DISCUSSIONS
In this section, the 2D semiconductor device simulator
MEDICI is used for investigating the influence of the
P+P-top device parameters on the device breakdown
voltage and specific on-resistance. The performance of
the P+P-top device is compared with the conventional DRESURF device.
1. Breakdown Voltage
(b)
Fig. 3 shows the variation of the breakdown voltage
with the drift doping concentration for P+P-top device
and conventional D-RESURF device. Compared to the
conventional D-RESURF device, the P+P-top device
presents a drastically increase in the optimum drift
doping concentration while keeps a same level for the
breakdown voltage, which benefits the tradeoff between
the breakdown voltage and specific on-resistance.
Furthermore, for the P+P-top device, the breakdown
voltage increases with the increase slightly of drift
doping concentration when the vertical breakdown
occurs, and shows a weak dependence on the P+ region
parameters. However, for fixed P+ region parameters, the
breakdown voltage is maximized when an optimized drift
doping concentration is used. A further increase in the
drift doping concentration leads to a rapid reduction in
the breakdown voltage because the D-RESURF
condition cannot be satisfied [17]. Fig. 3(a) shows that
the increase of P+ region depth leads to an increase of the
optimum drift doping concentration, while Figs. 3(b) and
(c) shows the distance from P-well area to P+ region and
P+ region length have to be chose carefully to obtain an
optimal drift doping concentration. The Figure shows the
optimum L1 and LP are 4 μm and 1 μm for the
(c)
Fig. 3. Optimal relationships between the breakdown voltage
and drift region concentration for (a) various P+ region depth,
(b) various distance from P-well area to P+ region, (c) various
P+ region length.
investigated device, respectively.
The electric field distributions shown in Fig. 4 can be
used for explaining the physical insight as Fig. 3 shows.
Actually, P+ region influences the breakdown
characteristics by modulating the electric field peaks at
P+Ptop and PwellNdrift junctions. But the critical electric
field of the PwellNdrift junction is higher than the P+Ptop
junction due to the difference of the curvature radius and
676
JIA-FEI YAO et al : LOW SPECIFIC ON-RESISTANCE SOI LDMOS DEVICE WITH P+P-TOP LAYER IN THE DRIFT REGION
region depth. Moreover, from Figs. 4(b) and (c), it is
clear that when L1=4 μm and LP=1 μm, the P+P-top
device can obtain a relatively uniform surface electric
field distribution, thus resulting in the maximal
breakdown voltage. For the shorter or longer L1 or LP, the
high electric field peak at the P+Ptop or PwellNdrift junctions
lead to the device premature breakdown there, thus
reducing the breakdown voltage.
2. On Resistance
(a)
For investigating the impact of P+ region on the
specific on-resistance of P+P-top device, Fig. 5 gives the
current flow line contours when the device is biased on
on-state. Obviously, the specific on-resistance can be
expressed as:
Rsp = RS + Rch + Rld + RD
(b)
(1)
where RS, Rch, Rld and RD are the resistance of the source,
channel, drift region and drain, respectively. For the high
voltage device, Rld is the key component in the four parts
of the on-resistance. Rld includes four parts: the resistance
between the channel and P+ region Rld1, under the P+
region Rld2, under the P-top region Rld3 and between the
P-top layer and drain region Rld4, as Fig. 5 shows. When
the spreading resistance is neglected, the whole drift
resistance can be written as [19]
2
LPtop
L2P
L2 ù
1 é L12
Rld »
+
+ 2ú
ê +
q m n N d ê ts （ts -TP）（ts -TPtop） ts ú
ë
û
(c)
Fig. 4. Surface electric field distributions as functions of (a) P+
region depth, (b) distance from P-well area to P+ region, (c) P+
region length when breakdown occurs for the optimized drift
doping concentration.
doping concentration. As shown in Fig. 4(a), although the
deep P+ region brings the increased electric field peak at
the P+Ptop junction, while that at the PwellNdrift junction is
almost immune to the depth of P+ region. As a result, the
breakdown voltage shows a weak dependence on the P+
(2)
where q is the electric charge, μn is the electron mobility
in silicon.
Fig. 6 compares the I-V characteristics for the
conventional D-RESURF and P+P-top device at Vgs=5V.
As it is known, pinch-off effect occurs when Vds=Vgs-Vth,
where Vth is the threshold voltage. In LDMOS, pinch-off
effect depend on the voltage at Pwell/Ndrift junction (VPN)
and occurs when VPN=Vgs-Vth. As shown in the figure,
the VPN in the P+P-top device is lower than that of the DRESURF device at the same Vds. Therefore, pinch-off
effect is negligible to the I-V characteristics of the P+Ptop device. Due to the pinch-off effect occurs at a higer
drain voltage, the saturation current of the P+P-top
device is higher than that of the conventional D-
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.14, NO.5, OCTOBER, 2014
677
(a)
Fig. 5. On-state current flowline contours.
3
6
2.5
5
2
4
1.5
3
1
2
0.5
1
0
0
0
3
6
9
12
15
(b)
Fig. 6. A comparison of on-state performance at Vgs=5V.
RESURF device. And it is clear that the linear region
resistance of the P+P-top device is much lower.
Therefore, the drain cuurent in linear and satuate region
of the P+P-top device is higher than that of the
conventional D-RESURF device.
Fig. 7 shows the variation of the figure of merit and
specific on-resistance as a function of the parameters of
the P+ region when breakdown occurs for the optimized
drift doping concentration. The key P+ region parameters
include the P+ region depth, the distance from P-well area
to P+ region and the length of P+ region. No matter
which parameter, there is an optimal value allows the
device to obtain the lowest specific on-resistance. In fact,
for the small L1, LP and TP, the optimal drift doping
concentration increases drastically with the increase of
them as Fig. 3 shows, which results in a reduction of the
specific on-resistance according to Eq. (2). However, for
the large P+ region parameters, Fig. 3 indicates that the
drift doping concentration tends to saturation. The
specific on-resistance increases with the L1, LP and TP as
(c)
Fig. 7. Figure of merit and specific on-resistance as functions of
(a) P+ region depth, (b) distance from P-well area to P+ region,
(c) P+ region length when breakdown occurs for the optimized
drift doping concentration.
shown in Eq. (2). Actually, the deep TP and long LP
means a narrow current flow channel under the P+ region,
leading to a large Rld2. Moreover, the figure of merit
(FOM=BV2/Rsp) [20] is also shown in Fig. 7 to evaluate
the performance of the device. The maximum FOM and
minimum Rsp can be obtained under the same optimal
geometric parameters of the P+ region. The reason is that
678
JIA-FEI YAO et al : LOW SPECIFIC ON-RESISTANCE SOI LDMOS DEVICE WITH P+P-TOP LAYER IN THE DRIFT REGION
the breakdown voltage shows a weak dependence on the
P+ region parameters. The FOM is dominated by the
specific on-resistance. Besides, Fig. 7 also shows the
merits of the P+P-top device compared to the
conventional D-RESURF device. The specific onresistance of the proposed device can decreases from 302
mΩ·cm-2 to 224 mΩ·cm-2, which results in a drastically
increase in FOM from 0.56 MW/cm2 to 0.83 MW/cm2.
Conventional
D-RESURF
Optimal NP-top
450
P+P-top device 350
Optimal NP-top
300
400
L1=4µm
Tp=2µm
Lp=1µm
350
250
P+P-top device
Conventional D-RESURF device
4
6
8
10
12
200
Doping concentration of P-top layer , NP-top(1015cm-3)
3. Optimization of P-top Layer
(a)
The length, depth and doping concentration of the Ptop layer are the key parameters in the D-RESURF SOI
LDMOS. Fig. 8 compares the influence of the P-top layer
parameters on breakdown voltage and specific onresistance for the conventional D-RESURF device and
P+P-top device. In the figure, the drift doping
concentration is optimized to obtain the optimal surface
electric field distribution and maximal breakdown
voltage for any given P-top layer parameters. Owing to
the modulation effect of the P+ region on the surface
electric field profile, the P+P-top device presents the high
breakdown voltage under the condition of the wider
range of the P-top layer parameters. In other words, the
breakdown voltage is insensitive on the P-top layer
parameters in the P+P-top device, which brings a
potential flexibility in design and fabrication. Moreover,
compared to the conventional D-RESURF device, the
specific on-resistance of the P+P-top device decreases
drastically. Actually, the optimal drift doping
concentration in the conventional D-RESURF device can
be calculated by [9]:
N d = N eff + h ´ N p -top , (0 £ h £ 1)
(3)
where η is the junction depth factor of the P-top layer and
Neff is equivalent doping concentration of the drift region.
They are fixed for the given geometric parameters of
drift region.
Similarly, the optimal drift doping concentration in the
P+P-top device can be modified as:
N d = N eff + h ´ N p -top + l ´ N p + top , ( 0 £ h , l £ 1) (4)
where λ is the junction depth factor of the P+ region
which is a constant when the structure parameters is
(b)
(c)
Fig. 8. Breakdown voltage and specific on-resistance as
functions of (a) P-top layer doping concentration, (b) P-top
layer length, (c) P-top layer depth when the drift doping
concentration is optimized to maximize the breakdown voltage.
given.
From Eqs. (3) and (4), it is evident that the heavier
impurity can be adopted in the drift region for the P+Ptop device due to the additional P+ region. Thereby the
specific on-resistance reduced drastically according to Eq.
(2). For the investigated devices, Fig. 8 shows the
optimal P-top layer doping concentration, length and
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.14, NO.5, OCTOBER, 2014
679
Table 1. Optimal parameters for each device
Symbol
P+P-top device
conventional DRESURF device
TP(µm)
2
——
LP(µm)
1
-3
Nd(cm )
7.3×10
Np-top(cm-3)
N- drift region
SiO2
——
15
P-well
15
4.9×10
10×1015
8×1015
LPtop(µm)
20
16
TPtop(µm)
1.4
1
BV(V)
430.8
410.4
Rsp(mΩ·cm2)
224
302
FOM(MW/cm2)
0.83
P--Substrate
(a) Formation of N- drift and
P-well
(b) Formation of P-top layer
and field oxide
(c) Formation of gate oxide
and Polysilicon
(d) Formation of source and
drain region
0.56
depth of the P+P-top device are 10×1015 cm-3, 20 μm and
1.4 μm, respectively. While for the conventional DRESURF device, they are 8×1015 cm-3, 16 μm and 1 μm,
respectively. Furthermore, the optimal parameters for
these devices are listed in Table 1. Compared to the
conventional D-RESURF device; the proposed P+P-top
device exhibits a reduced specific on-resistance by
25.8%, an increased breakdown voltage by 5%, and thus
an increased FOM by 48.2%.
4. Fabrication Process
Fig. 9 illustrates the fabrication process flow of major
steps in fabricating the SOI P+P-top LDMOS device. The
device fabrication processes are the same as those for the
conventional D-RESURF LDMOS. Firstly, implant ions
is used to form the N- drift region and P-well area (see
Fig. 9(a)). It is followed by the P-top layer implantation,
field oxide grown and gate oxide growing. After that,
polysilicon was deposited and patterned for gate region,
as shown in Figs. 9(b) and (c). Subsequently, source,
drain and P-type body contact regions ion implantations
are performed. Then the formation of P+ region is the key
process for the P+P-top device fabrication. It can be
fabricated together with the P-type body contact region
without any additional mask, which is shown in Fig. 9(e).
Finally, metallization and passivation are carried out to
complete the LDMOS fabrication process (see Fig. 9(f)).
IV. CONCLUSIONS
A low specific on-resistance SOI P+P-top LDMOS
device is proposed. A P+ region connected to the P-top
layer is introduced to modulate the drift region surface
(e) Formation of P-type body (f) Formation of contact hole
contact region and P+ region
and metal electrode
Fig. 9. Key fabrication processes for the SOI P+P-top LDMOS
device.
electric field distribution and increase the optimal drift
doping concentration. The operation mechanism is
investigated and the structure parameters are optimized
by a 2D device simulator, MEDICI. The results show that
the proposed structure enables a 5% increase in
breakdown voltage and a 49% increase in optimum drift
doping concentration. As a result, the specific onresistance decreases by 25.8% and the FOM increases by
48.2%. Another merit of the P+P-top device is that the P+
region weakens the sensitivity of the breakdown voltage
on the device parameters and results in the flexible
design and fabrication. Moreover, the introduced P+
region can be fabricated together with the P-type body
contact region without any additional mask in
comparison with the conventional D-RESURF device.
Therefore, SOI P+P-top LDMOS device is a promising
candidate for SOI power integrated circuits owing to the
680
JIA-FEI YAO et al : LOW SPECIFIC ON-RESISTANCE SOI LDMOS DEVICE WITH P+P-TOP LAYER IN THE DRIFT REGION
high performance and the cost efficiency.
ACKNOWLEDGMENTS
[9]
This work was supported by the Specialized Research
Fund for the Doctoral Program of Higher Education of
China (No. 20133223110003).
REFERENCES
[1]
A.A. Orouji and M. Mehrad, “The Best Control of
Parasitic BJT Effect in SOI-LDMOS with SiGe
Window under Channel,” Electron Devices, IEEE
[10]
[11]
Transactions on, Vol. 59, No.2, pp.419-425, Feb.
[2]
[3]
[4]
[5]
[6]
[7]
[8]
2012.
K. Mao, M. Qiao, Z.J. Li and B. Zhang, “700V
ultra-low on-resistance DB-nLDMOS with
optimised thermal budget and neck region”,
Electronics Letters, Vol. 50, No.3 pp.209-211,
2014.
J.A. Appels and H.M.J. Vaes, “High voltage thin
layer devices (RESURF DEVICES),” Electron
Devices Meeting, 1979 Internationa, Washington
D.C, pp.238-241, Dec. 1979.
A.W. Ludikhuiza, “A review of RESURF
technology”, Power Semiconductor Devices and
ICs, 2000. Proceedings. The 12th International
Symposium on, Toulouse, pp. 11-18, May 2000.
Y. Li, M. Qiao, Y. Jiang, X. Zhou, W. Xu, and B.
Zhang, “Uniform and linear variable doping ultrathin PSOI LDMOS with n-type buried layer”,
Electronics Letters, Vol. 49, No.22, pp. 1407-1409,
2013.
H. Elahipanah and A.A. Orouji, “A 1300-V 0.34mΩ·cm2 partial SOI LDMOSFET with novel dual
charge accumulation layers”, Electron Devices,
IEEE Transactions on, Vol. 57, No.8, pp.19591965, 2010.
T.T. Hua, Y.F. Guo, Y. Yu, G. Sheu, X.J. Xia and
C.C. Zhang, “A 2D Analytical Model of SOI High
voltage Devices with Dual Conduction Layers,”
IETE Technical Review, Vol. 29, No.4, pp.346-354,
Sep. 2012.
R.P. Zingg, I. Weijland, H.V. Zwol, P. Boos, T.
Lavrijsen and T. Schoenmakers, “850V DMOS
switch in silicon-on-insulator with specific Ron of
[12]
[13]
[14]
[15]
[16]
[17]
13Ω·mm2,” SOI Conference, 2000 IEEE
International, Wakefield, pp.62-63, Oct. 2000.
M.H. Han, H.B. Chen, C.J. Chang, J.J. Wul, W.C.
Chen, C.C. Tsai and C.Y. Chang, “A Novel Cost
Effective Double Reduced Surface Field Laterally
Diffused Metal Oxide Semiconductor Design for
Improving Off-State Breakdown Voltage,” Jpn. J.
Appl. Phys, Vol. 51, No.4, pp.04DP04, Apr. 2012.
W.H. Li and J.S. Luo, “Breakdown voltage analysis
for thin film SOI RESURF structure”, Chinese
Journal of Semiconductors, Vol. 21, No.2, pp.161166, 2000.
H. S. Wasisto, G. Sheu, S.M. Yang, R.O.
Sihombing and Y.F. Guo, et al, “A novel 800V
multiple RESURF LDMOS utilizing linear P-top
rings,” TENCON 2010 IEEE Region 10 Conference,
Fukuoka, pp.75-79, Nov. 2010.
G. Sheu, S.M. Yang, Y.F. Chang and S.C. Tsaur,
“An Analytical Model of Surface Electric Field
Distributions in Ultrahigh-Voltage Buried P-Top
Lateral Diffused
Metal-Oxide-Semiconductor
Devices,” Jpn. J. Appl. Phys, Vol. 49, No.7, pp.
074301, July. 2010.
S. Hardikar, M.M. Souza, Y.Z. Xu and T.J. Pease,
“A novel double RESURF LDMOS for HVIC’s”,
Microelectron Journal, Vol. 35, No.3, pp.305-310,
2004.
L.L. Jiang, M. Qiao, Z.J. Li and B. Zhang, “A
Novel Double RESURF LDMOS with optimized
ESD Robustness”, Communications, Circuits and
Systems, 2009. ICCCAS 2009. International
Conference on , Chengdu, China, pp.638-640, 2009.
M.H. Han, H.B. Chen, C.J. Chang, C.C. Tsai and
C.Y. Chang, “Improving Breakdown Voltage of
LDMOS Using a Novel Cost Effective Design,”
Semiconductor Manufacturing, IEEE Transactions
on, Vol. 26, No.2, pp.248-252, May. 2013.
Y.F. Guo, J. Fang, B. Zhang, Z.H. Li and Z.J. Li,
“2D Analytical Model of SOI Double RESURF
Effect,” Journal of Semiconductors, Vol. 26, No.4,
pp.764-769, Apr. 2005.
J.R. Tsai, Y.M. Lee, M.C. Tsai, G. Sheu and S.M.
Yang, “Development of ESD Robustness
Enhancement of a Novel 800V LDMOS Multiple
RESURF with Linear P-top Rings,” TENCON 2011
IEEE Region 10 Conference, Bali, pp.760-763,
Nov. 2011.
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.14, NO.5, OCTOBER, 2014
[18] H. Zia, “Determination of Manufacturing Resurf
Process Window for a Robust 700V Double Resurf
LDMOS Transistor,” Power Semiconductor
Devices and ICs, 2008. Proceedings. The
International Symposium on, Orlando, pp.133-136,
May. 2008.
[19] Jayant
Baliga,
Fundamentals
of
Power
Semiconductor Devices, Springer, 2008.
[20] J.F. Yao, Y.F. Guo, T.T. Hua, S. Huang, C.C.
Zhang, X. J. Xia and G. Sheu, “Novel Silicon-onInsulator Lateral Power Device with Partial Oxide
Pillars in the Drift Region”, Jpn. J. Appl. Phys, Vol.
52, No.1, pp.014302, Apr. 2013.
Jia-Fei Yao received the B.S. degree
from Nanjing University of Posts and
Telecommunications, Nanjing, China,
in 2010. He is currently studying for
the PH.D. degree in microelectronics
in Nanjing University of Posts and
Telecommunications. His research
interests in the power device design and power device
model.
Yu-Feng Guo received the Ph.D.
degree in Microelectronics from
University of Electronic Science and
Technology of China, Chengdu,
China, in 2005, B.S. and M.S.
degrees in material engineering from
Sichuan University, Chengdu, China,
in 1996 and 2001, respectively. From July 1996 to
September 1998, he was an assistant engineer in
Luoyang Ship Material Research Institute. He joined
Nanjing University of Posts and Telecommunications,
Nanjing, China, in 2005 where he is currently a Professor
and Vice-Dean at the College of Electronic Science &
Engineering, Director, and Center of Electrical &
Electronic Experiment Teaching. He is also a consultant
of Semiconductor Device Laboratory, Asia University,
Taichung, Taiwan. He is currently leading a research
group in power semiconductor devices, power integrated
circuits and RF integrated circuits. His current research
interests include the characterization, simulation and
modeling of power semiconductor devices, RF devices,
and Nano CMOS devices.
681
Guang-Ming Xu received the B.S.
and M.S.degree degree from Nanjing
University of Posts and Telecommunications in 2011 and 2014,
respectively. His research interests in
power device design.
Ting-Tng Hua received the B.S.
degree from Nanjing University of
Posts and
Telecommunications,
Nanjing, China, in 2009. She is
currently studying for the Ph.D.
degree in Nanjing University of Posts
and
Telecommunications.
Her
research interests in power device design and power
device model.
Hong Lin receied the M.S.degree in
Nanjing University of Posts and
Telecommunications, Nanjing, china,
in 2006, and B.S degree in Nanjing
university, Nanjing, china, in 2002.
He joined Nanjing University of
Posts and Telecommunications,
Nanjing, China, in 2006 where He is a lecturer at the
College of Electronic Science & Engineering. He
research interests in power device design and power
device model.
Jian Xiao received the B.S. and M.S.
degrees in Electrical Engineering
from Southeast University in 1998
and 2004 respectively, where he is
currently pursuing the Ph.D. degree
in electrical engineering.
He is
research interests mainly include multimedia processing,
reconfigurable computing and related SoC designs.