Synthesizing Asynchronous Burst-Mode
Machines without the Fundamental-Mode
Timing Assumption
Gennette Gill
Montek Singh
Univ. of North Carolina
Chapel Hill, NC, USA
Contribution
Å Synthesize robust asynchronous controllers
z … from “burst-mode” finite-state machine specifications
Å No timing assumptions between controller and env.
z Reduces need for timing verification
Å Improves modularity and facilitates design reuse
Outline
Å Motivation
Å Background and Previous Work
Å Fundamental Mode: Challenges
Å Our Solution
z FSM Architecture
z Synthesis steps
z Example
z Informal proof of correctness
Å Results
Å Conclusion
Motivation: Why Asynchronous Design
Å No central clock – may eliminate problems inherent
to synchronous design
Å Several potential benefits:
z higher speed, lower power, more modularity
Å Our focus is improving modularity
Motivation
Background
Challenges
Solution
Results
Conclusion
Motivation: Modularity
Å Replace modules locally without global implications
Å Design reuse
Å No timing analysis between module and env.
z Decreased design and verification effort
Å Facilitates automation; improves design time
Research Focus
Focus:
z
Automated synthesis of asynchronous controllers
Objective:
z
Minimize timing constraints between env and module
z
Target is Quasi Delay-Insensitive (QDI) operation
¾ Only timing assumption is “isochronic forks”
¾ Equal wire delays along different fork branches
Burst Mode Finite State Machines
Å A subset of Mealy finite state
machines
Å Consist of states connected by
transitions
Å Transitions consist of
A
a+/c+d+
b-/c-d-
C
a-b+/c-
B
z An input burst (a set of input changes)
z An output burst (a set of output changes)
Å Values change in any order within bursts
z Must be monotonic
Motivation
Background
Challenges
Solution
Results
Conclusion
Burst Mode Finite State Machines
Key properties:
z An output burst follows a complete input burst
z A new input burst follows a complete output burst
¾Restriction on the environment
z Maximal set property: No input burst can be a
subset of another
¾ Otherwise, specification is ambiguous
z Unique entry point: Each state can only be
entered with a unique set of input values.
¾Facilitates hazard-free solution
Burst Mode: Previous Work
Å Many existing methods
z Minimalist [Fuhrer/Nowick et al. 1996-2001]
z 3D [Yun et al. 1992]
z ATACS [Meyers et al. 1999]
z All operate using timing assumptions
Å Minimalist = Basis for our work
z Generates sum-of-products implementation
z Optimal synthesis steps
z Low Latency
Fundamental Mode
Å The environment should not provide new inputs until
after the machine has stabilized internally
Å When placing a component in an environment
z Perform timing analysis, or
z Assume the environment is not too fast
Å Timing analysis of every instance undermines
modularity
Å We break the timing assumption down into two
separate challenges
z State bits may not have changed when output changes
z State bits may have changed, but not “stabilized”
z In either case, environment may react too fast
Fundamental Mode: Challenge I
Å Output produced before state changes
z A new input arrives before the state changes
z The machine is driven to an undesired state
Example:
Å A transition from state A to state
B on input 10
Å A new input arrives before all
state bits have changed
Å The machine is driven to state C
00 01 11 10
A A
A
A
B
S0 C
C
C
B
S1 C
C
C
B
B C
B
B
B
??
Motivation
Background
Challenges
Solution
Results
Conclusion
Challenge I: Solution
Å Do not change output until state has changed
I
S
O
I
env
input
Output
Logic
S
O
env
output
input
State
Logic
With fundamental mode
similar to a Mealy machine
State
Logic
Output
Logic
Without fundamental mode
similar to a Moore machine
output
Fundamental mode: Challenge II
A new input can arrive before all products that implement an
output or state bit have “stabilized”
Å “Stabilized” ≠ changed
Å
z Stabilized means there is no gate that is enabled but has yet to change
Å
Example: P1and P2 are unacknowledged internal paths
- internal changes that cause no external changes
00
01
11
10
A
0
0
0
1
S0
0
0
0
1
P1
S1
0
0
0
1
OUT
B
1
1
1 P1
P0
P
1
P0
Challenge II: Solution
Å Prevent more than one product from being enabled
for a given function at any one time
z Changed ⇒ stabilized
Å Two prevention methods:
z If one product, P1 will assert before another product P2, use
P1 to disable P2
z If ordering cannot be determined, products should not
overlap in Boolean space
Our system: target architecture
1.
z Each state and output bit
has a set function and a
reset function
z Combine using a special
C-element
2.
Disable
Set/reset implementation:
Output is fed back to
disable set/reset functions
z Necessary to prevent
unacknowledged internal
paths
Motivation
Background
Challenges
Set
Function
Set-reset
element
c
Reset
Function
Disable
S
0
R
0
Out
Hold
0
1
1
1
0
1
0
1
Hold
Solution
Results
Conclusion
Target architecture: Set/reset functions
Set and reset functions are both implemented as two-level
sum-of-products
Å Each function is disabled once it has caused output change
Å
z inverted disable bit for set function
Set function
Reset function
Inputs
Inputs
Disable
Disable
Target architecture: Fed back outputs
Å In this scenario, the fed-back disable prevents
possible glitches
A
B
00
01
11
10
S+
S+
S+
S+
S+
S+
P0
P1
P0 (set)
P1(set)
S+
S+
P2 (reset)
C
R+
R+
P2
R+
R+
OUT
Synthesis Approach
Å Two steps:
z Constrained State Encoding
¾Critical-race-free constraints
¾Non-overlapping cube constraints
¾Guarantees existence of correct logic covering
z Constrained Logic Covering
¾Hazard-free cover
¾Non-overlapping products
¾Imposes constraints on state encoding
Logic Covering
Å We use a simple (non-optimized) logic covering step
z Does not introduce product overlaps or hazards
z Depends on the valid input region of a state
00 01 11 10
A
B
C
D
A
C
B
Definition: valid input region
Smallest cube that contains the
entry point and all exit points of
a state
Logic Covering: Output Logic
Å Entry point of A is 00
Å A transitions to B on input 11
A
Å Output changes from 1 to 0
00
01
11
00
10
01
S+
S+
S+
S+
A
R-
R-
S-
S-
S-
10
R-
R-
R-
S-
B
11
B
R-
S-
A
11/ 0
S-
B
R+
R+
R+
R+
Logic Covering: State logic
•Entry point of A is 00
•A transitions to B on input 11
•output changes from 1 to 0
00
01
00
A
(01)
11
B
(10)
Sdc
R-
Sdc
R-
bit 1
11
S+
RS+
RSRSR-
10
11/ 0
A
bit 2
00
01
B
S(10) Rdc
SRdc
00
A
(01)
11
Sdc
R-
11
SRSR+
SR+
SRdc
B
10
SR-
State Encoding
Constraints:
z
Critical-race-free constraints
¾ Protect a transition from: another transition or stable state
¾ i.e., to ensure transition from A to B does not get diverted to
some other state X
z
Non-overlapping cube constraints
¾ Protect a state’s valid input region from other transitions
¾ i.e., to ensure that a single product cover exists
¾ Subsume critical-race-free constraints
Types of Dichotomies
Constraints expressed as dichotomies:
z A dichotomy (Sa; Sb) is a constraint
A
between two sets of symbolic states that
prohibits their respective smallest
containing binary cubes from intersecting
Å
C
B
Constraints of type (AB; C)
z Prevent state C from being embedded in
transition AB. Not necessary if C is don’t
care in the input column.
Å
Constraints of type (AB; CD)
A
C
z Prevent transition AB from intersecting
B
transition CD.
D
Example
S0
S3
b-/c-d-
a+/d+
a-/d-
00
a+b+/c+
S1
a-/d+
S2
Dichotomies:
A sample
burst
modeto
Dichotomies:
Solve
the dichotomies
Calculate
the
valid
finite
state
{0
11a| ;2state
3 {0
} each
because
{0
2}
1machine
; 3}
find
encoding
that
inputs
for
stateboth
with two
inputs
transitions
take
place in
causes
no
illegal
{1 2 ; 0} {1 2 ; 3}
input
column 11
intersections
{2 3 ; 0} {2 3 ; 1}
01
S0
00
S1
S1
01
S2
11
S3
10
11
S2
S0
S3
S2
10
Example: State Cover
State bit 2
State bit 1
00
01
11
00
10
S0 S- R- S- Rdc S-Rdc S- Rdc
00
S1
01
S2 S- R+ S- R- Sdc R11
S2
11
S3
10
S3
10
S + R-
Sdc R- Sdc R-
11
10
S0 S- R- S- Rdc S+ R- S- Rdc
00
S-Rdc
S1
01
01
S-
R+
Sdc
R-
S - R-
Sdc
R-
S - R+
S + R- S - R-
Example: Output Cover
Output c
S0
00
00
01
11
10
00
01
11
10
SR+
SR+
SR+
SR+
SR+
SR+
SR+
SR+
S+
R-
S+
R-
SR+
SR+
S+
R-
S+
R-
S+
R-
S+
R-
S+
R-
S+
R-
SR+
SR+
S1
01
S2
11
S3
10
Output d
S+
R-
S0
00
S1
01
S+
R-
S2
11
S3
10
S+
R-
S+
R-
Solution to Challenges
Å Challenge I: Output change does not imply state
change is complete
z Solved using the Moore model
Å Challenge II: Change does not imply stabilization
z Allow only single product activation: change → stability
z Logic covering approach = “single product cover”
¾ Dichotomies to protect valid input regions
¾ Fed back outputs to disable further product assertion
z Net result: only one product is activated at any given time for
a given state or output bit
Informal Proof of Correctness
Å Define: Stable internal state
z
At most one product is active for each output and state bit
z
All fed back disables have reached the products in the set
and reset functions
Å Assume: machine begins in a stable internal state
Å Claim: machine will return to a new stable internal
state before a new input arrives
Informal Proof of Correctness
Å Proof:
z State change visible at point a ⇒ state logic is stable
z Output change visible at point b ⇒ output logic is stable
⇒ FSM is stable when environment produces new input
Output Logic
State Logic
a
Set
Function
Set
Function
c
Reset
Function
c
Reset
Function
Environment
b
Results
Å Automated synthesis tool
z Built off of Minimalist
z Modified state encoding and logic covering
Å Several burst-mode FSM benchmarks
z Successfully able to handle all benchmarks
z Some overhead w.r.t. Minimalist (as expected)
z Not considered: state merging or fed-back output
Motivation
Background
Challenges
Solution
Results
Conclusion
Results
Å Comparison: Our method vs. Minimalist
z I/S/O = number of inputs, states, and outputs
z #b = number of state bits
z #c = product count
¾ Product count does not include set/reset elements
Us
Key Results:
Design
I/S/O
z Our method has the same
number of state bits in
each case
z Product count:
¾ Max overhead = 58%
¾ In some cases, up to 16%
improvement
Min-crf
#b #c #
b
#c
Sbuf-read-ctl
3/7/3
3
19 3
12
Sbuf-send-ctl
3/8/3
3
19 3
19
Rf-control
6/12/4 4
35 4
24
It-control
5/10/7 4
30 4
28
Pe-send-ifc
5/11/3 4
33 4
28
Dram-ctrl
7/12/6 4
35 4
27
Pscsi-ircv
4/6/3
16 3
19
3
Conclusion
New method for synthesizing asynchronous finite-state
machines
z Eliminate fundamental-mode timing assumptions
z Allow modularity and design reuse
z Modest product count overhead
Further work:
z Optimized logic covering: cube merging
z State merging: reduce total number of states
z Fed back outputs as state bits
Motivation
Background
Challenges
Solution
Results
Conclusion