MODULE 4
Applications of Flip-Flops
Bounce elimination switch
Mechanical switches are employed in digital system as a input devices by witch digital
information (0 and 1) is entered into the system. There is a very serious problem associated with
these switches which is switch bouncing (chattering).
If we entered input as ‘1’ in a sequential circuit the output is ‘1’ but it oscillates between ‘1’and
‘0’ before come to rest i.e. 1. This changes the output of the sequential circuit and creates
difficulties. This problem is eliminated by the use of Bounce elimination switches.
Registers :
A register is composed of a group of flip-flops to store a group of bits (word). For storing N bit
of words we require N number of flip-flops (one flip of for each bit).
A flip flop can store only one bit of data, a 0 or a 1; it is referred to as a single bit register. When
more bits of data are to be stored, a number of flip flops are used. A register is a set of flip flops
used to store a binary data. The storage capacity of a register is a number of bits of digital data
that it can retain. Loading a register means setting or resetting the individual flip flops, i.e.
inputting data into the register so that their states correspond to the bits of data to be stored.
Loading may be serial or parallel in serial loading, data is transferred into the register in serial
form, i.e. one bit at a time, whereas in parallel loading, the data is transferred into the register in
parallel form meaning that all the flip flops are triggered into their new states at the same time.
Parallel input requires that the SET and/or RESET controls of every flip flop be accessible.
Counters :
Digital counters are used for count the events. Electrical pulses corresponding to the event are
produced using transducers & these pulses counted using a counter.
A digital counter is a set of flip-flops whose stated change in response to pulses applied at the
input to the counter. The flip flops are interconnected such that their combined state at any time
is the binary equivalent of the total number of pulses that have occurred up to that point. Thus, as
its name implies, a counter is used to count the pulses. A counter can also be used as a frequency
divider to obtain waveforms with frequencies that are specific fractions of the clock frequency.
They are also used to perform the timing function as in digital watches, to create time delays, to
crate non-sequential binary counts, to generate pulse trains, and to act as frequency counters, etc.
Random access memory:
In computers, digital control systems, information processing systems it is necessary to store
digital data and retrieve the data as desired.
Flip-Flops can be used for making memories in which data can be stored for any desired length
of time and then readout whenever required.
The data stored in RWMs (Read Write memories) constructed from semiconductor devices will
be lost if power is removed. Such memory is said to be volatile. But ROM is non-volatile.
Random access memory (RAM) is the memory whose memory locations can be accessed
directly and immediately. By contrast, to access a memory location on a magnetic tape, it is
necessary to wind or unwind the tape and go through a series of addresses before reaching the
address desired. Therefore, the tape is called the sequential access memory.
Counters
1. Introduction
A counter is a sequential machine that produces a specified count sequence. The
count changes whenever the input clock is asserted.
There is a great variety of counter based on its construction.
1. Clock: Synchronous or Asynchronous
2. Clock Trigger: Positive edged or Negative edged
3. Counts: Binary, Decade
4. Count Direction: Up, Down, or Up/Down
5. Flip-flops: JK or T or D
A counter can be constructed by a synchronous circuit or by an asynchronous
circuit. With a synchronous circuit, all the bits in the count change synchronously
with the assertion of the clock. With an asynchronous circuit, all the bits in the
count do not all change at the same time.
A counter may count up or count down or count up and down depending on the
input control.
Because of limited word length, the count sequence is limited. For an n-bit
counter, the range of the count is [0, 2n-1]. The count sequence usually repeats
itself. When counting up, the count sequence goes in this manner: 0, 1, 2, … 2n-2,
2n-1, 0, 1, …etc. When counting down the count sequence goes in the same
manner: 2n-1, 2n-2, … 2, 1, 0, 2n-1, 2n-2, … etc.
Example:
The complement of the count sequence counts in reverse direction. If the
uncomplemented output counts up, the complemented output counts down. If the
uncomplemented output counts down, the complemented output counts up.
Example:
The natural count sequence is to run through all possible combinations of the bit patterns before
repeating itself. External logic can be used to arbitrary cause the counter to start at any count and
terminate at any count.
binary counter produces a count sequence similar to the binary
numbers. A decade counter counts from 0 to 9, thus making it suitable for human interface.
Other counters count to 12 making them suitable for clocks.
Uses of Counters
The most typical uses of counters are
place; the occurrence of event to be counted is represented by the input signal to the counter (Fig.
1.1a)
rate timing signals (Fig. 1.2a)
Two Classes of Counters
Asynchronous & Synchronous
Asynchronous: The events do not have a fixed time relationship with each other and do not occur
at the same time.
Synchronous: The events have a fixed time relationship with each other and do occur at the same
time.
Counters are classified according to the way they are clocked. In asynchronous counters, the first
flip-flop is clocked by the external clock pulse and then each successive flip-flop is by clocked
the output of the preceding flip-flop. In synchronous counters, the clock input is connected to all
of the flip-flop so that they are clocked simultaneously.
Asynchronous Counters
An asynchronous counter is one in which the flip-flop within the counter do not change states at
exactly the same time because they do not have a common clock pulse.
asynchronous binary counter
The main characteristic of an asynchronous counter is each flip-flop derives its own clock from
other flip-flops and is therefore independent of the input clock. Consequently, the output of each
flip-flop may change at different time, hence the term asynchronous. From the asynchronous
counter diagram above, we observed that the output of the first flip-flop becomes the clock input
for the second flip-flop, and the output of the second flip-flop becomes the clock input for the
third flip-flop etc.
For the first flip-flop, the output changes whenever there is a negative transition in the clock
input. This means that the output of the first flipflop produces a series of square waves that is
half the frequency of the clock input. Since the output of the first flip-flop becomes the clock of
the second flip-flop, the output of the second flip-flop is half the frequency of its clock, i.e. the
output of the first flip-flop that in turn is half the frequency of the clock input. This behaviour, in
essence is captured by the binary bit pattern in the counting sequence
2.1 2-Bit Asynchronous Binary Counter
A two-bit asynchronous counter is shown on the left. The external clock is connected to the
clock input of the first flip-flop (FF0) only. So, FF0 changes state at the falling edge of each
clock pulse, but FF1 changes only when triggered by the falling edge of the Q output of FF0.
Because of the inherent propagation delay through a flip-flop, the transition of the input clock
pulse and a transition of the Q output of FF0 can never occur at exactly the same time. Therefore,
the flip-flops cannot be triggered simultaneously, producing an asynchronous operation.
for simplicity, the transitions of Q0, Q1 and CLK in the timing diagram above are
shown as simultaneous even though this is an asynchronous counter. Actually, there is some
small delay between the CLK, Q0 and Q1 transitions. Usually, all the CLEAR inputs are
connected together, so that a single pulse can clear all the flip-flops before counting starts. The
clock pulse fed into FF0 is rippled through the other counters after propagation delays, like a
ripple on water, hence the name Ripple Counter.
-bit ripple counter circuit above has four different states, each one corresponding to a
count value. Similarly, a counter with n flipflops can have 2 to the power n states. The number of
states in a counter is known as its mod (modulo) number. Thus a 2-bit counter is a mod-4
counter.
-n counter may also be described as a divide-by-n counter. This is because the most
significant flip-flop (the furthest flip-flop from the original clock pulse) produces one pulse for
every n pulses at the clock input of the least significant flip-flop (the one triggers by the clock
pulse). Thus, the above counter is an example of a divide-by-4 counter.
Example 2:
3-Bit Asynchronous Binary Counter
The following is a three-bit asynchronous binary counter and its timing diagram for one cycle. It
works exactly the same way as a two-bit asynchronous binary counter mentioned above, except
it has eight states due to the third flip-flop.
Asynchronous counters are commonly referred to as ripple counters for the following reason:
The effect of the input clock pulse is first “felt” by FFO. This effect cannot get to FF1
immediately because of the propagation delay through FF0. Then there is the propagation delay
through FF1 before FF2 can be triggered. Thus, the effect of an input clock pulse “ripples”
through the counter, taking some time, due to propagation delays, to reach the last flip-flop.
4 Bit Asynchronous Binary Counter
The following is a 4-bit asynchronous binary counter and its timing diagram for one cycle. It
works exactly the same way as a 2-bit or 3 bit asynchronous binary counter mentioned above,
except it has 16 states due to the fourth flip-flop.
Asynchronous Decade Counters
states. But counters with
states less than this number are also possible. They are designed to have the number of states in
their sequences, which are called truncated sequences. These sequences are achieved by forcing
the counter to recycle before going through all of its normal states.
counter with ten states in
its sequence is called a decade counter.
Once the counter counts to ten (1010), all the flip-flops are being cleared. Notice that only Q1
and Q3 are used to decode the count of ten. This is called partial decoding, as none of the other
states (zero to nine) have both Q1 and Q3 HIGH at the same time.
nter is shown in the table below:
Glitch: Notice that there is a glitch on the Q1 waveform. The reason for this glitch is that Q1
must first go HIGH before the count of ten can be decoded. Not until several nanoseconds after
the counter goes to the count of ten does the output of the decoding gate go LOW (both inputs
are HIGH). Therefore, the counter is in the 1010 state for a short time before it is reset to 0000,
thus producing the glitch on Q1 and the resulting glitch on the CLR line that resets the counter.
Example: Modulus Twelve Asynchronous Counter
An Asynchronous counter can be implemented having a modulus of 12 with a straight binary
sequence from 0000 through 1011
Asynchronous Up-Down Counters
In certain applications a counter must be able to count both up and down. The circuit below is a
3-bit up-down counter. It counts up or down depending on the status of the control signals UP
and DOWN. When the UP input is at 1 and the DOWN input is at 0, the NAND network
between FF0 and FF1 will gate the non-inverted output (Q) of FF0 into the clock input of FF1.
Similarly, Q of FF1 will be gated through the other NAND network into the clock input of FF2.
Thus the counter will count up.
Figure 1.8: 3-bit up-down counter
When the control input UP is at 0 and DOWN is at 1, the inverted outputs of FF0 and FF1 are
gated into the clock inputs of FF1 and FF2 respectively. If the flip-flops are initially reset to 0's,
then the counter will go through the following sequence as input pulses are applied.
Notice that an asynchronous up-down counter is slower than an up counter or a down counter
because of the additional propagation delay introduced by the NAND networks.
Commercially Available Asynchronous Counters
Example 1: The 74LS93 Asynchronous Binary Counter
Synchronous Counters
In synchronous counters, the clock inputs of all the flip-flops are connected together and are
triggered by the input pulses. Thus, all the flip-flops change state simultaneously (in parallel).
3.1 2-Bit Synchronous Binary Counter
Propagation Delay:
Figure
3-Bit Synchronous Binary Counter
The circuit below is a 3-bit synchronous counter. The J and K inputs of FF0 are connected to
HIGH. FF1 has its J and K inputs connected to the output of FF0, and the J and K inputs of FF2
are connected to the output of an AND gate that is fed by the outputs of FF0 and FF1.
Pay attention to what happens after the 3rd clock pulse. Both outputs of FF0 and FF1 are HIGH.
The positive edge of the 4th clock pulse will cause FF2 to change its state due to the AND gate.
The count sequence for the 3-bit counter is shown in Figure 3.3c.The most important advantage
of synchronous counters is that there is no cumulative time delay because all flip-flops are
triggered in parallel.Thus, the maximum operating frequency for this counter will be
significantly higher than for the corresponding ripple counter.
Synchronous Decade Counters
Similar to an asynchronous decade counter, a synchronous decade counter counts from 0 to 9 and
then recycles to 0 again. This is done by forcing the 1010 state back to the 0000 state. This so
called truncated sequence can be constructed by the following circuit.
From the sequence in the Figure 3.5b, we notice that:
clock pulse each time Q0=1 and Q3=0.
(count 7), or then Q0=1 and Q3=1 (count 9).
Flip-flop 2 (Q2) changes on the next clock pulse each time both Q0=1 and
Q1=1. Thus we must have
J2 = K2 = Q0Q1
Flip-flop 3 (Q3) changes to the opposite state on the next clock pulse
each time Q0=1, Q1=1, and Q2=1 (state 7), or when Q0=1 and Q3=1
(state 9). Thus we must have
J3 = K3 = Q0Q1Q2 + Q0Q3
These characteristics are implemented with the AND/OR logic connected
as shown in the logic diagram
Up-Down Synchronous Counters
A circuit of a 3-bit synchronous up-down counter and a table of its sequence are shown in Figure
3.6. Similar to an asynchronous up-down counter, a synchronous up-down counter also has an
up-down control input. It is used to control the direction of the counter through a certain
sequence.
An examination of the sequence table shows:
ach clock pulse. for the UP sequence,
Q1 changes state on the next clock pulse when Q0=1.
state on the next clock pulse
clock pulse when Q0=Q1=1.for the DOWN sequence, Q2 changes state on the next clock pulse
when Q0=Q1=0.
Registers:
The Shift Register
The Shift Register is another type of sequential logic circuit that can be used for the storage or
the transfer of data in the form of binary numbers. This sequential device loads the data present
on its inputs and then moves or “shifts” it to its output once every clock cycle, hence the name
“shift register”.
A shift register basically consists of several single bit “D-Type Data Latches”, one for each data
bit, either a logic “0” or a “1”, connected together in a serial type daisy-chain arrangement so
that the output from one data latch becomes the input of the next latch and so on.
Data bits may be fed in or out of a shift register serially, that is one after the other from either the
left or the right direction, or all together at the same time in a parallel configuration.
The number of individual data latches required to make up a single Shift Register device is
usually determined by the number of bits to be stored with the most common being 8-bits (one
byte) wide constructed from eight individual data latches.
Shift Registers are used for data storage or for the movement of data and are therefore commonly
used inside calculators or computers to store data such as two binary numbers before they are
added together, or to convert the data from either a serial to parallel or parallel to serial format.
The individual data latches that make up a single shift register are all driven by a common clock
( Clk ) signal making them synchronous devices.
Shift register IC’s are generally provided with a clear or reset connection so that they can be
“SET” or “RESET” as required. Generally, shift registers operate in one of four different modes
with the basic movement of data through a shift register being:




• Serial-in to Parallel-out (SIPO) - the register is loaded with serial data, one bit at a
time, with the stored data being available at the output in parallel form.
• Serial-in to Serial-out (SISO) - the data is shifted serially “IN” and “OUT” of the
register, one bit at a time in either a left or right direction under clock control.
• Parallel-in to Serial-out (PISO) - the parallel data is loaded into the register
simultaneously and is shifted out of the register serially one bit at a time under clock
control.
• Parallel-in to Parallel-out (PIPO) - the parallel data is loaded simultaneously into the
register, and transferred together to their respective outputs by the same clock pulse.
The effect of data movement from left to right through a shift register can be presented
graphically as:
Also, the directional movement of the data through a shift register can be either to the left, (left
shifting) to the right, (right shifting) left-in but right-out, (rotation) or both left and right shifting
within the same register thereby making it bidirectional. In this tutorial it is assumed that all the
data shifts to the right, (right shifting).
Serial-in to Parallel-out (SIPO) Shift Register
4-bit Serial-in to Parallel-out Shift Register
The operation is as follows. Lets assume that all the flip-flops ( FFA to FFD ) have just been
RESET ( CLEAR input ) and that all the outputs QA to QD are at logic level “0” ie, no parallel
data output.
If a logic “1” is connected to the DATA input pin of FFA then on the first clock pulse the output
of FFA and therefore the resulting QA will be set HIGH to logic “1” with all the other outputs
still remaining LOW at logic “0”. Assume now that the DATA input pin of FFA has returned
LOW again to logic “0” giving us one data pulse or 0-1-0.
The second clock pulse will change the output of FFA to logic “0” and the output of FFB and QB
HIGH to logic “1” as its input D has the logic “1” level on it from QA. The logic “1” has now
moved or been “shifted” one place along the register to the right as it is now at QA.
When the third clock pulse arrives this logic “1” value moves to the output of FFC ( QC ) and so
on until the arrival of the fifth clock pulse which sets all the outputs QA to QD back again to logic
level “0” because the input to FFA has remained constant at logic level “0”.
The effect of each clock pulse is to shift the data contents of each stage one place to the right,
and this is shown in the following table until the complete data value of 0-0-0-1 is stored in the
register. This data value can now be read directly from the outputs of QA to QD.
Then the data has been converted from a serial data input signal to a parallel data output. The
truth table and following waveforms show the propagation of the logic “1” through the register
from left to right as follows.
Basic Data Movement Through A Shift Register
Clock Pulse No
QA
QB
QC
QD
0
0
0
0
0
1
1
0
0
0
2
0
1
0
0
3
0
0
1
0
4
0
0
0
1
5
0
0
0
0
Note that after the fourth clock pulse has ended the 4-bits of data ( 0-0-0-1 ) are stored in the
register and will remain there provided clocking of the register has stopped. In practice the input
data to the register may consist of various combinations of logic “1” and “0”. Commonly
available SIPO IC’s include the standard 8-bit 74LS164 or the 74LS594.
Serial-in to Serial-out (SISO) Shift Register
This shift register is very similar to the SIPO above, except were before the data was read
directly in a parallel form from the outputs QA to QD, this time the data is allowed to flow
straight through the register and out of the other end. Since there is only one output, the DATA
leaves the shift register one bit at a time in a serial pattern, hence the name Serial-in to SerialOut Shift Register or SISO.
The SISO shift register is one of the simplest of the four configurations as it has only three
connections, the serial input (SI) which determines what enters the left hand flip-flop, the serial
output (SO) which is taken from the output of the right hand flip-flop and the sequencing clock
signal (Clk). The logic circuit diagram below shows a generalized serial-in serial-out shift
register.
4-bit Serial-in to Serial-out Shift Register
You may think what’s the point of a SISO shift register if the output data is exactly the same as
the input data. Well this type of Shift Register also acts as a temporary storage device or as a
time delay device for the data, with the amount of time delay being controlled by the number of
stages in the register, 4, 8, 16 etc or by varying the application of the clock pulses. Commonly
available IC’s include the 74HC595 8-bit Serial-in to Serial-out Shift Register all with 3-state
outputs.
Parallel-in to Serial-out (PISO) Shift Register
The Parallel-in to Serial-out shift register acts in the opposite way to the serial-in to parallel-out
one above. The data is loaded into the register in a parallel format in which all the data bits enter
their inputs simultaneously, to the parallel input pins PA to PD of the register. The data is then
read out sequentially in the normal shift-right mode from the register at Q representing the data
present at PA to PD.
This data is outputted one bit at a time on each clock cycle in a serial format. It is important to
note that with this type of data register a clock pulse is not required to parallel load the register as
it is already present, but four clock pulses are required to unload the data.
4-bit Parallel-in to Serial-out Shift Register
As this type of shift register converts parallel data, such as an 8-bit data word into serial format,
it can be used to multiplex many different input lines into a single serial DATA stream which
can be sent directly to a computer or transmitted over a communications line. Commonly
available IC’s include the 74HC166 8-bit Parallel-in/Serial-out Shift Registers.
Parallel-in to Parallel-out (PIPO) Shift Register
The final mode of operation is the Parallel-in to Parallel-out Shift Register. This type of shift
register also acts as a temporary storage device or as a time delay device similar to the SISO
configuration above. The data is presented in a parallel format to the parallel input pins PA to PD
and then transferred together directly to their respective output pins QA to QA by the same clock
pulse. Then one clock pulse loads and unloads the register. This arrangement for parallel loading
and unloading is shown below.
4-bit Parallel-in to Parallel-out Shift Register
The PIPO shift register is the simplest of the four configurations as it has only three connections,
the parallel input (PI) which determines what enters the flip-flop, the parallel output (PO) and the
sequencing clock signal (Clk).
Similar to the Serial-in to Serial-out shift register, this type of register also acts as a temporary
storage device or as a time delay device, with the amount of time delay being varied by the
frequency of the clock pulses. Also, in this type of register there are no interconnections between
the individual flip-flops since no serial shifting of the data is required.
Universal Shift Register
Today, there are many high speed bi-directional “universal” type Shift Registers available such
as the TTL 74LS194, 74LS195 or the CMOS 4035 which are available as 4-bit multi-function
devices that can be used in either serial-to-serial, left shifting, right shifting, serial-to-parallel,
parallel-to-serial, or as a parallel-to-parallel multifunction data register, hence the name
“Universal”.
These universal shift registers can perform any combination of parallel and serial input to output
operations but require additional inputs to specify desired function and to pre-load and reset the
device. A commonly used universal shift register is the TTL 74LS194 as shown below.
4-bit Universal Shift Register 74LS194
Universal shift registers are very useful digital devices. They can be configured to respond to
operations that require some form of temporary memory storage or for the delay of information
such as the SISO or PIPO configuration modes or transfer data from one point to another in
either a serial or parallel format. Universal shift registers are frequently used in arithmetic
operations to shift data to the left or right for multiplication or division.
Registers in which data are entered or/and taken out in serial form are referred as shift registers,
since bits are shifted in the Flip-Flops with the occurrence of clock pulses either in the right
direction or in the left direction or in both the directions (Bi-directional). IC74295A is a bidirectional shift register.
A register is referred as universal register if it be operated in all the four possible modes and also
as bi-directional registers. For example 74194 is a universal register.
Universal Shift Register:
A universal shift register is a bidirectional register, whose input can either in serial form or in
parallel form and whose output can also be either in serial form or in parallel form.
Following figure shows the logic diagram of the 74194 4-bit universal shift register. Note that
the output of each flip flop is routed through AOI logic to the stage on its right and to the stage
on its left. The mode control inputs S0, and S1, are used to enable the left to, right connections
when it is desired to shift-right, and the right-to-left connections when it is desired to shift-left.
Universal shift
register
The truth table shows that no shifting occurs when S0 and S1 are either LOW or both HIGH.
When So = S1=0, there is no change in the contents of the register, and when So = S1 = 1, the
parallel input data A, B, C and D are loaded into the register on the rising edge of the clock
pulse. The combination S0 = S1= 0, is said to inhibit the loading of serial or parallel data, since
the register contents cannot change under that condition. The register has an asynchronous
active-Low clear input, which can be used to reset all the flip flops irrespective of the clock and
any serial or parallel inputs.
he Sequential Ring Counter
In the previous Shift Register tutorial we saw that if we apply a serial data signal to the input of a
Serial-in to Serial-out Shift Register, the same sequence of data will exit from the last flip flip in
the register chain after a preset number of clock cycles thereby acting as a sort of time delay
circuit to the original input data signal.
But what if we were to connect the output of this Shift Register back to its input so that the
output from the last flip-flop, QD becomes the input of the first flip-flop, DA. We would then
have a closed loop circuit that “recirculates” the same bit of DATA around a continuous loop for
every state of its sequence, and this is the principal operation of a Ring Counter.
Then by looping the output back to the input, (feedback) we can convert a standard shift register
circuit into a ring counter. Consider the circuit below.
4-bit Ring Counter
The synchronous Ring Counter example above, is preset so that exactly one data bit in the
register is set to logic “1” with all the other bits reset to “0”. To achieve this, a “CLEAR” signal
is firstly applied to all the flip-flops together in order to “RESET” their outputs to a logic “0”
level and then a “PRESET” pulse is applied to the input of the first flip-flop ( FFA ) before the
clock pulses are applied. This then places a single logic “1” value into the circuit of the ring
counter.
So on each successive clock pulse, the counter circulates the same data bit between the four flipflops over and over again around the “ring” every fourth clock cycle. But in order to cycle the
data correctly around the counter we must first “load” the counter with a suitable data pattern as
all logic “0’s” or all logic “1’s” outputted at each clock cycle would make the ring counter
invalid.
This type of data movement is called “rotation”, and like the previous shift register, the effect of
the movement of the data bit from left to right through a ring counter can be presented
graphically as follows along with its timing diagram:
Rotational Movement of a Ring Counter
Since the ring counter example shown above has four distinct states, it is also known as a
“modulo-4″ or “mod-4″ counter with each flip-flop output having a frequency value equal to
one-fourth or a quarter (1/4) that of the main clock frequency.
The “MODULO” or “MODULUS” of a counter is the number of states the counter counts or
sequences through before repeating itself and a ring counter can be made to output any modulo
number. A “mod-n” ring counter will require “n” number of flip-flops connected together to
circulate a single data bit providing “n” different output states.
For example, a mod-8 ring counter requires eight flip-flops and a mod-16 ring counter would
require sixteen flip-flops. However, as in our example above, only four of the possible sixteen
states are used, making ring counters very inefficient in terms of their output state usage.
Johnson Ring Counter
The Johnson Ring Counter or “Twisted Ring Counters”, is another shift register with feedback
exactly the same as the standard Ring Counter above, except that this time the inverted output Q
of the last flip-flop is now connected back to the input D of the first flip-flop as shown below.
The main advantage of this type of ring counter is that it only needs half the number of flip-flops
compared to the standard ring counter then its modulo number is halved. So a “n-stage” Johnson
counter will circulate a single data bit giving sequence of 2n different states and can therefore be
considered as a “mod-2n counter”.
4-bit Johnson Ring Counter
This inversion of Q before it is fed back to input D causes the counter to “count” in a different
way. Instead of counting through a fixed set of patterns like the normal ring counter such as for a
4-bit counter, “0001”(1), “0010”(2), “0100”(4), “1000”(8) and repeat, the Johnson counter
counts up and then down as the initial logic “1” passes through it to the right replacing the
preceding logic “0”.
A 4-bit Johnson ring counter passes blocks of four logic “0” and then four logic “1” thereby
producing an 8-bit pattern. As the inverted output Q is connected to the input D this 8-bit pattern
continually repeats. For example, “1000”, “1100”, “1110”, “1111”, “0111”, “0011”, “0001”,
“0000” and this is demonstrated in the following table below.
Truth Table for a 4-bit Johnson Ring Counter
Clock Pulse No
FFA
FFB
FFC
FFD
0
0
0
0
0
1
1
0
0
0
2
1
1
0
0
3
1
1
1
0
4
1
1
1
1
5
0
1
1
1
6
0
0
1
1
7
0
0
0
1
As well as counting or rotating data around a continuous loop, ring counters can also be used to
detect or recognise various patterns or number values within a set of data. By connecting simple
logic gates such as the AND or the OR gates to the outputs of the flip-flops the circuit can be
made to detect a set number or value.
Standard 2, 3 or 4-stage Johnson Ring Counters can also be used to divide the frequency of the
clock signal by varying their feedback connections and divide-by-3 or divide-by-5 outputs are
also available.
For example, a 3-stage Johnson Ring Counter could be used as a 3-phase, 120 degree phase shift
square wave generator by connecting to the data outputs at A, B and NOT-B.
The standard 5-stage Johnson counter such as the commonly available CD4017 is generally used
as a synchronous decade counter/divider circuit.