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Clustered Hierarchical Search
Structure for Large-Scale Packet
Classification on FPGA
Publisher : Field Programmable Logic and
Applications, 2011
Author : Oguzhan Erdem, Hoang Le, Viktor K.
Prasanna
Presenter : Yu-Hsiang Wang
Date : 2011/11/09
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Outline
 Related Work
 Clustered Hierarchical Search Structure(CHSS)
 Architecture
 Performance evaluations
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Related Work
• Backtrack : the search needs to proceed in the
backward direction and requires stalling the pipeline.
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Clustered Hierarchical Search Structure
• Clustering algorithm : partition a given ruleset based on
the SA field to eliminate backtracking from DA trie to the
SA.
• In each cluster, the prefixes
are pairwise disjoint.
• The number of clusters is
at most 4 in the real life and
synthetic rulesets.
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Clustered Hierarchical Search Structure
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Clustered Hierarchical Search Structure
• A range tree is built for each leaf prefix node of a DA
trie if the number of rules at the node exceeds a
predefined threshold.
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Clustered Hierarchical Search Structure
• Define two parameters : NRtrie, NRtree
• NRtrie: remaining rules of DA trie node > NRtrie
leaf node => DP tree
non-leaf node => TCAM
• NRtree : remaining rules of DP tree > NRtree => TCAM
• TCAM include: (1) the non-leaf DA trie rules
(2) the excessive DP tree rules.
• NRtrie and NRtree provide the trade-off between the size
of the on-chip memory and TCAM.
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Architecture
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Performance evaluations
• We set a limit on αT = 0.1 (the ratio of the number of
rules stored in the TCAM over the total number of rules
of the given ruleset).
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Performance evaluations
• Xilinx ISE 12.4, with Xilinx Virtex-5 XC5VFX200T with −2
speed grade