Design of a ‘Single Event Effect’
Mitigation Technique for
Reconfigurable Architectures
SAJID BALOCH
Supervisory Team
I V ER
S
TH
E
R
GH
Y
OF
Baloch
Dr.Adrian Stoica3
IT
E
UN
Prof. Dr. T. Arslan1,2
DI N BU
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ACRONYMES
–
–
–
–
–
–
–
–
–
–
–
Baloch
SEU (Single Event Effect)
SET (Single Event Transient)
SEB (Single Event Burnout)
SEL (Single Event Latch-up)
Cfg (Configuration)
EDAC (Error Detection and Correction)
SoC (System on Chip)
FPGA (Field Programmable Gate Array)
DEU (Double Event Upset)
TEU (Triple Event Upset )
MEU (Multiple Event Upsets)
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a) FPGAs
- SRAM
DSP
IP
- Anti Fuse
- EPROM
IP
MEMORY
Reconfigurable
Array
b) Reconfigurable SoC
- General purpose
- Domain Specific
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MEMORY
RECONFIGURABLE
ARCHITECTURES
Re-Configurable SoC Architecture
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RADIATION EFFECTS
RE-CONFIGURABLE ARCHITECTURES
– PERMANANT FAULTS (due to SEL, SEB etc)
– TEMPORARY FAULTS (due to SEU etc)
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SEU MITIGATION TECHNIQUES
a) HARDWARE REDUNDANCY
- Dual Modular Redundancy (DMR)
- Triple Modular Redundancy (TMR)
- EDAC Codes
- Process Technology
b) TIME REDUNDANCY
c) COMBINATION (Hardware & Time)
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Radiation Hardening
SEU EFFECTS
• TRANSIENT FAULTS (Data Memory etc)
• PERMANANT FAULTS (Cfg. Memory)
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Combinational
Logic Circuits
D-Flip Flop
Data_in
D-Flip Flop
SEU EFECTS
Synchronous Circuits
Data_out
Clock
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D-Flip Flop
SEU EFECTS
Configuration Memory
LUT
M
M
M
M
M
M
SEU (BITFLIP)
M
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SEU EFECTS
ROUTING OF A SIGNAL
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CLUSTER
CLUSTER
CLUSTER
CLUSTER
CLUSTER
CLUSTER
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Proposed SEU/SET Mitigation
Technique
based on:
• Temporal Data Sampling
• Weighted Voting
Salient Features of The Proposed Technique:
Auto Correction Mechanism for
• 100% SEU Recovery
• 100% Double Fault Recovery
• Voter Faults Recovery
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Temporal Sampling
Primary
Section
Data
S
SET
Q
Secondary
Section
1
S
L1
R
CLR
SET
Q
2
L2
Q
R
CLR
Q
CLk-A
S
SET
Q
3
S
L3
R
CLR
SET
Q
4
L4
Q
R
CLR
Q
CLk-B
S
SET
Q
5
S
L5
R
CLR
SET
Q
6
L6
Q
R
CLR
Q
CLk-C
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TEMPORAL SAMPLING
Clock Scheme
• 3 derivates of Main Clock
• Each Clock is Phase shifted
• 25% duty Cycle
2 Clock Cycles
CLOCK
CLk-A
CLk-B
Computation Cycle
CLk-C
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Weighted Voter Circuit
Minimized Term
X4.X3.X0 +
X5.X3.X0 +
X5.X4.X0 +
X4.X3.X1 +
X5.X3.X1 +
X5.X4.X1 +
X4.X3.X2 +
X5.X3.X2 +
X5.X4.X2 +
X5.X4.X3 +
X3.X2.X1.X0 +
X4.X2.X1.X0 +
X5.X2.X1.X0
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Case Example
SEU in Secondary Section
Node
Baloch
Before
SEU
After
SEU
Voting Weights
‘1’
‘0’
1
1
1
2
-
3
1
1
2
-
5
1
1
2
-
2
1
0
-
1
4
1
1
1
-
6
1
1
1
-
14
Total Votes
‘1’
‘0’
8
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Case Example
Multiple Bit Upset
Node
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Before
SEU
After
SEU
Voting Weights
‘1’
‘0’
1
1
1
2
-
3
1
0
-
2
5
1
0
-
2
2
1
0
1
-
4
1
1
1
-
6
1
1
1
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Total Votes
‘1’
‘0’
5
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Hardware Implementation of
Proposed Scheme with
Auto-Correction Mechanism
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Single Event Transition Fault
Data / Clock
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SEU/SET Simulator
•SEU’s can be injected at instance
•SEU of any duration can be injected
•Multiple upsets can be injected
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Performance Analysis
Fault Coverage
Mitigation Scheme
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%age Fault Tolerance
SET
SEU
DEU
TEU
Proposed Scheme
100%
100%
100%
50%
F. Lima etal Scheme
63%
100%
-
-
D. Mavis etal Scheme
100%
100%
32%
18%
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Performance Analysis
Area Overhead
450
Area (u square meter)
400
350
300
250
200
150
100
50
0
Proposed Technique
Mavis etal Technique
Results are based on:
0.13µm CMOS technology
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