ARM Cortex-M0
CORTEX-M0 Structure Discussion 3
August 23, 2012
Paul Nickelsberg
Orchid Technologies Engineering and Consulting, Inc.
www.orchid-tech.com
Cortex-M0 Structure Discussion 3
Topics Today
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CORTEX-M0
CORTEX-M0
CORTEX-M0
CORTEX-M0
Power Management
Fault Handling
Stack Structures
SVC/WFE/WFI Instructions
Cortex-M0 Power Management
Our discussion focuses on Cortex-M0 Power Management
as distinct from additional power management features which
may be implemented by a particular device vendor
Cortex-M0 Power Management
Low Power Instruction Execution
Device Specific Power Management
Peripheral Power On/Off Control
Sleep Mode Support
Phase Locked Loop Control
Deep Sleep Mode Support
Peripheral Clock Source Control
Wake-Up Interrupt Controller
Peripheral Clock Rate Control
WFE / WFI Instruction Support
State Saving Registers
Real Time Clock Features
On-Chip Oscillator Support
Cortex-M0 Power Management
Approx Current in mA
Low Power Instruction Execution
Approx Speed in MHz
Cortex-M0 Power Management
Cortex-M0 Power Modes
• Sleep Mode
Stops Processor Clock
• Deep Sleep Mode
Stops System Clock, Power off PLL, and Memory
• Mode Selection made using SCB Register
Cortex-M0 Power Management
Cortex-M0 Entry into Power Saving Modes
• WFI Instruction
Execution of WFI Instruction causes processor to immediately
enter selected sleep mode
• WFE Instruction
Execution of WFE Instruction causes processor to enter selected
sleep mode if event bit is set
• Exit Processor Exception
If SLEEPONEXIT bit is set in SCB Register, processor enters
selected sleep mode on return from exception to thread mode
Cortex-M0 Power Management
Cortex-M0 Exit from Power Saving Modes
• Wake-Up from WFI or SLEEPONEXIT
Upon receipt of Prioritized Interrupt, processor immediately
resumes execution of instructions
• Wakeup from WFE
Upon receipt of Prioritized Interrupt or external event signal,
processor immediately resumes execution of instructions
• Wakeup using WIC
Upon receipt of Wake-up Interrupt Controller Signal, processor
immediately resumes execution of instruction. This feature is
optional and when implemented usually applies to Deep Sleep
wakeup only
Cortex-M0 Power Management
Full Pwr
Low Pwr
Time
Normal Instruction Execution
Sleep
Normal Instruction Execution
Cortex-M0 Fault Handling
• HARDFAULT Vector
The HARDFAULT Vector catches processor faults
• Processor Faults
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SVC Instruction Priority Error
BKPT w/o Debugger
System Generated Bus Error
Attempted execution of instruction in XN Memory Area
Attempted execution of undefined instruction
Attempted load or store to unaligned address
• Processor Lockup (Double Fault)
Occurs when Fault occurs in NMI or HARDFAULT Handler
Cortex-M0 Fault Handling
Normal Instruction Execution
HardFault
Lock Up
Normal Instruction Execution
HardFault Exception preempts all other exceptions
Reset or NMI restarts processor
Cortex-M0 Stack Structure
• Cortex-M0 Stack pushes data onto the stack
from higher to lower addresses
SP
SP + 0x1C
SP + 0x18
SP + 0x14
SP + 0x10
SP + 0x0C
SP + 0x08
SP + 0x04
SP + 0x00
Content
PSR
PC
LR
R12
R3
R2
R1
R0
SP Here before Interrupt
SP Here after Interrupt
Processing Capability
Meaning and Implications
32 Bit
CORTEX-M0
8 Bit
Architecture
- Low Power Instruction Execution
- Sleep Power Mode
- Deep Sleep Power Mode
- WFI / WFE Sleep Entry
- Fault Handling
Processor Architecture – 8 Bit World to 32 Bit World