USART
USART
1
USART
Dependencies
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PMC has to be programmed 1st for USART to work
PIO Controller has to be programmed for the pins to behave as intended
The USART configuration can be done before enabling the USART clock
Depending on application needs, the USART clock can be stopped when not
needed after restart the USART resumes its operations where it left off
2
USART
USART Features
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Independent Programmable Baud Rate Generator
5- to 9-bit Full-duplex Synchronous Asynchronous Serial Communications
Hardware Handshaking RTS-CTS
Modem Signal Management DTR-DSR-DCD-RI
RS485 with Driver Control Signal
ISO7816, T = 0 or T = 1 Protocols for Interfacing with Smart Cards
IrDA Modulation and Demodulation Communication at up to 115.2 Kbps
MSB or LSB support
5 Parity mode
Time Guard generation
Break generation
Framing Error
Test Modes
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Remote Loopback, Local Loopback, Automatic Echo
3
USART
USART: Block Diagram
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Common USART Signals:
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SCK Serial Clock
RXD Receive Data
RTS Request To send
TXD Transmit Data
CTS Clear To Send
Modem Signals:
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DTR Data Terminal Ready
DSR Data Set Ready
DCD Data Carrier Detect
RI Ring Indicator
4
USART
USARTs on AT91SAM7S64
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2 USARTs embedded:
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USART0, USART1
Full Modem Line Support ONLY on USART1
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Each USART have its own Baud Rate generator
Modem Signals available only on USART1
5
USART
Baud Rate Generator
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The baud rate generator provides the bit period clock named Baud Rate
clock
Based on a 16-bit divider, programmable thanks to CD field of the
US_BRGR (Baud rate Generator Register)
The clock source is programmable through the USCLKS field in the US_MR
(Mode Register):
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AT91SAM7S64 Master Clock MCK
A division of MCK (CD field)
External Clock provides on SCK
Baud Rate Error :
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In most of the cases needs to be < 5%
In IrDA mode needs to be < 1.87%
6
USART
USART Modes vs Baud Rate Calculation
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Synchronous:
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Asynchronous:
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ISO7816:
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ISO7816 Bit rate
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ISO7816 bit rate is the duration of a bit in number of ISO7816 clock cycles
ISO7816 Clock is provided to the USART SCK pin to feed the SMART card clock
Fi_Di_Ratio is defined in accordance to ISO7816 standard and the Smart Card
application user.
Note: On reset Fi_Di_Ratio is set to 372 value
7
USART
Baud Rate Generator
8
USART
Asynchronous Receiver Mode
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Valid Start Detection :
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A LOW level on RXD is interpreted as a valid
START bit if it is detected for more than 8
cycles of the sampling clock, which is 16
times the baud rate when OVER =0
OVER=1 , 4 cycles of the sampling clock
9
USART
Asynchronous Receiver Mode
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The RXD line is sampled by the Receiver
US_MR
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SYNC field =0
OVER 1-bit field
• =0 RXD line over samples 16 times the Baud Rate Clock
• =1 RXD line over samples 8 times the Baud Rate Clock
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ONLY 1 STOP bit is read
As soon as the STOP bit is sampled, the receiver is looking for a new valid
START bit
10
USART
Synchronous Receiver Mode
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The RXD line is sampled at each rising edge of Baud Rate Clock
Baud Rate Clock Max = MCK
Synchronous mode allows HIGH speed transfer
US_MR (SYNC 1-bit field =1)
Valid START bit is a LOW level detected on RXD
11
USART
Transmitter Mode
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Start bit, data bits, parity bit and stop bits are
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Shifted on falling edge of the Baud Rate clock
Sampled at each rising edge of Baud Rate Clock
12
USART
IrDA Mode
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Half Duplex point to point wireless communication
USART embeds infrared modulator and demodulator compliant with IrDa
specification version 1.1
Data transfer from 2.4Kb/s up to 115.2Kb/s
IrDA mode activated by setting USART_MODE field to value 0x8 in the US_MR
Use the same logic as the ISO7816, the IrDA activation is mandatory by setting
a non zero value to the Fi_Di field (US_FIDI register)
IrDA Filter Register (US_IF) configures the demodulator filter
13
USART
IrDA Modulation
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Modulator is based on IrDA Transmitter
Based on Return to Zero Inverter (RZI) modulation
“0” is represented a a light pulse with a duration of 3/16 of a bit time
14
USART
IrDA Demodulation
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Demodulator is based on IrDA Receiver
Non zero value of US_IF field allows a 8-bit counter to validate that the RX line
is kept to value zero during a time of US_IF x 1/MCK
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RX line is NOT asserted during this time the counter restart with US_IF value and
count down for reach 0.
RX line is asserted and after the data bits (pulse) on RX are validated.
15
USART
IrDA Mode Specific Registers
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US_IF: Infra-Red
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Sets the filter of the IrDA demodulator
IrDA demodulator available on the receiver part
IRDA_FILTER 8-bit field
determine the duration necessary to valid the RX line
US_FIDI:
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FI_DI_RATIO 11-bit field
1 – 2047 value range
MUST be set to a non-zero value
16
USART
ISO7816 Mode
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USART interface for Smart Cards and Security Access Module
ISO7816 T=0 and T=1 protocols supported
Half Duplex Mode
TXD line is bi-directional
Fixed Data Format ( Automatic set up of the corresponding fields)
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8 data bits
Even parity
1 or 2 stop bit
17
USART
ISO7816 Mode
US_MR settings
ONLY for T=0
MAX_ITERATION NBSTOP USCLKS USART_MODE CLKO
field value:
0x1 min , max 0x7
0x0 or 0x2
0x0 or 0x1
0x4 T=0, 0x6 T=1
0x1
ISO7816 mandatory fields
INACK MSBF OVER
optional fields
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ISO7816 T=0 without parity error
As there is no parity error the RXD line is set to one during the time guard and allow the next
character to be sent
18
USART
ISO7816 Mode
NACK
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ISO7816 T=0 with parity error and NACK generation
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RXD line is set to zero during the time guard
NACK is activated and add one bit after the time guard
Repetition of the character is done according to the MAX_ITERATION field
value in the US_MR
The Receiver does not put the erroneous value on the US_RHR register
PARE field is activated in the US_CSR
If Inhibit NACK is set on the US_MR, the Error is not driven on the I/O line and
the INACK is set on the US_CSR
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19
USART
ISO7816 Mode Specific Registers
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US_NER: Number of Errors
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US_FIDI:
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FI_DI_RATIO 11-bit field
1 – 2047 value range :completes the Baud Rate set up
The clock provided on SCK is divided by FI_DI_RATIO
FI_DI Ratio Example MCK=SCK=18.432 Mhz CD=5
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NB_ERRORS 8-bit field gives the total number of errors that occurred during an
ISO7816 transfer
8- bit counter
automatically clears when read
SmartCard needed Clock= 3.686Mhz = MCK/CD
ISO7816_ClockBit Rate= ISO7816_Clock/Fi_Di_Ratio= 38400
ISO7816_Clock => 18.432/5=3.686Mhz for an equivalent baudrate of 38400 we
have 38400=MCK/CD/Fi_Di => Fi_Di = 3.686M/38400=96
The bit rate is the duration of a bit in number of ISO7816_Clock
20
USART
RS485 Mode
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USART_MODE 2-bit field of US_MR set to 0x01 value
RS485 mode enables line driver control
USART as the Same behavior than in Asynchronous or synchronous
Mode
RTS pin is driven HIGH when the Transmitter is operating
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TXEMPTY flag controls RTS line behavior
21
USART
RS485 Mode
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RTS pin is driven at inverse level than the TXEMPTY bit
RTS in HIGH level means that a transmission is in progress
Below an example with Timeguard set
22
USART
Modem Mode
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USART_MODE in the Mode Register (US_MR) is set to the value 0x3.
In Modem Mode :
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USART acts as in asynchronous mode
All the asynchronous parameters are available
provides the current state of the control lines from the modem to the CPU
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TXD
RTS: Request To Send
DTR: Data Terminal Ready
RXD
CTS: Clear To Send
DSR: Data Set Ready
DCD: Data Carrier Detect
RI: Ring Indicator
23
USART
Modem Mode
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USART acts as a Data Terminal Equipment
USART drives DTR and RTS signals
USART detects a level change on
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DSR means DSRIC bit of the Status Register is set and can trigger an interrupt
DCD means DCDIC bit of the Status Register is set and can trigger an interrupt
CTS means CTSIC bit of the Status Register is set and can trigger an interrupt
RI means RIIC bit of the Status Register is set and can trigger an interrupt
CTS to HIGH level disable the Transmitter, once the character transmission is
completed
24
USART
USART Test Modes
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3 USART Test Modes
Allow on-board diagnostics
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Normal Mode
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RXD pin on the receiver input
TXD pin on the the transmitter output
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25
USART
USART Test Modes
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Automatic Echo Mode: Bit by bit retransmission
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A bit is received on the RXD pin is sent to the TXD pin
Programming the transmitter as no impact on TXD
Receiver is active
26
USART
USART Test Modes
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Local Loop Back
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Direct Connection between the transmitter output and the receiver input
TXD and RXD pins are not used:
• RXD pin has no effect on the receiver
• TXD pin is continuously driven high
27
USART
USART Test Modes
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Remote Loop Back Mode: bit-by-bit retransmission.
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Direct connection of the RXD pin to the TXD pin
Transmitter and the Receiver are disabled and have no effect
28
USART
Multidrop Mode
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PAR 3-bit field of US_MR set to 11x value
DATA and ADDRESS characters follow the rule:
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Receiver
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Parity bit set to ONE means ADDRESS character
Parity bit set to ZERO means DATA character
PARE bit of the Status Register is SET while receiving an address character
No parity error can be detected
PARE bit reset when active RSTSTA bit of the Control register
Transmitter
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SENDA bit need to be SET in the Control Register while sending an address
character (US_THR)
SENDA to level zero, a data character will be write in the US_THR
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USART
USART Options
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USART Options:
- Parity
- Break
- Timeguard
- Time-Out
USART options can be used when using the USART in SYNCHRONOUS
and ASYNCHRONOUS modes
Timeguard and Time-out delays are limited by the Baud rate
30
USART
Framing Error
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Can be detected only on Receiver side
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The STOP bit is detected to level ZERO
FRAME bit is set on the Status Register (US_CSR)
• On the middle of the stop bit
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FRAME is cleared by writing the RSTSTA bit of the Control Register (US_CR)
31
USART
Parity Options
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5 parity modes:Odd, Even, Mark, Space, None
Even parity example:
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If the number of set bits is even, it sets the parity bit to 0; if the number of set bits is
odd, it sets the parity bit to 1. In this way, every data has an even number of set bits.
On the receiving side, the device checks each byte to make sure that it has an even
number of set bits. If it finds an odd number of set bits, the receiver knows there was
an error during transmission
Below Parity True table associated with an example
32
USART
Parity Options
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Configurable through the PAR (3-bit) field of the US_MR
Parity Error detection:
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sets the PARE (Parity Error) bit in US_CSR
PARE bit cleared by writing US_CR with the RSTSTA bit at 1
33
USART
Timeguard Options
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Allows transmission with SLOW remote devices
The Transmitter insert an ‘idle state’ between 2 characters
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‘idle state’ is a HIGH level on the TXD line
Duration of the ‘idle state’ is programmable through the Timeguard register
(US_TTGR):
• TG x Bit Period
• TG is 8-bit field, programmable up to 255 value
• TG =0 means no Timeguard programmed
34
USART
Timeguard Options
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Change TXRDY and TXEMPTY normal behavior
TXRDY rises ONLY at the start bit of the next character
TXRDY remains to ZERO during Timeguard if the character is written in
US_THR
TXEMPTY rises at the end of the character transmission and after the
Timeguard
35
USART
Break Options
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Transmit a BREAK condition on the TXD line
Break TXD line is driven to Low level:
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The Transmission is Stopped until the Break is completed and cleared
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Duration, at least one complete character transmission
Break equivalent frame is a zero character with parity and stop bit at 0
Only one break a time
Completed: duration constraints
Cleared: STPBRK bit set in the US_CR, allow the TXD line to transmit
After the Break, TXD line remains HIGH
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During a minimum of 12 bit times or Timeguard value if set to a upper value that 12
Ensure that the Remote receiver detect the end of the Break to prevent the lose of t
he next sent character
36
USART
Break Options
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Transmit a BREAK condition on the TXD line
USART configuration: 8-bit data, parity enable, 1 stop bit, no Timeguard
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Start Break active at the END of the current Character transfer
Stop Break is active ONLY after the Minimal Break duration
Minimal Break Transmission duration = Character transmission duration
End of the Break duration = 12 bit time
37
USART
Time-Out Options
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Allow the Receiver to handle variable length frames
Receive a Time-Out condition on the RXD line
RXD line is driven to HIGH level:
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Time-out delay period is set on the TO 16-bit field of the Receiver Time-Out
(US_RTOR)
Time-Out Delay = T0 x Bit Time
A 16-bit counter start decrement from the TO value to 0
Each character received re-start the Time-Out Counter
End of the Time-Out, the TIMEOUT bit is set in Status register (US_CSR)
On the Control Register:
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RETTO-bit, Reload and Start Time-Out allows a periodic interrupt while no character
received
STTO-bit, Start Time-out. One character must be received before active the
Time_Out, and an interrupt is performed when Time-Out occurs
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USART
Hardware Handshaking Option
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Flow control by connected
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RequesToSend RTS
ClearToSend CTS
Same behavior than in Asynchronous or synchronous Mode
PDC channels are mandatory
39
USART
Hardware Handshaking Option
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Receiver
RTS line is driven HIGH means receiver disable and the PDC Receive Buffer is Full
Receiver Enables RTS line is driven LOW
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Transmitter
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CTS line driven HIGH disable the
Transmitter
CTS is driven HIGH after completed
the character transmission
40
USART
USART & Peripheral DMA Controller
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Kind of DMA dedicated to a peripheral operation
Minimum CPU overhead/per transfer : 2 cycles
Increase the microcontroller performance
Decrease the power consumption
Several channels: Receiver,Transmitter
Integrated PDC user interface on USART memory space:
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32-bit Transmitter and Receiver Pointer Registers
• Buffer Address
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16-bit Transmitter and Receiver Counter Registers
• Buffer Size
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32-bit Transmitter and Receiver NEXT Pointer Registers
• Buffer Address
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16-bit Transmitter and Receiver NEXT Counter Registers
• Buffer Size
41
USART
USART PDC Register Locations
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Control registers start at peripheral address offset by 0x100
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0x100 : US_RPR : USART Receive Pointer Register, Read/Write
0x104 : US_RCR : USART Receive Counter Register, Read/Write
0x108 : US_TPR : USART Transmit Pointer Register, Read/Write
0x10C : US_TCR : USART Transmit Counter Register, Read/Write
0x110 : US_RNPR : USART Receive Next Pointer Register, Read/Write
0x114 : US_RNCR : USART Receive Next Counter Register, Read/Write
0x118 : US_TNPR : USART Transmit Next Pointer Register, Read/Write
0x11C : US_TNCR : USART Transmit Next Counter Register, Read/Write
0x120 : US_PTCR : USART PDC Transfer Control Register, Write-only
0x124 : US_PTSR : USART PDC Transfer Status Register, Read-only
USART0 control registers for SAM7S start at address 0 xFFFC 0000
USART0 PDC control registers start at address 0 xFFFC0100
USART1 control registers for SAM7S start at address 0 xFFFC 4000
USART1 PDC control registers start at address 0 xFFFC 4100
42
USART
USART Interrupts
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USART Interrupt Enable Register US_IER (Write Only)
0 = No effect
1 = Enable
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USART Interrupt Disable Register US_IDR (Write Only)
0 = No effect
1 = Disable
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USART Interrupt Mask Register US_IMR (Read Only)
0 = Not enabled
1 = Enabled
US_IER, US_IDR, US_IMR
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CTSSIC
TIMEOUT
9
DCDIC
PARE
7
18
DSRIC
FRAME
6
17
RIIC
RXBUFF
6
16
NACK
OVRE
5
13
RXBUFF
ENDTX
4
12
ITERATION
ENDRX
3
2
10
TXEMPMTY
1
RXBRK TXRDY
9
RXRDY
0
43
USART
USART Interrupts
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RXRDY: RXRDY
TXRDY: TXRDY
RXBRK: Receiver Break
ENDRX: End of Receive Transfer
ENDTX: End of Transmit
PDC Related
TXBUFE: Buffer Empty
RXBUFF: Buffer Full
OVRE: Overrun Error
FRAME: Framing Error
PARE: Parity Error
TIMEOUT: Time-out
TXEMPTY: TXEMPTY
ITERATION: Iteration
NACK: Non Acknowledge
RIIC: Ring Indicator Input Change
DSRIC: Data Set Ready Input Change
DCDIC: Data Carrier Detect Input Change Modem Mode Related
CTSIC: Clear to Send Input Change
44
USART
USART & AT91 Software Libraries
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USART Standalone software examples are provided
USART Standard Modes example
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Send / receive Characters
With the PDC features activated or not
Interrupt managements
AT91SAM7S64.h file describes all the peripherals and their dedicated registers
lib_AT91SAM7S64.h file contains ‘inline more common USART functions:
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PIO configuration
USART Clock activation through the Power Management Controller
Baud Rate function
45
USART
USART & AT91 CD-ROM Tools
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USART Utility Javascript tools:
Setting of USART Baud Rate according to the:
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Mode required
Master Clock source
Baud Rate required
Gives the value to set in the USART mode register, and specific register according
to USART Mode
46
USART
USART Summary
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The USART support all following facilities:
Several modes supported:
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Asynchronous, Synchronous, Modem, ISO7816, IrDA, RS485, 3 test modes
5 to 9 byte length data length
MSB or LSB support
1, 1.5 or 2 Stop bits
5 parity mode
Over sampling control
Time Guard generation
Break generation
Framing Error
Hardware Handshaking
Time-Out
47