Lecture 14 DMA Controller & Serial
Communications Interface (UART)
Outline
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Transfer Mode
Extended Repeat Area Function
Address Update Function Using Offset
Group Scan Mode
Interrupt Sources
Registers
Serial Communications Interface
Operation in Asynchronous Mode
Overview
 The RX210 Group incorporates a 4-channel direct memory
access controller (DMAC)
 Performs data transfers without the CPU

When a DMA transfer request is generated, the DMAC transfers
data stored at the transfer source address to the transfer
destination address
 Transfer space: 512 Mbytes

0000 0000h to 0FFF FFFFh and F000 0000h to FFFF FFFFh excluding
reserved areas
 Maximum transfer volume: 1M data

Maximum number of transfers in block transfer mode: 1,024 data ×
1,024 blocks
 Channel priority: Channel 0 > 1 > 2 > 3 (Channel 0: Highest)
 Transfer data

Single data: Bit length: 8, 16, 32 bits

Block size: Number of data: 1 to 1,024
 Power consumption reduction function: Module stop state
Transfer Mode
 Normal transfer mode
 One data is transferred by one transfer request

A maximum of 65535 can be set as the number of transfer
operations using the DMCRAL of DMACm
 When these bits are set to 0000h, no specific number of
transfer operations is set

Performed with the transfer counter stopped (free running mode)
 Setting DMCRB of DMACm is invalid in normal transfer mode
 A transfer end interrupt request can be generated after
completion of the specified number of transfer operations

Except in free running mode
 The register update operation in normal transfer mode
Transfer Mode (cont.)
 The operation in normal transfer mode
Transfer Mode (cont.)
 Repeat transfer mode
 One data is transferred by one transfer request

A maximum of 1K data can be set as a total repeat transfer size
using DMCRAH of the DMACm

A maximum of 1K can be set as the number of repeat transfer
operations using DMCRB of the DMACm
A maximum of 1M data (1K data × 1K count of repeat transfer
operations) can be set as a total data transfer size
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 Either the transfer source or transfer destination can be
specified as a repeat area

When transfer of the repeat size data is completed, the address of
the specified repeat area (DMSAR or DMDAR) returns to the
transfer start address
 DMA transfer can be stopped

When data of the specified repeat size has all been transferred in
repeat transfer mode

The repeat size end interrupt can be requested

DMA transfer can be resumed by writing 1 to DTE bit in DMCNT
Transfer Mode (cont.)
 A transfer end interrupt request can be generated

After completion of the specified number of repeat transfer
operations
 The register update operation in repeat transfer mode
Transfer Mode (cont.)
 The operation in repeat transfer mode
Transfer Mode (cont.)
 Block transfer mode
 A single block data is transferred by one transfer request

A maximum of 1K data can be set as a total block transfer size
using DMCRA of the DMACm

A maximum of 1K can be set as the number of block transfer
operations using DMCRB of the DMACm
A maximum of 1M data (1K data × 1K count of block transfer
operations) can be set as a total data transfer size

 Either the transfer source or transfer destination can be
specified as a block area

When transfer of a single block data is completed, the address of
the specified block area (DMSAR or DMDAR of the DMACm) returns
to the transfer start address
 DMA transfer can be stopped

When a single block data has all been transferred in block mode

The repeat size end interrupt can be requested

DMA transfer can be resumed by writing 1 to the DTE bit in DMCNT
of DMACm in the repeat size end interrupt handling
Transfer Mode (cont.)
 Transfer end interrupt request can be generated

After completion of the specified number of block transfers
 The register update operation in block transfer mode
Transfer Mode (cont.)
 The operation in block transfer mode
Extended Repeat Area Function
 Supports a function to specify the extended repeat areas on
the transfer source and destination addresses
 The address registers repeatedly indicate the addresses of the
specified extended repeat areas

The extended repeat areas can be specified separately to the
transfer source address register (DMSAR) and transfer destination
address register (DMDAR) of DMACm

The extended repeat area on the source address is specified by the
SARA[4:0] bits in DMAMD of DMACm
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The extended repeat area on the destination address is specified by
the DARA[4:0] bits in DMAMD of DMACm
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The size can be specified separately for the source and destination
sides
 The area which is specified as the repeat area or block area
should not be specified as the extended repeat area
 DMA transfer is stopped

When the address register value reaches the end address of the
extended repeat area and the extended repeat area overflows
Extended Repeat Area Function (cont.)

An interrupt by an extended repeat area overflow can be requested
 When an overflow occurs in the extended repeat area on the
transfer source while the SARIE bit in DMINT of DMACm is set

The ESIF flag in DMSTS of DMACm is set to 1

The DTE in DMCNT of DMACm is cleared to 0 to stop DMA transfer

If the ESIE bit in DMINT of DMACm is set to 1, an interrupt by an
extended repeat area overflow is requested
 When the DARIE bit in DMINT of DMACm is set to 1

The DMDAR becomes a target to apply the function
 DMA transfer can be resumed by writing 1 to the DTE bit in
DMCNT of DMACm in the interrupt handling.
 An example of the extended repeat area operation
 Eight bytes are specified as an extended repeat area
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By the lower three bits of DMACm.DMSAR
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SARA[4:0] bits in DMACm.DMAMD = 00011b
 The data size is eight bits
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SZ[1:0] bits in DMACm.DMTMD = 00b
Extended Repeat Area Function (cont.)
Address Update Function Using Offset
 The source and destination addresses can be updated by
fixing, increment, decrement, or offset addition
 When the offset addition is selected
 The offset specified by the DMA offset register (DMOFR of
DMAC0) is added to the address

Every time the DMAC performs one data transfer
 This function realizes a data transfer where addresses are
allocated to separated areas
 Offset subtraction can also be realized by setting a negative
value in DMOFR of DMAC0

The negative value must be 2’s complement
 Address update function using offset can be specified only for
the DMAC0 channel
 The address update method in each address update mode
Address Update Function Using Offset (cont.)
 An example of address updating using offset addition
 The transfer data is 32 bits long
 Offset addition is set as transfer source address update mode
 Increment is set as transfer destination address update mode

The second and subsequent data is each read from the transfer
source address obtained by adding the offset value to the previous
address

The data read from the addresses at the specified intervals is
written to the continuous locations on the destination
Address Update Function Using Offset (cont.)
Activation Sources
 DMAC activation by software
 Setting the DCTG[1:0] bits in DMTMD of DMACm to 00b
 To start DMA transfer by software, set the DTE bit in DMCNT of
DMACm to 1 (DMA transfer is enabled)

The SWREQ in DMREQ of DMACm to 1 (DMA transfer is requested)

With the DMST bit in DMAST set to 1 (DMAC activation enabled)
 When the DMAC is activated by software while the CLRS bit in
DMREQ of DMACm is 0

The SWREQ bit in DMREQ of DMACm is cleared to 0 after data
transfer is started in response to a DMA transfer request
 As the DMAC is activated by software while the CLRS bit is 1

The SWREQ bit is not cleared to 0 after data transfer is started

A DMA transfer request is issued again after completion of a
transfer
 DMAC Activation by interrupt requests from on-chip
peripheral modules or external interrupt requests
Activation Sources (cont.)
 The activation source can be selected separately for each
channel using the DMRSRm registers (m = 0 to 3) of the ICU
 Generated while the DCTG[1:0] bits in DMTMD of DMACm is set
to 01b
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The DTE bit in DMCNT of DMACm is set to 1 (DMA transfer is
enabled)
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The DMST bit in DMAST is set to 1 (DMAC activation is enabled)
 Another activation request cannot be accepted during the
transfer of other DMAC channel or DTC
 When the proceeding transfer is completed, channel arbitration
is performed

A DMA transfer request of the highest priority channel is accepted

DMA transfer of the channel starts
 When DMA transfer starts, the ACT bit in DMSTS of DMACm is
set to 1 (the DMAC is in the active state)
Ending DMA Transfer
 The operation for ending DMA transfer depends on the
transfer end conditions
 When DMA transfer ends, the DTE bit in DMCNT and the ACT
flag in DMSTS of DMACm are changed from 1 to 0

Indicating that DMA transfer has ended
 Transfer end by completion of specified total number of
transfer operations
 In normal transfer mode (DMACm.DMTMD.MD[1:0] = 00b)

When the value of DMCRAL of DMACm changes from 1 to 0, DMA
transfer ends on the corresponding channel
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The DTE bit in DMCNT of DMACm is cleared to 0
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The DTIF bit in DMSTS of DMACm is set to 1 at the same time
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If the DTIE bit in DMINT of DMACm is 1 at this time, a transfer end
interrupt request is issued to the CPU or the DTC
 In repeat transfer mode (DMACm.DMTMD.MD[1:0] = 01b)
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When the value of DMCRB of DMACm changes from 1 to 0, DMA
transfer ends on the corresponding channel
Ending DMA Transfer (cont.)

The DTE bit in DMCNT of DMACm is cleared to 0
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The DTIF bit in DMSTS of DMACm is set to 1 at the same time

If the DTIE bit in DMINT of DMACm is 1 at this time, an interrupt
request is issued to the CPU or the DTC
 In block transfer mode (DMACm.DMTMD.MD[1:0] = 10b)

When the value of DMCRB of DMACm changes from 1 to 0, DMA
transfer ends on the corresponding channel

The DTE bit in DMCNT of DMACm is cleared to 0

The DTIF bit in DMSTS of DMACm is set to 1 at the same time

If the DTIE bit in DMINT of DMACm is 1 at this time, an interrupt
request is issued to the CPU or the DTC

Before sending an interrupt request from the DMAC to the CPU or
the DTC, the interrupt control register must be set.
 Transfer end by repeat size end interrupt
 In repeat transfer mode, a repeat size end interrupt is
requested when transfer of a 1-repeat size of data is completed

While the RPTIE bit in DMINT of DMACm is set to 1
Ending DMA Transfer (cont.)

When the interrupt is requested to complete DMA transfer, the DTE
bit in DMCNT of DMACm is cleared to 0

The ESIF flag in DMSTS of DMACm is set to 1

If the ESIE bit in DMINT of DMACm is 1 at this time, an interrupt
request is issued to the CPU or the DTC

The transfer can be resumed by writing 1 to the DTE bit in DMCNT
of DMACm
 A repeat size end interrupt can be requested also in block
transfer mode
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The interrupt is requested in the same way as in repeat transfer
mode when transfer of a 1-block size data is completed
 Transfer end by interrupt on extended repeat area overflow
 An interrupt by an extended repeat area overflow is requested

When an overflow on the extended repeat area occurs while the
extended repeat area is specified and the SARIE or DARIE bit in
DMINT of DMACm is set to 1

The DMA transfer is terminated
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The DTE bit in DMCNT of DMACm is cleared to 0
Ending DMA Transfer (cont.)

The ESIF flag in DMSTS of DMACm is set to 1

If the ESIE bit in DMINT of DMACm is 1 at this time, an interrupt
request is issued to the CPU or the DTC

Even if an interrupt by an extended repeat area overflow is
requested during a read cycle, the following write cycle is
performed
 In block transfer mode, even if an interrupt by an extended
repeat area overflow is requested during a 1-block transfer

The remaining data in the block is transferred
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Transfer is terminated after a block transfer
Interrupt Sources
 Each DMAC channel can output an interrupt request to the
CPU or the DTC
 After transfer in response to one request is completed
 When the transfer destination is the external bus or the on-chip
peripheral bus
 An interrupt request is generated upon completion of data
write to the write buffer not to the actual transfer
destination
 The relation among the interrupt sources, the interrupt
status flags, and the interrupt enable bits
Interrupt Sources (cont.)
Interrupt Sources (cont.)
 The different procedures are used for canceling an interrupt
to restart DMA transfer
 Discontinuing or terminating DMA transfer
 Write 0 to the DTIF bit in DMSTS of DMACm to clear a transfer
end interrupt

Or to the ESIF bit in DMSTS of DMACm to clear a repeat size
interrupt and an extended repeat area overflow interrupt
 The DMACm remains in the stop state
 When starting another DMA transfer after that, set the
appropriate registers

Set the DTE bit in DMCNT of DMACm to 1 (DMA transfer enabled)
 Continuing DMA transfer
 Write 1 to the DTE bit in DMCNT of DMACm

The ESIF bit in DMSTS of DMACm is automatically cleared to 0
(interrupt source cleared)

DMA transfer is resumed
Registers
 DMA Source Address Register (DMSAR)
Registers (cont.)
 DMA Destination Address Register (DMDAR)
Registers (cont.)
 DMA Transfer Count Register (DMCRA)
Registers (cont.)
 DMA Block Transfer Count Register (DMCRB)
 DMA Transfer Enable Register (DMCNT)
Registers (cont.)
 DMA Transfer Mode Register (DMTMD)
Registers (cont.)
 DMA Address Mode Register (DMAMD)
Registers (cont.)
 DMA Offset Register (DMOFR)
 DMAC Activation Request Select Register m (DMRSRm)
Registers (cont.)
 DMA Software Start Register (DMREQ)
 DMA Module Activation Register (DMAST)
Registers (cont.)
 DMA Status Register (DMSTS)
Registers (cont.)
 DMA Interrupt Setting Register (DMINT)
Serial Communications Interface
 The RX210 Group has 13 independent serial
communications interface (SCI) channels
 The SCI is configured as SCIc module (SCI0 to SCI11) and
SCId module (SCI12)
 The SCIc (SCI0 to SCI11) can handle both asynchronous and
clock synchronous serial communications

Asynchronous serial data communications can be carried out with
standard asynchronous communications chips

Such as a Universal Asynchronous Receiver/Transmitter (UART) or
Asynchronous Communications Interface Adapter (ACIA)

As an extended function in asynchronous communications mode,
the SCI also supports smart card (IC card) interfaces conforming to
ISO/IEC 7816-3 (standard for Identification Cards)

Single-master operation as an simple I2C bus interface and simple
SPI interfaces are also supported
 As well as the functions of the SCIc module, the SCId module
(SCI12) supports an extended serial protocol

With a structure formed from Start Frames and Information Frames
Block Diagram
Operation in Asynchronous Mode (cont.)
 Example of data format in asynchronous serial
communications
 With 8-bit data, parity, two stop bits
 Any of 12 transfer formats can be selected according to the
SMR setting
Clock
 The SCI's transfer clock can be selected as
 Either an internal clock generated by the on-chip baud rate
generator or an external clock input to the SCKn pin

According to the setting of CM bit in SMR and CKE[1:0] bits in SCR
 When an external clock is input to the SCKn pin

The clock frequency should be 16 times the bit rate (ABCS = 0)

8 times the bit rate (when ABCS in SEMR = 1)

The base clock of TMR0 and TMR1 can be selected by the ACS0 bit
in SEMR of SCIn (n = 5, 6, 12)
 When the SCI is operated on an internal clock, the clock can be
output from the SCKn pin

The frequency of the clock output is equal to the bit rate

The phase is such that the rising edge of the clock is in the middle
of the transmit data
CTS and RTS Functions
 The CTS function is the use of input on the CTSn# pin in
transmission control
 Setting the SPMR.CTSE bit to 1 enables the CTS function

Placing the low level on the CTSn# pin causes transmission to start

Applying the low level to the CTS# pin while transmission is in
progress does not affect transmission of the current frame
 The RTS function uses the function of output on RTSn# pin
 A low level is output when reception becomes possible
 Conditions for low-level output

The value of the RE bit in the SCR is 1

Reception is not in progress

There are no received data yet to be read

The ORER, FER, and PER flags in the SSR are all 0
 Condition for high-level output

The conditions for low-level output have not been satisfied
SCI Asynchronous Mode Initialization
 Before transmitting and receiving data
 Start by writing the initial value “00h” to SCR
 Whenever the operating mode or transfer format is changed,
SCR must be initialized before the change is made
 When the external clock is used in asynchronous mode, ensure
that the clock signal is supplied even during initialization
 Clearing the SCR.RE bit to 0 initializes neither the ORER, FER,
and PER flags in SSR nor RDR
 Switching the value of the SCR.TE bit from 1 to 0 or 0 to 1
while the SCR.TIE bit is 1 leads to the generation of a TXI
interrupt request
SCI Asynchronous Mode Initialization (cont.)
 Sample SCI initialization flowchart (asynchronous mode)
Asynchronous Mode Serial Data Transmission
 In serial transmission, the SCI operates as
 The SCI transfers data from TDR to TSR when data is written to
TDR in the TXI interrupt processing routine

The TXI interrupt at the beginning of transmission is generated

When the TE bit in SCR is set to 1 after the TIE bit in SCR is set to 1

Or when these two bits are set to 1 simultaneously
 Transmission starts after the CTSE bit in SPMR is set to 0
(disabling the CTS function)

Or a low level on CTS# pin causes data transfer from TDR to TSR

If the TIE bit in SCR is 1 at this time, a TXI interrupt request is
generated

Continuous transmission is obtainable by writing the next data for
transmission to TDR in the TXI interrupt processing routine before
transmission of the current data for transmission is completed

When TEI interrupt requests are in use, set the SCR.TIE bit to 0
(disabling TXI requests) and the SCR.TEIE bit to 1 (enabling TEI
requests) after the last of the data to be transmitted are written to
the TDR from the processing routine for TXI requests
Asynchronous Mode Serial Data Transmission (cont.)
 Data is sent from the TXDn pin in the order

Start bit, transmit data, parity bit or multi-processor bit (may be
omitted depending on the format), and stop bit
 The SCI checks for updating of (writing to) TDR at the time of
stop bit output
 When TDR is updated, setting of the CTSE bit in SPMR to 0
(CTS function disabled) cause the next transfer of the next data

Or a low level input on the CTSn# pin

Transmission from TDR to TSR and sending of the stop bit

After that, serial transmission of the next frame starts
 If TDR is not updated, the TEND flag in SSR is set to 1

The stop bit is sent, and then the mark state is entered in which 1
is output

If the TEIE flag in SCR is 1 at this time, a TEI interrupt request is
generated
 A sample flowchart for serial transmission in asynchronous
mode
Asynchronous Mode Serial Data Transmission (cont.)
 Example of operation for serial transmission in asynchronous
mode
 From the middle of transmission until transmission completion
 With 8-bit data, parity, one stop bit
Asynchronous Mode Serial Data Reception
 In serial data reception, the SCI operates as
 When the value of the RE bit in SCR becomes 1

The output signal on the RTSn# pin goes to the low level
 When the SCI monitors the communications line

After detects a start bit, it performs internal synchronization, stores
receive data in RSR, and checks the parity bit and stop bit
 If an overrun error occurs, the ORER flag in SSR is set to 1

If RIE in SCR is 1 at this time, an ERI interrupt request is generated

Receive data is not transferred to RDR
 If a parity error is detected, the PER bit in SSR is set to 1 and
receive data is transferred to RDR

If RIE in SCR is 1 at this time, an ERI interrupt request is generated
 If a framing error (when the stop bit is 0) is detected, the FER
bit in SSR is set to 1 and receive data is transferred to RDR

If RIE in SCR is 1 at this time, an ERI interrupt request is generated
 When reception finishes successfully, receive data is transferred
to RDR
Asynchronous Mode Serial Data Reception (cont.)

If RIE in SCR is 1 at this time, an RXI interrupt request is generated

Continuous reception is enabled by reading the receive data
transferred to RDR in this RXI interrupt processing routine before
reception of the next receive data is completed

Reading out the received data that have been transferred to RDR
causes the RTSn# pin to output the low level
 Example of SCI operation for serial reception in
asynchronous mode
 With 8-bit data, parity, one stop bit
Asynchronous Mode Serial Data Reception (cont.)
 Example of SCI operation for serial reception in
asynchronous mode
 With 8-bit data, parity, one stop bit
 When RTS function is used
Asynchronous Mode Serial Data Reception (cont.)
 If a receive error is detected, an ERI interrupt request is
generated but an RXI interrupt request is not generated
 Data reception cannot be resumed while the receive error flag
is 1

Clear the ORER, FER, and PER bits to 0 before resuming reception
 Be sure to read the RDR during overrun error processing
 The states of the SSR status flags and receive data handling
when a receive error is detected
Registers
 Receive Shift Register (RSR)
 Receive Data Register (RDR)
 Transmit Shift Register (TSR)
 Transmit Data Register (TDR)
Registers (cont.)
 Serial Mode Register (SMR)
Registers (cont.)
 Serial Control Register (SCR)
Registers (cont.)
 Serial Control Register (SCR)
Registers (cont.)
 Serial Extended Mode Register (SEMR)
Registers (cont.)
 SPI Mode Register (SPMR)
Registers (cont.)
 I2C Mode Register 1 (SIMR1)
Registers (cont.)
 Smart Card Mode Register (SCMR)
Registers (cont.)
 Serial Status Register (SSR)