Dynamic Voltage and Frequency Scaling for
Optimal Real-Time Scheduling on Multiprocessors
Kenji Funaoka, Akira Takeda, Shinpei Kato, and Nobuyuki Yamasaki
Graduate School of Science and Technology
Keio University, Yokohama, Japan
Email: {funaoka,takeda,shinpei,yamasaki}@ny.ics.keio.ac.jp
Abstract— Not only system performance but also energy efficiency is critically important for embedded systems. Optimal real-time scheduling is effective to not only schedulability
improvement but also energy efficiency for the systems. In
this paper, real-time dynamic voltage and frequency scaling
(RT-DVFS) techniques based on the theoretically optimal realtime static voltage and frequency scaling (RT-SVFS) techniques
proposed in our previous work are presented for multiprocessor
systems. Simulation results show that RT-DVFS covers up the
disadvantages of RT-SVFS in the sense that RT-DVFS are not
practically affected by the difference among systems, whereas the
energy consumption of RT-SVFS highly depends on the selectable
processor frequency especially in high system utilization.
I. I NTRODUCTION
Multiprocessor architectures such as Simultaneous Multithreading (SMT) and Chip Multiprocessing (CMP) are becoming more attractive for intelligent embedded systems. It
is important for embedded systems that real-time tasks such
as robot controls and image processing meet their real-time
constraints. Consequently powerful processors are desirable
for these systems. On the other hand, the trade-off between
system performance and energy efficiency is critically important for battery-based embedded systems. Real-time operating
systems must go together with both requirements.
Real-time voltage and frequency scaling has been introduced to solve the problem. The processors of most recent
computer systems are based on CMOS logic. Maximum
processor frequency f depends on supply voltage V , and
energy consumption E is proportional to processor frequency
and square of supply voltage (i.e., E ∝ f V 2 ) [1]. Real-time
voltage and frequency scaling can potentially save energy at
a cubic order, while they meet real-time constraints. Realtime voltage and frequency scaling is based on the essential
characteristic of real-time tasks; namely the tasks can be
executed slowly as long as all deadlines are met. This goal
can be theoretically realized by real-time static voltage and
frequency scaling (RT-SVFS). However there is still room for
improvement on practical environments. The peak computing
rate is much higher than the average throughput that must be
sustained since most of real-time scheduling theories are based
on the worst-case analysis to meet real-time constraints. Realtime dynamic voltage and frequency scaling (RT-DVFS) can
save more energy by leveraging the characteristic.
Real-time voltage and frequency scaling techniques are
constructed on real-time scheduling theories to meet real-time
constraints. For single-processor systems, EDF [2] is an optimal real-time scheduling algorithm. On the other hand, EDFFF and EDF-US, which are the extensions for multiprocessors,
are not optimal [3], [4]. Approximately 50% processor time is
wasted to meet real-time constraints on the algorithms at the
worst-case. In other words, the algorithms theoretically require
twice as many processors or powerful processors as optimal
algorithms do. Accordingly the systems which leverage the
algorithms expend more energy than ideal. Fortunately three
optimal real-time scheduling algorithms for multiprocessors
are presented (i.e., PD2 [5], EKG [6], and LNREF [7], [8]).
PD2 incurs significant run-time overhead due to its quantumbased scheduling approach. EKG concentrates workloads on
some processors due to the approach similar to partitioned
scheduling. From the viewpoint of energy efficiency, energy
consumption is minimized when the workloads are balanced
among processors [9]. LNREF is an efficient algorithm on the
balance as compared to the other optimal algorithms.
The remainder of this paper is organized as follows. The
next section discusses the related work. In section III, we show
the system model. Sections IV and V explain LNREF and
RT-SVFS. In section VI, we present RT-DVFS techniques for
optimal real-time scheduling on multiprocessors. Section VII
evaluates the technique on practical environments. Finally we
conclude with a summary and future work in section VIII.
II. R ELATED W ORK
Many real-time voltage and frequency scaling techniques
have been proposed in many aspects for single processor
systems. Pillai and Shin [10] show a RT-SVFS technique based
on the optimal real-time scheduling algorithm EDF [2]. Our
uniform RT-SVFS on multiprocessors is analogous to EDFbased RT-SVFS. Real-time dynamic voltage and frequency
scaling (RT-DVFS) techniques are also proposed for hard realtime systems [10], soft real-time systems [11], and dynamic
real-time systems [12] to achieve more energy efficiency.
On the other hand, previous works such as [13], [14], [15]
for multiprocessors are based on partitioned scheduling or nonoptimal global scheduling. As mentioned above, the algorithms
require twice as many processors or powerful processors
as optimal algorithms do at the worst case. Our RT-SVFS
techniques [16] are the first work which leverages optimal realtime scheduling on multiprocessors. No RT-DVFS technique
based on optimal real-time scheduling is presented heretofore.
III. S YSTEM M ODEL
Optimal real-time voltage and frequency scaling on multiprocessors is a NP-hard partition problem since selectable
processor frequency is discontinuous on practical systems.
Consequently we assume that processor frequency can be controlled continuously at first. The effectiveness of the technique
is shown in the simulation on practical environments.
The problem of scheduling a set of hard periodic tasks
with voltage and frequency scaling on a multiprocessor system
is presented. The system is modeled as a taskset T =
{T1 , . . . , TN }, which is a set of N periodic tasks to be executed on M processors P = {P1 , . . . , PM }. Each processor Pk
is characterized by continuous normalized processor frequency
αk (0 ≤ αk ≤ 1). Each processor can execute at most
one task simultaneously. Each task can not be executed in
parallel among processors. Each task Ti is characterized by
two parameters, worst-case execution time ci and period pi .
A task Ti executed on a processor Pk requires ci /αk processor
time at every pi interval. The relative deadline di is equal to
its period pi . All tasks must complete the execution by the
deadlines. The ratio ci /p
i , denoted ui (0 < ui ≤ 1), is called
task utilization. U =
Ti ∈T ui denotes taskset utilization.
Maximum task utilization is defined as Umax = max{ui |Ti ∈
T}. We assume that all tasks may be preempted and migrated
among processors at any time, and are independent (i.e., they
do not share resources and do not have any precedence).
In this paragraph, the differences between the system model
and practical environments are discussed. (1) In practical
environments, operable processor frequencies are discontinuous. The set of operable frequencies is defined as f =
{f1 , . . . , fm |f1 < · · · < fm }. The lowest frequency fi ∈ f
such that αk ≤ fi /fm will be selected to bridge the gap between theory and practicality. (2) Processor throughput is not
proportional to processor frequency in many cases as opposed
to the system model described above. In practical systems,
the frequency which can achieve the corresponding system
throughput will be selected. (3) The system model assumes
that no overhead occurs at run-time. In practical environments,
the scaled frequency interferes with the scheduling even if
the frequency is not changed dynamically. The worst-case
overhead must be included in the worst-case execution time.
IV. T-N P LANE A BSTRACTION
T-N Plane Abstraction [7], [8] is an abstraction technique of
real-time scheduling. T-N Plane Abstraction is based on the
fluid scheduling model [17]. In the fluid scheduling model,
each task is executed at a constant rate at all times. Figure
1 illustrates the difference between the fluid schedule and a
practical schedule. The figure represents time on horizontal
axis and task’s remaining execution time on vertical axis. In
practical scheduling, the task will be blocked by the other
tasks as shown in the lower of the figure since a processor can
execute only one task simultaneously. In the fluid scheduling
model, each task Ti is executed along its fluid schedule
path, the dotted line from (ri , ci ) to (ri + pi , 0), where ri
is the release time of the current job. It is impossible for
remaining
execution time fluid schedule path
practical schedule path
ci
pi
release time
Ti
Fig. 1.
deadline
blocked
ri
time
Fluid schedule and a practical schedule.
remaining execution time
fluid schedule path
T-N plane
deadline
c1
T1
p1
c2
T2
p2
cN
TN
nodal remaining
execution time
pN
k-1 th
Fig. 2.
time
k th
k+1 th T-N plane
T-N Plane Abstraction.
the fluid scheduling model to realize optimal schedule on
practical systems since one processor must execute multiple
tasks simultaneously. Notice that tasks need not constantly
track their fluid schedule paths. Namely deadlines are the only
time at which tasks must track the fluid schedule paths.
Figure 2 shows the way T-N Plane Abstraction abstracts
real-time scheduling. All deadlines divide time as the vertical
dotted lines as shown in the figure. The right isosceles triangles
called T-N planes (Time and Nodal remaining execution time
domain planes) are placed between every two consecutive
deadlines. The rightmost vertex of the T-N plane coincides
with the intersection of the fluid schedule path and the right
side of the divided time-span. Since T-N planes in the same
time-span are congruent, we have only to keep in mind an
overlapped T-N plane shown in the lower of the figure at a
time. The overlapped T-N plane represents time on horizontal
axis and task’s nodal remaining execution time on vertical
axis. If the nodal remaining execution time becomes zero at
the rightmost vertex of each T-N plane, the task execution
follows the fluid schedule path at every deadline. Since T-N
nodal remaining execution time
ǩk t f
nodal remaining execution time
token
tf
T1
Ti
no nodal laxity diagonal (NNLD)
0
T2
Event C
T3
T4
0
t0
Fig. 4.
fluid schedule path
t
Event B
t1
tf
time
t2
P1
T1
T1
T1
P2
T2
T3
T4
time
Fig. 3.
Example of LNREF.
planes are repeated over time, good scheduling algorithms for
a single T-N plane can help all tasks to meet their deadlines.
Figure 3 shows an overlapped T-N plane, where tokens
representing tasks move from time t0 to tf . All tokens are on
their fluid schedule paths at the beginning of the T-N plane. A
token moves diagonally down if the task is executed; otherwise
it moves horizontally. If all tokens arrive at the rightmost
vertex, all tasks meet their deadlines. The successful arrival to
the rightmost vertex is called nodally feasible. For the nodal
feasibility, new events at which the scheduling decision is
made again in the T-N plane are laid on. Event C and Event
B occur when tokens hit the oblique side (NNLD) and the
bottom side of the T-N plane, respectively. We assume that the
jth event occurs at time tj . M tokens which have the Largest
Nodal Remaining Execution time are selected First (LNREF)
on M processors at every event. LNREF is an optimal realtime scheduling algorithm for multiprocessors in the sense that
any periodic taskset with utilization U ≤ M will be scheduled
to meet all deadlines. If U > M , no algorithm can realize the
successful schedule. Therefore we assume that U ≤ M .
For example, there are four tasks (T1 , T2 , T3 , T4 ) and two
processors (P1 , P2 ) as shown in Figure 3. Since there are two
processors, two tasks can be executed simultaneously. At time
t0 , T1 and T2 are executed on P1 and P2 in the LNREF order.
Event B occurs at time t1 since T2 hits the bottom side of the
T-N plane. Then two tasks T1 and T3 are selected again. Event
C occurs at time t2 since T4 hits the oblique side (NNLD) of
the T-N plane. The rescheduling is ingeminated at every event.
V. S TATIC VOLTAGE AND F REQUENCY S CALING
RT-SVFS proposed in our previous work [16] is based on
the technique called T-N Plane Transformation. Figure 4 shows
tf
tj
time
T-N Plane Transformation (αk = 0.5).
Algorithm: DecideUniformFrequency
1: foreach 1...M as k
2:
αk = max{Umax , U/M }
3: end foreach
Fig. 5.
Uniform RT-SVFS.
a transformed T-N plane with frequency αk = 0.5. Selected
tokens move diagonally down along the NNLD of the T-N
plane. If αk is given to the processor Pk , the voltage Vk
is uniquely defined since maximum processor frequency f
depends on supply voltage V . Thus the voltage and frequency
scaling is equivalent to the frequency decision problem.
RT-SVFS techniques for different types of systems are
presented in the following sections. SMT processors share resources among threads; thus the voltage and frequency can be
controlled only uniformly among threads. On the other hand,
the voltage and frequency can be controlled independently
among processors in most of CMP and Symmetric Multiprocessing (SMP) processors. We first show a uniform RT-SVFS
technique targeting for SMT processors. Then an independent
RT-SVFS technique targeting for CMP and SMP processors is
constructed upon the uniform RT-SVFS technique.
A. Uniform RT-SVFS
We assume that all processors have the same frequency
α(= α1 = . . . = αM ). Figure 5 shows the uniform RT-SVFS
algorithm. The algorithm is theoretically optimal as a static
approach in the case where the voltage and frequency can be
controlled only uniformly among threads or processors [16].
DecideUniformFrequency differs from the independent RTSVFS technique described in the next section in the sense that
DecideUniformFrequency is also optimal on practical systems,
which can not control processor frequency continuously.
B. Independent RT-SVFS
The strategy of independent RT-SVFS is analogous to
EKG [6]. All tasks are classified into either heavy or light.
Each heavy task Ti is exclusively executed on one processor
Pk with frequency αk = ui . All light tasks are executed on the
other processors by LNREF with DecideUniformFrequency.
Definitions for heavy and light are presented. Theavy and
light
T
denote the sets of heavy and light tasks,respectively.
Light taskset utilization is defined as U light = T ∈Tlight ui .
i
light
= max{ui |Ti ∈ Tlight } denotes maximum utilization
Umax
Independent RT-SVFS.
of Tlight . The number of heavy tasks is represented as H.
Heavy tasks are executed on the processors (P1 , . . . , PH ). The
number of processors for the light taskset is M − H.
The independent RT-SVFS algorithm is shown in Figure
6. Tasks are sorted in decreasing utilization order at first,
and we assume that all tasks are light. Then a light task
light
Ti with utilization ui = Umax
is classified into heavy to
light
>
dislodge the bottleneck of uniform RT-SVFS while Umax
light
U / (M − H) holds. The algorithm is theoretically optimal [16] in the sense that energy consumption is minimized.
Furthermore the algorithm can solve the problem in polynomial time as opposed to the exhaustive algorithm [16].
VI. DYNAMIC VOLTAGE AND F REQUENCY S CALING
RT-DVFS accommodates to the fluctuation of tasks’ execution time. Since LNREF is based on the worst-case analysis,
the voltage and frequency assigned by RT-SVFS is unnecessarily high in many cases. Each task Ti almost always
completes the execution earlier than ci is completely consumed
because ci represents “worst-case” execution time. Assume
that a task Ti completes the execution at time tj earlier than
ci is completely consumed as shown in Figure 7. Schedulers
can detect the early completion, and Event B occurs at time
tj . In this case, the time li,j , which represents the theoretical
value, can be reused for voltage and frequency scaling.
RT-SVFS presented in the previous section resolves the
problem based on the task utilization, while RT-DVFS controls the voltage and frequency based on nodal utilization
introduced by Cho et al [7]. li,j denotes the nodal remaining
execution time of a task Ti at time tj . The nodal utilization
of Ti at time tj is defined as ri,j = li,j /(tf − tj ). Sj =
Ti ∈T ri,j denotes total nodal utilization at time tj . Smax j =
max{ri,j |Ti ∈ T} denotes maximum nodal utilization of T at
time tj . The nodal utilization of light taskset at time tj is
light
defined as Sjlight =
r . Smax
j = max{ri,j |Ti ∈
Ti ∈Tlight i,j
light
T } denotes maximum nodal utilization of Tlight at time
theoretical schedule path
Ti
l i,j
0
actual schedule path
t j-1
tj
B
Fig. 6.
worst-case remaining execution time
B
Algorithm: DecideIndependentFrequency
Require: u1 ≥ u2 ≥ . . . ≥ uN
1: Theavy = φ
2: Tlight = T
3: foreach 1...M as i
light
4:
if Umax > U light / (M − H) then
heavy
= Theavy ∪ {Ti }
5:
T
light
= Tlight \{Ti }
6:
T
7:
else
8:
break
9:
end if
10: end foreach
11: foreach 1...M as k
12:
if Pk executes a heavy task Tk then
13:
αk = uk
14:
else
15:
αk = U light /(M − H)
16:
end if
17: end foreach
tj
time
Event B
Fig. 7.
Actual and theoretical schedules.
Algorithm: DecideUniformFrequencyDynamic
1: foreach 1...M as k
2:
αk = max{Smax j , Sj /M }
3: end foreach
Fig. 8.
Uniform RT-DVFS.
tj . The utilization of RT-SVFS can be changed to the nodal
utilization to realize RT-DVFS as shown in Figures 8 and 9.
The RT-DVFS techniques are performed at time t0 and arbitrary time. The nodal remaining execution time of completing
tasks is zero since the tasks do not need to be executed until
next releases. Thus the nodal utilization of completing tasks is
zero. RT-DVFS achieves lower energy consumption than RTSVFS does since RT-DVFS takes account of the zero nodal
utilization. If the voltage and frequency scaling is performed
at time tj shown in Figure 7, rescheduling by LNREF at time
tj is required since the T-N Plane is transformed at time tj .
A. Feasibility
The feasibilities of the RT-DVFS techniques are presented.
The feasibility of the independent RT-SVFS technique is
provided by the uniform independent RT-SVFS technique [16];
thus the independent RT-DVFS technique provides the feasibility if the uniform RT-DVFS technique provides the feasibility.
In other words, we have only to keep in mind whether the
uniform RT-DVFS technique can provide the feasibility.
Critical moment [7] is the first time when more than M
tokens simultaneously hit the NNLD as shown in Figure 10.
Cho et al. [7] show that critical moment is the sufficient and
necessary condition where tokens are not nodally feasible in
T-N Plane Abstraction. It is also available in the transformed
T-N plane in the same manner since αk ≤ Smax 0 holds for
all k in the uniform RT-DVFS technique (i.e., all tokens are in
the transformed T-N plane at time t0 [16]). Theorem 1 shows
that the condition where a critical moment occurs is derived
from total nodal utilization.
Theorem 1 (Total Nodal Utilization at Critical Moment):
If a critical moment occurs at time tj , Sj > αM .
nodal remaining execution time
ǩt f
Fig. 9.
t j-1
Fig. 11.
Independent RT-DVFS.
T1̖TM
TM+1
t0
Critical
Moment
Fig. 10.
tj
tf
time
RT-DVFS performed at time tj where S ≤ αM . Assume that N (≤ M ) tokens can be
selected at time tj−1 . Since all tasks are in the T-N plane
at first, ri,j−1 ≤ 1 for all i; thus Sj−1 = S ≤ αN is derived
from S ≤ M and ri,j−1 ≤ 1 for all i. The total remaining
execution time decreases by αN (tj −tj−1 ) between time tj−1
and tj . Sj is calculated as follows:
1
Sj =
li,j
tf − tj
Ti ∈T



1 
=
li,j−1  − αN (tj − tj−1 )
tf − tj
nodal remaining execution time
ǩk t f
0
tj
B
Algorithm: DecideIndependentFrequencyDynamic
Require: r1,j ≥ r2,j ≥ . . . ≥ rN,j 1: Theavy = φ
2: Tlight = T
3: foreach 1...M as i
light
light
4:
if Smax j > Sj / (M − H) then
heavy
heavy
5:
T
=T
∪ {Ti }
6:
Tlight = Tlight \{Ti }
7:
else
8:
break
9:
end if
10: end foreach
11: foreach 1...M as k
12:
if Pk executes a heavy task Tk then
13:
αk = rk,j
14:
else
light
15:
αk = Sj /(M − H)
16:
end if
17: end foreach
Ti ∈T
tf
⇐ since Equation (1)
S(tf − tj−1 ) − αN (tj − tj−1 )
.
=
tf − tj
time
Critical moment.
We have
Proof: This proof is the similar fashion as that of
LNREF [7] since frequency scaling is the lengthways time
scaling of T-N planes. The remaining time li,j of the tasks on
the NNLD at the critical moment is α(tf − tj ). Thus
Sj =
M+1
i=1
N
α(tf − tj )
li,j
+
> αM,
tf − tj
tf − tj
i=M+2
where (T1 , . . . , TM+1 ) are on the NNLD at time tj .
The contraposition of Theorem 1 implies that no critical
moment occurs if Sj ≤ αM holds for all j. If S0 ≤ αM
holds, no critical moment occurs since total nodal utilization is
monotonically decreasing as shown in the following theorem.
Theorem 2 (Total Nodal Utilization): If S0 ≤ αM , no critical moment occurs throughout the current T-N plane.
Proof: This proof is shown by the inductive method. The
induction hypothesis is:
Sj−1 = S
li,j−1
=S
⇔
tf − tj−1
Ti ∈T
li,j−1 = S(tf − tj−1 ),
⇔
Ti ∈T
(1)
Sj−1 − Sj
S(tf − tj−1 ) − αN (tj − tj−1 )
=S −
tf − tj
tj − tj−1
=
(αN − S) ≥ 0
tf − tj
⇒Sj−1 ≥ Sj .
If S0 ≤ αM , no critical moment occurs from Theorem 1 since
total nodal utilization is monotonically decreasing.
We assume that the voltage and frequency scaling is performed at time tj as shown in Figure 11. Note that tj does
not represent the exact time. Consequently the voltage and
frequency scaling can be performed at any time. All tokens
remain nodally feasible as shown in the following theorem.
Theorem 3 (Feasibility in RT-DVFS): All
tokens
are
nodally feasible even if the voltage and frequency scaling is
performed at any time.
Proof: Sj ≤ αM holds before the voltage and frequency
scaling since Sj−1 ≤ αM from Theorem 2 and no token
hits the NNLD between time tj−1 and tj . When the voltage
and frequency scaling is performed at time tj , the shaded
triangle shown in Figure 11 is transformed by the RT-DVFS
algorithms. Assume that the frequency changes from α to α .
TABLE I
S YSTEMS FOR SIMULATION .
Static
100%
80%
60%
40%
System 1
α
V
0.5
3
0.75
4
1.0
5
System 2
α
V
0.5
3
0.75
4
0.83 4.5
1.0
5
System 3
α
V
0.36
1.4
0.55
1.5
0.64
1.6
0.73
1.7
0.82
1.8
0.91
1.9
1.0
2.0
If Sj ≤ α M for all j > j , all tokens are nodally feasible
from Theorem 1. Since Sj is monotonically decreasing from
Theorem 2, Sj ≤ α M holds for all j > j . Therefore all
tokens remain nodally feasible from Theorem 1.
Theorem 3 shows that the voltage and frequency scaling
can be performed at any time. Frequent voltage and frequency
scaling can reduce much energy consumption; however it
incurs significant run-time overhead. Therefore the frequency
of the voltage and frequency scaling is the trade-off between
energy efficiency and system performance.
B. Practical Implementation
The previous section shows that the RT-DVFS techniques
can be performed at any time. Assume that the RT-DVFS techniques are performed at every ∆ interval. If ∆ → 0, energy
consumption based on the RT-DVFS techniques is minimized
theoretically; however it is unrealistic from the viewpoint of
system overhead. The balance between practicality and energy
efficiency is important. The events (i.e., time t0 , Event C, and
Event B) are good timings of voltage and frequency scaling
since (1) additional rescheduling at voltage and frequency
scaling is not required, and (2) the task sort of the independent
RT-SVFS can be omitted since LNREF sorts tasks in decreasing nodal remaining execution time. The implementation can
accommodate to the early completion shown in Figure 7 since
Event B occurs at the early completion.
VII. S IMULATION
The advancement of RT-DVFS proposed in this paper is
evaluated by comparing with RT-SVFS in terms of energy
consumption in three systems shown in Table I. Each system
has the operable sets of normalized frequency α and voltage
V for each processor as shown in the table. The voltage and
frequency scaling is performed only at every event to restrain
the overhead of the voltage and frequency scaling. The simulation interval L is [0, min{lcm{pi |Ti ∈ T}, 232 }]. Energy
represents the normalized energy consumption as follows:
1 L Pk ∈P αk Vk2
EnergyRatio =
dt,
2
L 0
M Vmax
where Vmax represents the maximum voltage of each system.
Five cases are compared. Static represents the case where
the voltage and frequency is controlled by RT-SVFS shown
in Figure 6. The other four cases are that the voltage and
frequency is controlled by RT-DVFS shown in Figure 9.
EnergyRatio
1
0.8
0.6
0.4
0.2
0.4
0.5
0.6
0.7
0.8
0.9
1
1.1
System utilization
Fig. 12.
Energy of System 1.
In RT-DVFS, the four cases where actual execution time
uniformly varies in the range of [0.4ci , ci ] (40%), ([0.6ci , ci ])
(60%), [0.8ci , ci ] (80%), and always ci (100%) of worst-case
execution time for each task Ti are presented in the results.
The other RT-DVFS algorithms shown in the previous
papers can not be compared since the previous algorithms
based on non-optimal real-time scheduling algorithms can not
guarantee the schedulability in high system utilization.
A. Simulation Setup
Each simulation is modeled as four processors and a taskset.
A taskset is initially empty. A new task is appended to the
taskset as long as U ≤ Utarget , where Utarget is the target
utilization for each simulation. For each task Ti , its utilization
ui is computed based on a uniform distribution in the range
of [0.01, 0.1]. Only the utilization of the last task is adjusted
so that U becomes Utarget . Each task Ti is generated with the
period pi in the integer range of [100, 3000] and the worst-case
execution time ci = ui pi . In order to measure the average
energy consumption, hundred simulations are conducted for
each system utilization U/M between 0.5 and 1.0 where most
traditional algorithms can not guarantee the schedulability.
B. Simulation Results
Figures 12, 13, and 14 show the results corresponding to that
of Systems 1, 2, and 3, respectively. The figures show system
utilization U/M on the horizontal axis and the average Energy
on the vertical axis. The results of the three systems show
that the results of RT-SVFS highly depend on the selectable
voltage and frequency level in the higher system utilization.
The reason comes from the fact that RT-SVFS must take
account of the worst case execution time and can not change
the voltage and frequency for ever. On the other hand, RTDVFS can accommodate to dynamic environments even if
actual execution time is always equal to worst-case execution
time (100%). The reason comes from the fact that the voltage
and frequency levels selected by RT-DVFS are unnecessarily
high only at first; namely most of tasks complete the execution
earlier than the ideal case since the set of higher voltage
1
EnergyRatio
The practical implementation is a topic for the future work.
The frequency of the voltage and frequency scaling is a
trade-off between energy efficiency and system performance.
Frequent voltage and frequency scaling incurs significant runtime overhead due to the physical limitation of processors.
Therefore effective implementation and appropriate control of
the voltage and frequency are required in practical systems.
Static
100%
80%
60%
40%
0.8
0.6
ACKNOWLEDGEMENT
0.4
This research is supported by CREST, JST.
R EFERENCES
0.2
0.4
0.5
0.6
0.7
0.8
0.9
1
1.1
1
1.1
System utilization
Fig. 13.
Static
100%
80%
60%
40%
1
EnergyRatio
Energy of System 2.
0.8
0.6
0.4
0.2
0.4
0.5
0.6
0.7
0.8
0.9
System utilization
Fig. 14.
Energy of System 3.
and frequency is selected to bridge the gap between theory
and practicality as shown in the system model. After that,
RT-DVFS can decrease the voltage and frequency. Therefore
the curves of RT-DVFS smoothly decrease as compared to
that of RT-SVFS. RT-DVFS can linearly reduce the energy
consumption when actual execution time varies uniformly. In
the lower system utilization, all results are mostly the same
since the selectable voltage and frequency is bounded by the
sets of lowest voltage and frequency shown in Table I.
VIII. C ONCLUSIONS AND F UTURE W ORK
In this paper, we have presented two algorithms for real-time
dynamic voltage and frequency scaling based on an optimal
real-time scheduling algorithm for multiprocessors. The RTDVFS algorithms proposed in this paper is based on the
optimal RT-SVFS techniques proposed in our previous work.
The algorithms can be applied to both uniform settings and
independent settings of the voltage and frequency among processors. RT-DVFS can accommodate to dynamic environments
even if actual execution time is always equal to worst-case
execution time. Additionally RT-DVFS can linearly reduce the
energy consumption when actual execution time varies.
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