BUFFER 1
Synthesis Design Team
Henry Leung, Jizhou Li
Run Synopsis Design Compiler
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# HDL file names (.v or .vhd)
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set my_HDL_files [list fofo.vhd txt_util.vhd]
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# Top-level Module / Entity name
set my_toplevel fifo_read
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# The name of the clock pin
# If no clock-pin exists, pick anything
set my_clock_pin clk
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# Target frequency in MHz for optimization
set my_clk_freq_MHz 100
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# Delay of input signals (Clock-to-Q, Package etc.)#
set my_input_delay_ns 0.1
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# Reserved time for output signals (Holdtime etc.) #
set my_output_delay_ns 0.1
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####################################################
# No modification below
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####################################################
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Initial Timing Report
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# generated on Fri Jan 21 15:26:21 2011
# Top Cell: fifo_read
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-----------------------------------------------------------timeDesign Summary
------------------------------------------------------------
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+--------------------+---------+---------+---------+---------+---------+---------+
| Setup mode | all | reg2reg | in2reg | reg2out | in2out | clkgate |
+--------------------+---------+---------+---------+---------+---------+---------+
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WNS (ns):| 8.351 | 8.351 | 8.514 | 9.598 | N/A | N/A |
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TNS (ns):| 0.000 | 0.000 | 0.000 | 0.000 | N/A | N/A |
| Violating Paths:| 0 | 0 | 0 | 0 | N/A | N/A |
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All Paths:| 210 | 168 | 176 | 34 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
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+----------------+-------------------------------+------------------+
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Real
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Total
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| DRVs
+------------------+------------+------------------|
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| Nr nets(terms) | Worst Vio | Nr nets(terms) |
+----------------+------------------+------------+------------------+
| max_cap
| 247 (247) | -0.035 | 247 (247) |
| max_tran |
0 (0)
| 0.000 |
0 (0)
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| max_fanout |
0 (0)
| 0
|
0 (0)
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+----------------+------------------+------------+------------------+
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Density: 51.375%
Routing Overflow: 0.00% H and 1.53% V
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Post CTS Timing Report
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# generated on Fri Jan 21 15:30:55 2011
# Top Cell: fifo_read
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-----------------------------------------------------------timeDesign Summary
------------------------------------------------------------
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+--------------------+---------+---------+---------+---------+---------+---------+
| Setup mode | all | reg2reg | in2reg | reg2out | in2out | clkgate |
+--------------------+---------+---------+---------+---------+---------+---------+
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WNS (ns):| 8.186 | 8.186 | 8.623 | 9.355 | N/A | N/A |
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TNS (ns):| 0.000 | 0.000 | 0.000 | 0.000 | N/A | N/A |
| Violating Paths:| 0 | 0 | 0 | 0 | N/A | N/A |
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All Paths:| 210 | 168 | 176 | 34 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
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+----------------+-------------------------------+------------------+
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Real
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Total
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| DRVs
+------------------+------------+------------------|
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| Nr nets(terms) | Worst Vio | Nr nets(terms) |
+----------------+------------------+------------+------------------+
| max_cap
| 247 (247) | -0.036 | 247 (247) |
| max_tran |
0 (0)
| 0.000 |
0 (0)
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| max_fanout |
0 (0)
| 0
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0 (0)
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+----------------+------------------+------------+------------------+
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Density: 51.698%
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Post-Route Timing Report
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# generated on Fri Jan 21 15:35:04 2011
# Top Cell: fifo_read
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-----------------------------------------------------------timeDesign Summary
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+--------------------+---------+---------+---------+---------+---------+---------+
| Setup mode | all | reg2reg | in2reg | reg2out | in2out | clkgate |
+--------------------+---------+---------+---------+---------+---------+---------+
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WNS (ns):| 7.933 | 7.933 | 8.388 | 9.331 | N/A | N/A |
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TNS (ns):| 0.000 | 0.000 | 0.000 | 0.000 | N/A | N/A |
| Violating Paths:| 0 | 0 | 0 | 0 | N/A | N/A |
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All Paths:| 210 | 168 | 176 | 34 | N/A | N/A |
+--------------------+---------+---------+---------+---------+---------+---------+
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+----------------+-------------------------------+------------------+
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Real
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Total
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| DRVs
+------------------+------------+------------------|
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| Nr nets(terms) | Worst Vio | Nr nets(terms) |
+----------------+------------------+------------+------------------+
| max_cap
| 250 (250) | -0.066 | 250 (250) |
| max_tran |
0 (0)
| 0.000 |
0 (0)
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| max_fanout |
0 (0)
| 0
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0 (0)
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+----------------+------------------+------------+------------------+
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Density: 94.129%
------------------------------------------------------------
Connectivity Verify
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******** Start: VERIFY CONNECTIVITY ********
Start Time: Fri Jan 21 15:38:20 2011
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Design Name: fifo_read
Database Units: 2000
Design Boundary: (0.0000, 0.0000) (108.4150, 104.3600)
Error Limit = 1000; Warning Limit = 50
Check all nets
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VC Elapsed Time: 0:00:00.0
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Begin Summary
Found no problems or warnings.
End Summary
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End Time: Fri Jan 21 15:38:20 2011
******** End: VERIFY CONNECTIVITY ********
Verification Complete : 0 Viols. 0 Wrngs.
(CPU Time: 0:00:00.1 MEM: 0.031M)
Geometry Verify
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encounter 1> *** Starting Verify Geometry (MEM: 325.2) ***
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VERIFY GEOMETRY ...... Starting Verification
VERIFY GEOMETRY ...... Initializing
VERIFY GEOMETRY ...... Deleting Existing Violations
VERIFY GEOMETRY ...... Creating Sub-Areas
...... bin size: 2080
VERIFY GEOMETRY ...... SubArea : 1 of 1
VERIFY GEOMETRY ...... Cells
: 0 Viols.
VERIFY GEOMETRY ...... SameNet
: 0 Viols.
VERIFY GEOMETRY ...... Wiring
: 0 Viols.
VERIFY GEOMETRY ...... Antenna
: 0 Viols.
VERIFY GEOMETRY ...... Sub-Area : 1 complete 0 Viols. 0 Wrngs.
VG: elapsed time: 0.00
Begin Summary ...
Cells
:0
SameNet : 0
Wiring
:0
Antenna : 0
Short
:0
Overlap : 0
End Summary
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Verification Complete : 0 Viols. 0 Wrngs.
**********End: VERIFY GEOMETRY**********
*** verify geometry (CPU: 0:00:00.4 MEM: 13.5M)
Layout
ModelSim
• Simulation with original VHDL file
• Simulation with synthesized VHDL file