Combinationality of
cyclic circuits
EECS 290A – Spring 2005
UC Berkeley
01/25/2005
Outline
 Sequential circuits
 Synchronous vs. asynchronous
 Combinational circuits
 Definition
 Acyclic vs. cyclic circuits
 Cyclic circuits
 Origins and applications
 When cyclic circuits behave combinationally
 Up-bounded inertial delay model and ternary
simulation
 Analysis and synthesis of cyclic circuits
Sequential circuits
 Synchronous vs. asynchronous implementations
of finite state machines

With/without reference clock
 Hybrid implementations (e.g. GALS, quasi delay-
insensitive designs, de-synchronization, etc.)

Strong/weak timing assumptions
input
output
Combinational
Logic
input
output
Combinational
Logic
Sequential circuits
 Sources of sequentiality (output valuation depends
on input history)


Feedback (cyclicity), or
Delay
f (x[t], x[t-1], x[t-2])
x
D
D
z
Combinational circuits

Conceptual definition of combinational circuits
 For any input assignment, the output valuates to
the same fixed value after a bounded amount of
time
 Operational definition of combinational circuits
 Depending on timing and circuit (e.g. static
CMOS, floating mode, etc.) model
 Here we use the up-bounded inertial (UIN) delay
model [Brozowski & Seger 95]


Ideal delay – glitches are persistent
Inertial delay – small glitches are smoothed out
Up-bounded inertial delay model
 Up-bounded inertial delay model satisfies
(0 < d(t) < D)
1.
2.
If z(t) changes from v to v’ at time t1, then there exists
d > 0 such that x(t) = v’ for t1 – d ≤ t < t1.
If x(t) = v for t1 ≤ t < t1 + D, then there exists a time t2,
t1 ≤ t2 < t1 + D such that z(t) = v for t2 ≤ t < t1 + D.
d(t)
x(t)
x(t)
z(t)
x(t)
d
t1
z(t)
t1+D
z(t)
t1
t2
Combinationality and cyclicity
 Acyclic circuits are asymptotically combinational
 Circuits with delay elements without feedback are
combinational in the asymptotic sense
 Cyclic circuits are not necessarily sequential or
physically undesirable (e.g. oscillation, nondeterminism, etc.)

However, must be very careful in designing cyclic
circuits
f (x[t], x[t-1], x[t-2])
x
D
D
z
So cyclic combinational circuits?
 Why ?


Possible area reduction for hardware
(code-size reduction for software)
Other advantages?
 Why not ?

Sophisticated functional and timing analysis
 Still controversial
Early history about combinational
cyclic circuits
 It is argued that, under some circumstances, cyclicity
is a necessity to generate minimal combinational
circuits [Kautz 70]

This example is not good for all possible delay
assignments [Shiple 96]
1
x1
1
0
x2
0
x3
0
z1 = x1' (x3' + x2)
z2 = x2' (x1' + x3)
z3 = x3' (x2' + x1)
Early history about combinational
cyclic circuits
 A more convincing family of examples [Rivest 77]
 The smallest acyclic implementation of the 2n output
functions requires (3n – 2) two-fanin gates.
x1
x2
x3
x1
x2
x3
f1=x1(x2+x3)
f3=x3(x1+x2)
f5=x2(x1+x3)
f2=x2+x1x3
f4=x1+x2x3
f6=x3+x1x2
Recent interests in the EDA
community
 Cyclic definitions occur
commonly in high-level
system designs [Stok 92]
 Not all cyclic
dependencies are
sequential or physically
undesirable, e.g.,
x
c
x
1
0
c
G
0
F
z = if(c) then F(G(x))
else G(F(x))
 More recently, make acyclic
functions cyclic (to reduce
area) [Riedel & Bruck 03]
1
c
0
1
z
Recent interests in the synchronouslanguage community
 Synchronous languages are popularly used in
the design of real-time control systems


Signals synchronized by global clock ticks
Internal evaluations take zero time


Instantaneous valuations of signals
Esterel language allows simultaneous cyclic
definitions of functional valuations

Adopt the analysis of combinational cyclic circuits
Questions to be answered
 How to analyze if a cyclic circuit is “good” ?
 How to make cyclic circuits acyclic ?
 How to make acyclic circuits cyclic ?
Cyclic-circuit example 1
 Combinational
(Assume gates and wires can have arbitrary delays)
x
z
Cyclic-circuit example 2
 Combinational but with internal oscillation
(Assume gates and wires can have arbitrary delays)
x
z
Cyclic-circuit example 3
 Not combinational even though functional analysis
says so
y, Y
1
1
a0
0
b0
z
0
0
x
z(t)
0
1
2
3
When cyclic circuits behave
combinationally
 Malik’s procedure [Malik 94]



Select a cutset
Perform ternary simulation
Circuit is combinational iff, for any input
assignment, each output valuates to either 0
or 1 after the simulation reaches a fixed point.
Ternary simulation
 Let “” denote the
unknown value
(the least element in the
lattice with information
partial order)

Monotonicity is
important for a fixedpoint computation to
guarantee termination
 Some examples
F: {0,1,} → {0,1,}
0
1

NOT
AND
OR
XOR
0
1
0
0
0
0
0
1

0

0
0
1
1
1

1

0
0
0
1

1
1
1

1

1
0
1


1

0
 1
 
0
1

0





Ternary simulation – example 1
 Select a cutset, at (y,Y) say
 Let y have unknown value 
 Valuate all signals w.r.t. some input assignment
y, Y
a
z
b
x
Ternary simulation – example 2
 Not combinational
x1
x2
x3
z1 = x1' (x3' + x2)
z2 = x2' (x1' + x3)
z3 = x3' (x2' + x1)
Ternary simulation – example 3
 Combinational
x1
x2
x3
x1
x2
x3
f1=x1(x2+x3)
f3=x3(x1+x2)
f5=x2(x1+x3)
f2=x2+x1x3
f4=x1+x2x3
f6=x3+x1x2
Symbolic analysis
 For each signal s in the circuit, introduce two characteristic functions
fs0(x) and fs1(x) such that



fs0(x) = 1 iff input assignment x makes s valuates to 0
fs1(x) = 1 iff input assignment x makes s valuates to 1
Thus fs (x) = ¬(fs0(x)  fs1(x) )
 Ternary simulation are performed with symbolic computation


Initially, PI variable xi has fxi0 = ¬xi and fxi1 = xi , and all other signals s
has fs0 = 0 and fs1 = 0
In every iteration, simulate the acyclic circuit (due a cutset) in
topological order from PI to PO with symbolic computation for each
gate




E.g., for w := AND(u,v), we have fw0 = fu0  fv0 and fw1 = fu1  fv1
From iteration t-1 to iteration t, update cutset fy0[t](x) := fY0[t -1](x) and
fy0[t](x) := fY0[t -1](x)
Simulation terminates when all cutset variable y has fy0[t](x) = fy0[t -1](x)
and fy1[t](x) = fy1[t -1](x)
Upon termination, the circuit is combinational iff every PO variable zi
has fzi = 0
Exactness of combinationality analysis
 Combinationality analysis using ternary simulation is
exact under the UIN delay model [Shiple 96]


However, UIN delay model might seem somewhat
conservative (large glitches may be persistent)
The analysis is also exact under up-bounded ideal
delay model (?)
x
c
z
Complexity of combinationality
analysis
 For any input assignment, ternary simulation
converges in at most k iterations, where k is
the cutset size
 Determining if a cyclic circuit is combinational
is co-NP complete

Find some input vector that makes the output
behave non-deterministically
Making cyclic circuits acyclic
 Why?
 Most CAD algorithms do not support cyclic circuits (not
separated by registers)
 To avoid complicated analysis and optimization
 How?
 In symbolic analysis, we get fz 0 and fz 1 for every
i
i
primary output zi. By that, we know the function for zi,
and can derive an acyclic implementation.
 [Malik 94], [Halbwachs & Maraninchi 95], [Edwards 03]
Other applications of combinationality
analysis
 Constructive semantics in Esterel language

Translate a program (with cyclic definitions)
into a circuit netlist and then perform
combinationality analysis
Synthesis of cyclic circuits
 Perform Boolean resubstitution as much as
possible [Riedel & Bruck 03]


Not restricted to the topological constraint of
acyclicity
Generalized Boolean resubstitution
Boolean resubstitution
 Given a Boolean function f, try to express f
with another function g.


E.g. f := abc + acd’ + abd
g := a (b + d’)
Rewriting f in terms of g yields
f := (c + d) g
Note that resubstitution is performed at the
functional level
Synthesis of cyclic circuits
 Requirement
 Phrase the ternary simulation at the functional level:
For every input assignment, there must be some signal
valuating to either 0 or 1 such that all cyclic
dependencies are broken
x1
x2
x3
x1
x2
x3
f1=x1(x2+x3)
f3=x3(x1+x2)
f5=x2(x1+x3)
f2=x2+x1x3
f4=x1+x2x3
f6=x3+x1x2
Synthesis of cyclic circuits
 The marginal operator [Riedel & Bruck 03]
 f (x1,…,xn)  x1,…,xn. (f  x1)    (f  xn)
(f  xi)  fx =0 xnor fx =1
i
i
 Condition C for a “network” N to be combinational
 C(N) = (f1  I1)C(Nf )    (fk  Ik)C(Nf ), where Ii
1
k
is the set of internal variables that fi depends upon
 (fi  Ii) denotes the condition where the valuation of fi
is independent of the variables in Ii
 Nf denotes the subnetwork with every occurrence of fi
i
substituted with its corresponding global function (or
target function in [Riedel & Bruck 03]) in terms of PI
variables
Cyclify acyclic functions – example 1
 Consider network N1
Global functions:
d = c’(a’+b’) + a’b’
e = a’bc’ + b’(a+c)
f = b’(a’+c’) + ab
de = a + b’c’
ef = c + ab’
fd = b
Cyclified functions:
d = b’c’ + a’e
e = b’(a+c) + c’f’ f
f = ab + b’d
C(N1d) = C(N1e) = C(N1f) = 1
C(N1) = a + b’c’ + c + ab’ + b = 1
d
e
Cyclify acyclic functions – example 2
 Consider network N2
Global functions:
d = c’(a’+b’) + a’b’
e = a’bc’ + b’(a+c)
f = b’(a’+c’) + ab
d(e,f) = bc
e(d,f) = b’c
f(d,e) = a’b
Cyclified functions:
d = b’f + c’e
e = d(a+f’) + b’c
f = ae’ + b’d
f
C(N2d) = 1
C(N2e) = 0
C(N2f) = b’ + c
d
e
C(N2) = bc (1) + b’c (0) + a’b (b’+c)
= bc
Cyclify acyclic functions
 General procedure [Riedel & Bruck 03]

Branch-and-bound algorithms


Start from a “dense” cyclic network. Iteratively
delete some dependency edges until the network
is combinational.
Start from a set of global functions. Iteratively
perform resubstitution until combinationality
cannot be maintained for any further
resubstitution.
What’s missing?
 Purely functional analysis cannot guarantee well-
behaved circuitry! [JMB 04]
Non-functional restrictions need to be imposed.
f := ¬a h  ¬b ¬h
g := ¬a ¬b f
h := a b  ¬g
a

h
b
g
a
b
a
h
x
y
f
g
x
y
b
(i)
( ii )
f
Some possible non-functional
restrictions
 Exclude axioms (x  ¬x) = true and (x  ¬x) =
false from the marginal operator
 Add additional minterms
f := ¬a h  ¬b ¬h  ¬a ¬b
g := ¬a ¬b f
h := a b  ¬g
 Other approaches ?
Timing analysis of cyclic circuits
 Topological longest paths may not be an
adequate upper bound
 Following the ternary simulation procedure to
determine longest paths
 False paths?
Summaries
 What we learned



How to tell if a cyclic circuit is combinational
How to make cyclic circuits acyclic
How to synthesize cyclic circuits from acyclic
functions
 What’s coming


Software synthesis rather than hardware
Combinationality at a higher abstraction level
References










[Kautz 70] W. Kautz. The necessity of closed loops in minimal combinational
circuits. IEEE Trans. On Computers, pp.162-164, Feb. 1970.
[Rivest 77] R. Rivest. The necessity of feedback in minimal monotone
combinational circuits. IEEE Trans. on Computers, pp.606-607, 1977.
[Stok 92] L. Stok. False loops through resource sharing. In Proc. ICCAD,
pp.345-348, 1992.
[Malik 94] S. Malik. Analysis of cyclic combinational circuits. IEEE Trans. on
CAD, pp.950-956, 1994.
[Brozowski & Seger 95] J. Brozowski & C.-J. Seger. Asynchronous circuits.
Springer-Verlag, 1995.
[Halbwachs & Maraninchi 95] N. Halbwachs & F. Maraninchi. On the symbolic
analysis of combinational loops in circuits and synchronous programs. In Proc.
Euromicro, 1995.
[Shiple 96] T. Shiple. Formal analysis of synchronous circuits. Ph.D. thesis, UCB,
1996.
[Edwards 03] S. Edwards. Making cyclic circuits acyclic. In Proc. DAC, 2003.
[Riedel & Bruck 03] M. Riedel & J. Bruck. The synthesis of cyclic combinational
circuits. In Proc. DAC, 2003. Cyclic combinational circuits: analysis for synthesis.
In Proc. IWLS, 2003.
[JMB 04] On breakable cyclic definitions. In Proc. ICCAD, 2004.