Chapter 8
MOS Memory and Storage Circuits
Microelectronic Circuit Design
Richard C. Jaeger
Travis N. Blalock
Jaeger/Blalock
10/17/03
Microelectronic Circuit Design
McGraw-Hill
Chap 8 - 1
Chapter Goals
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•
•
•
•
•
•
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Overall memory chip organization
Static memory circuits using the six-transistor cell
Dynamic memory circuits
Sense amplifier circuits used to read from memory
cells
Learn about row and address decoders
Implementation of CPU registers via flip-flops
Pass transistor logic
Read Only Memory
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Chap 8 - 2
Random Access Memory
• Random Access Memory (RAM) refers to memory in a
digital system that has both read and write capabilities
• Static RAM (SRAM) are able to store there information as
long as power is applied, and they will not lose their data
during a read cycle
• Dynamic RAM (DRAM) uses a capacitor to temporarily
store data which must be refreshed periodically to prevent
information loss, and the data is lost in most DRAMs
during the read cycle
• SRAM takes approximately four times more Silicon area
as DRAM
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Chap 8 - 3
A 256-MByte Memory Chip
Note that the basic building block for this
memory if a 128Kb cell
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• The figure shows the
block structure of a 256Mb memory
• There are sets of column
and row decoders that are
used for memory array
selection
• The column decoder splits
the memory into upper and
lower halves
• The row decoder and
wordline driver bisects
each 32-Mb subarray
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Chap 8 - 4
A 256-MByte Memory Chip
• The memory block
diagram contains 2M+N
storage locations
• When a bit has been
selected the set of sense
amplifiers are used to
read/write to the
memory location
• Horizontal rows are
referred to as wordlines
where the vertical lines
are called bitlines
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Chap 8 - 5
Static Memory Cells
• Inverters configured as shown in the above figure
form the basic static storage building block
• These cross-coupled inverters are often referred to
as a latch
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Chap 8 - 6
Static Memory Cells VTC
• The previous latch
has only two stable
states termed
bistable
• However, it is
possible for it to
enter an unstable
equilibrium point
where slight
changes in the
voltage could give
erroneous data
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Chap 8 - 7
The 6-T Cell
• With the addition of two control transistors it is
possible to create the 6-T cell which has both the
true and complemented values
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Chap 8 - 8
The Read Operation of a 6-T Cell
Initial state of the 6-T cell storing
a 0 with the bitlines’ initial
conditions assumed to VDD/2
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Conditions after the WL
transistors have been
turned on
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Chap 8 - 9
The Read Operation of a 6-T Cell
Final read state condition of
the 6-T cell
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Waveforms of the 6-T
cell read operation
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Chap 8 - 10
The Read Operation of a 6-T Cell
• Reading a 6-T cell that is storing a “1” follows the
same concept as before, except for the sources and
drains of the WL transistors are switches
• Note that the delay is approximately 20ns for this
particular cell
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Chap 8 - 11
The Write Operation of a 6-T Cell
It can be seen that not much happens while writing a “0”
to a cell that is already storing a “0”
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Chap 8 - 12
The Write Operation of a 6-T Cell
While writing a “0” to a cell that is storing a “1”, the
bitlines must be able to overpower the output drive of
the latch inverters to force it to store the new condition
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Chap 8 - 13
Dynamic Memory Cells
• The 1-T cell uses a capacitor for its storage element (either
a presence or absence of a charge)
• Due to leakage currents of MA, the data will eventually
become corrupt, hence it needs to be refreshed
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Chap 8 - 14
Data Storage in a 1-T Cell
Storing a 0
Storing a 1
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Chap 8 - 15
Data Storage in a 1-T Cell
• Notice that the voltage stored on the storage
capacitor on the previous slide does not reach VDD
• It instead is determined by the following:
VC  VG  VTN

VC  VG  VTO  
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V
C
 2F  2F
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
Chap 8 - 16
Data Storage in a 1-T Cell
• To read a DRAM cell, the bitline is precharged to
either VDD or VDD/2, and then MA is turned on
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Chap 8 - 17
Data Storage in a 1-T Cell
• The charge stored on CC will be shared with CBL
through the process of charge sharing, where the
read voltage varies slightly
CBLVBL  CCVC
VF 
 VBL
CBL  CC
• Where CBL>> CC and the charging time constant is:
  RON
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CBLCC
 RON CC
CBL  CC
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Chap 8 - 18
The Four-Transistor (4-T) Cell
• Since the 6-T SRAM provides a large signal current drive
to the sense amplifier, they generally have shorter access
times compared to the DRAM
• The 4-T DRAM cell is an alternative that increases access
time, and automatically refreshes itself
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Chap 8 - 19
Reading and Writing to the 4-T DRAM
Cell
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Chap 8 - 20
Sense Amplifiers
• Sense amplifiers are used to detect small currents
that flow through the access transistors or the
small voltage differences that occur during charge
sharing
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Chap 8 - 21
A Sense Amplifier for the 6-T Cell
• MPC is the precharge
transistor whose main
purpose is to force the
latch to operate at the
unstable point
previously mentioned
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Chap 8 - 22
Sense Amplifier Example
• For the figure on the previous slide, find the currents in the
latch transistors when MPC is turned on with the following
given: V  5V
DD
Jaeger/Blalock
10/17/03
2
W 
  
 L  All 1
NMOS :
PMOS :
K n'  25A / V 2
K n'  10 A / V 2
VTO  1V
VTO  1V
  0.5V 1/ 2
2F  0.6V
  0.75V 1/ 2
2F  0.6V
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Chap 8 - 23
Sense Amplifier Example
• Since the output voltage should equal on both sides of the
latch when MPC is on, it is known that VGS = VDS for the
latch NMOS devices and VSG = VSD for the latch PMOS
devices. Therefore these transistors are saturated
• Due to the symmetry of the situation, the drain currents are
equal giving the following:
K p'  W 
K n'  W 
2
2
 VSG  VTP  
 VGS  VTN 
2 L
2 L
1  10 A  2 
1  25A  2 
2
2




5

V

1

V

1
 2  




O
O
2  V  1 
2  V 2  1 
1.5VO2  3VO  13.5  0 
 VO  2.162V
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Chap 8 - 24
Sense Amplifier Example
• The drain currents are then found by (PMOS and
NMOS drain currents are equal):
1  25A  2 
2
iD   2  2.162  1  33.8A
2  V  1 
• And the power dissipation is found by:
P  2iDVDD  233.8A5V   0.338mW
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Chap 8 - 25
Sense Amplifier for the 1-T Cell
• The same sense
amplifier used in the
6-T cell can be used
for the 1-T cell in
manner shown in the
figure
Jaeger/Blalock
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Chap 8 - 26
Sense Amplifier for the 1-T Cell
• The sense amplifier works the same as it did for the 6T cell, but takes longer to reach steady state after
precharge
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Chap 8 - 27
The Boosted Wordline Circuit
• Obviously it is desired to have a fast access in
many DRAM application, so by driving the
wordline to a higher voltage (referred to as a
boosted wordline), 5V instead of 3V, it is possible
to increase the amount of current supplied to the
storage capacitors
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Chap 8 - 28
Clocked CMOS Sense Amplifiers
• The sense amplifier can definitely be a major source of
power dissipation, but be using a clocking scheme, it is
possible to reduce the power dissipated
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Chap 8 - 29
Clocked CMOS Sense Amplifiers
• Clocking the previous
circuit in the manner
shown in the figure will
eliminate static currents
in the latch during the
precharge state, and only
transient currents will
appear
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Chap 8 - 30
Address Decoders
• The following figures are examples of commonly used
decoders for row and column address decoding
NMOS NOR Decoder
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NMOS NAND Decoder
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Chap 8 - 31
Address Decoders
Complete 3-bit domino
CMOS NAND decoder
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Chap 8 - 32
Address Decoders
3-bit column data
selector using passtransistor logic
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Chap 8 - 33
Read-Only Memory (ROM)
• ROM is often needed in digital systems such as:
–
–
–
–
Holding the instruction set for a microprocessor
Firmware
Calculator plug-in modules
Cartridge style video games
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Chap 8 - 34
Read-Only Memory (ROM)
• The basic structure of
the NMOS static ROM
is shown in the figure
• The existence of a
NMOS means a “0” is
stored at that address
otherwise a “1” is
stored
• The major downfall to
this particular circuit is
that it dissipates a lot
of power
Jaeger/Blalock
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Chap 8 - 35
Read-Only Memory (ROM)
• The domino
CMOS ROM is
one technique
used to lower the
amount of power
dissipation
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Chap 8 - 36
Read-Only Memory (ROM)
• Another ROM
option is the
NAND array
ROM which
can be directly
used with a
NAND decoder
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Chap 8 - 37
Read-Only Memory (ROM)
• The main problem with these previous ROMs is that they
must be designed at the mask level, meaning that it was not
a versatile product.
• To solve this problem, the programmable ROM (PROM)
was introduced
• The standard PROM cannot be erased, so the erasable
ROM (EPROM), and later, electrically erasable ROM
(EEPROM) were introduced
• High density flash memories allow for selective electrical
erasure and reprogramming of memory cells
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Chap 8 - 38
RS Flip-Flop
• The reset-set (RS) flip-flop can be easily realized
by using either two cross-coupled NOR or NAND
gates
• The RSFF has the following truth tables
NOR RSFF
R S Q Q
NAND RSFF
R S Q Q
0
0
Q
Q
0
0
Q
Q
0
1
1
0
0
1
0
1
1
0
0
1
1
0
1
0
1
1
0
0
1
1
1
1
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Chap 8 - 39
RS Flip-Flop
NOR RSFF
NAND RSFF
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Chap 8 - 40
RS Flip-Flop
• Simplified RS flip-flop
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Chap 8 - 41
D-Latch using T-Gates
• A very important circuit of digital systems is the
D-Latch which is used for a D flip-flop
• Whenever C (clock) goes high in the below DLatch, whatever is on D is passed through to Q
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Chap 8 - 42
Master-Slave D Flip-Flop
• By using series DLatches that latch
the data on
opposite clock
phases, a D flipflop can be realized
as shown in the
figure
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Chap 8 - 43
End of Chapter 8
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Chap 8 - 44