Unit 11 Solutions
Unit 11 Problem Solutions
11.1
Z responds to X and to Y after 10 ns; Y responds to
Z after 5 ns. See FLD p. 713 for answer.
11.3
P and Q will oscillate. See FLD p. 713 for timing
chart.
11.4
11.5
11.2
See FLD p. 713 for solution. For part (b), also use
the following Karnaugh map. Don’t cares come
from the restriction in part (a).
H Q
See FLD p. 714 for solution.
See FLD p. 714 for solution.
R
0
1
00
0
X
01
0
X
11
1
1
10
0
1
Q+ = R + H Q
11.6 (a)
SRQ Q+
00 0 0
00 1 1
01 0 0
01 1 0
10 0 1
10 1 1
11 0 0
11 1 0
R Q
S
11.6 (b) See FLD p. 714 for solution.
0
1
00
0
1
01
1
1
11
0
0
10
0
0
Q+ = R'Q + S R'
11.11
11.7
See FLD p. 714 for solution.
11.8
See FLD p. 714 for solution.
11.9
See FLD p. 715 for solution.
11.10
See FLD p. 715 for solution.
11.12
For every input/state combination with the
condition SR = 0 holding, each circuit obeys the
next-state equation Q+ = S + R'Q. When S = R = 1,
in (a), both outputs are 1, and in (b), the latch holds
its state.
S
R
Q
11.13 (a)
Present
State
Q
0
1
AB
00
0
0
Next State Q+
AB
AB
01
11
0
1
1
1
11.13 (b)
AB
10
0
1
A
B
Q
P
Q+ = AB + QA + QB
Q+ = AB + Q(A + B)
11.13 (c) A change between AB = 01 and 10 can cause Q to
change depending on the inverter delays.
11.13 (d) P = Q' + A'B' equals Q' in all stable states.
109
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Unit 11 Solutions
11.13 (e)
A
B
11.13 (e) A change between AB = 01 and 10 can cause Q to
change depending on the inverter delays.
Q
P = Q'(A' + B') equals Q' in all stable states.
P
Q+ = (AB + Q)(A + B)
11.14 (a)
Present
State
Q
0
1
00
0
0
Next State Q+
A B
01
11
0
0
0
1
11.14
(b) &
(c)
10
1
1
Q+ = A(B' + Q)
This is a reset dominant latch where A´ acts a reset
and B´ acts as a set.
11.15 (a) Q+ = (M + N + G)[Q + (M + N+ G)N'G']
= (M +N + G)[Q + N'G']
= (M + N + G)Q + MN'G'
11.15 (b)
Q
0
1
000
0
0
001
0
1
011
0
1
GMN
010
100
1
0
1
1
101
0
1
111
0
1
110
0
1
The stable states are in bold.
11.15 (c) When G = 1, the circuit is always stable. When G = 0, M and N determine the state; N = 1 makes the state stable and
with N = 0 the state becomes the value of M. There would be a restriction on M and N if they could cause both inputs
to the output latch to be 1 when G = 0. This is not possible so there is no restriction.
11.15 (d) P = Q'[N + G + M'N'G'] = Q'[N + G + M']
For every stable state, P = Q' so P is usable as the complement of Q..
11.16 (a) Q+ = AB + QB
11.16 (b)
11.16 (c) AB = 01 is a hold input combination, AB = 00 and
10 are reset input combinations, and AB = 11 is a
set input combination. This is reset dominant latch
where S = A and R = B'. P = Q' + B'. In each
stable state P = Q' even for the input combination
AB = 10 (SR = 11) so P is usable as Q'. Allowing
the input combination AB = 10 (SR = 11) would
result in unreliable operation if both A and B could
change at the same time, i.e., change to AB = 01
(SR = 00), because the latch could end up in either
state 0 or 1 depending upon the delays in the circuit.
110
Present
State
Q
0
1
00
0
0
Next State Q+
A B
01
11
0
1
1
1
10
0
0
The stable states are in bold.
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Unit 11 Solutions
11.17
(a) Q+ = R'(S + Q) if SR = 0
(b) Q+ = (G + Q)(G' + D)
(c) Q+ = D
(d) Q+ = (Q + CE)(CE' + D)
(e) Q+ = (J + Q)(K' + Q')
(f) Q+ = (T + Q)(T' + Q')
11.18
D
G
Q
S
R
11.19
11.20 (a)
Clock
SRQ
00 0
00 1
01 0
01 1
10 0
10 1
11 0
11 1
D
Q
P
11.20 (b) A set-dominant FF from an S-R FF—The
arrangement will ensure that when S = R = 1, S1 = 1,
R1 = 0, and Q+ = 1.
S
S1
Q
R1
Q'
11.21
CK
R
Q+
0
1
0
0
1
1
1
1
R Q
S
0
1
00
0
1
01
1
1
11
0
1
10
0
1
Q+ = S + R'Q
Clock
S
R
Q
11.22 (a)
Clock
& (b)
J
K
(a) Q
(b) Q
111
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Unit 11 Solutions
11.23 (a)
Clock
& (b)
Q
(a) D
(b) T
11.24
Clock
Q0
Q1
Q2
5
11.25
10
15
20
25
30
35
40
45
50 t (ns)
Clock
PreN
T
Q
11.26
11.27 (a)
Clock
D
ClrN
Q
R
Q'
CK
D
Q1
When D = 0, then S = 0, and R = 1, so Q+ = 0.
When D = 1, then S = 1, and R = 0, so Q+ = 1.
Q2
11.27 (b) R will not be ready until D goes through the
inverter, so we must add the delay of the inverter to
the setup time:
Setup time = 1.5 + 1 = 2.5 ns
S
11.28
+V
S
Propagation delay for the DFF:
2.5 ns (same as for the S-R flip-flop, since the
propagation delay is measured with respect to the
clock)
Q
+V
R
112
© 2010 Cengage Learning. All Rights Reserved. May not be scanned, copied or duplicated, or posted to a publicly accessible website, in whole or in part.