Journal of the Korean Physical Society, Vol. 40, No. 4, April 2002, pp. 592∼594
Design and Fabrication of the Driving Circuits for One-Chip FED
on the Standard CMOS Process
Jong Duk Lee,∗ Jung Hyun Nam, Hyuck In Kwon and Byung-Gook Park
School of Electrical Engineering, Seoul National University, Seoul 151-742
(Received 11 Feburauy 2001)
Driving circuits must be implemented on the same substrate for microdisplay applications. To
integrate field emitter array with CMOS driving circuits on a single crystalline silicon, we propose a
simple fabrication scheme. The test patterns of the driving circuits consisted of a high-voltage MOSFET, and the driving circuits were fabricated on the basis of the 1.5-µm standard CMOS process.
The measured characteristics of the high-voltage MOSFET (HVMOSFET) showed a breakdown
voltage of about 120 V, which was high enough compared with the FEA operating voltage. The
low leakage current was shown to be under 100 pA, which was small enough to restrict the emission
current of the FEA. The operations of the shift register under 50 MHz and that of 8 bit D/A
converter were also confirmed.
PACS numbers: 79.70.+q
Keywords: CMOS one-chip FED, 1.5 µm standard CMOS process, High voltage MOSFET, Driving circuit
standard CMOS process.
I. INTRODUCTION
Field emission displays (FEDs) have merit in that active devices with good performance can be fabricated on
a single crystalline silicon wafer. A small size and high
resolution display system with low power consumption,
which is required for head-mounted displays (HMDs) or
electronic viewfinders of video camera systems, can be
a break-through application which can utilize the merits
of FED [1]. Fig. 1 shows the general configuration of a
one-chip FED system for microdisplay application.
The fabrication process for field emitters is similar to
that for nMOS. NMOS circuits can be easily used, preferably for integrating the driving circuits. However, that
requires a high operating voltage and a large static current [2]. Moreover, the output level of an nMOS circuit varies according to the device parameters. Accordingly, there are very narrow process margins in fabricating nMOS circuits and field emitter arrays simultaneously. Using CMOS logic circuits, the operation margin and the circuit performance can be enlarged. In
addition, the Inter-University Semiconductor Research
Center (ISRC) standard process gives device parameters
well established for circuit design. A fabrication process
scheme, with which high voltage MOSFET (HVMOSFET) and FEA can be integrated without affecting the
standard CMOS device parameters, is proposed for the
first time. In addition, the test patterns for the driving
systems were fabricated on the basis of the ISRC 1.5-µm
∗ E-mail:
II. SYSTEM DESIGN
The first thing to be considered is an adequate pixel
structure for a one-chip FED. Most recently developed
field emitters require a high driving voltage of about
60∼100 V. However, on-chip driving circuit based on the
standard CMOS process has been established on the basis of 5 V operation. So it is difficult to operate at such a
high voltage. As one solution, the concept of an MCFEA
(MOSFET controlled field emitter array) in which the
MOSFET, which can endure the high voltage between
Fig. 1. Configuration of the one-chip FED system. A field
emitter symbol represents an array of multiple field emitters.
[email protected]
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Design and Fabrication of the Driving Circuits for One-Chip FED· · · – Jong Duk Lee et al.
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Fig. 2. Cross-sectional view of designed MCFEA pixel
considering standard CMOS process. The HVMOSFET is
composed of active region (L1) and drift region (L2).
the source and the drain, controls the emission current
of the FEAs has already been proposed [3], and some
successful results have been reported [4].
In this paper, a simple fabrication scheme which can
integrate FEAs, high voltage MOSFETs, and driving circuits based on the standard CMOS process is proposed.
Fig. 2 shows the proposed structure for the MCFEA. It
follows all the standard CMOS fabrication processes, except for the pad opening. For making the FEAs, the large
areas of the n-wells are exposed by opening contact holes.
An FEA gate oxide composed of an inter-metal dielectric
and passivation oxide is deposited to about a thickness
1.8 µm. Holes with 1.5 µm diameters are etched, and Mo
tips and extraction gates are made by using the Spindt
process [5].
As shown in Fig. 2, the HVMOSFET for the MCFEA
is composed of an active region (L1) and drift region
(L2). While L1 mainly contributes to the channel current control, L2 is designed for high- voltage breakdown.
Therefore, the threshold voltage of the active region is
the same as that of nMOSFET used in driving circuits.
On the other hand, the threshold voltage of drift region
remains about 0 V to keep a low doping concentration
which reduces the electric field around the drain edge to
Fig. 3. The simulated potential contour of the HVMOSFET by 5 V step. The drain is biased by 80 V and the gate
voltage is maintained at 0 V. The maximum field is shown at
the edge of field oxide.
Fig. 4. The physical layout result for the 4×3 one-chip
FED system.
increase the drain breakdown voltage. When the HVMOSFET is turned on, a drain current larger than the
required emission current must be able to flow. When
it is turned off, the drain current must be constricted to
under 1/1000 of the turn-on emission current, and the
HVMOSFET must be protected from breakdown due to
the voltage between the drain to the source, which may
be as high as the FEA extraction gate voltage. The simulated result shown in Fig. 3 shows that a high drain
bias voltage of 80 V is dispersed through the drift region
when the HVMOSFET is turned-off to reduce the peak
magnitude of the electric field.
Fig. 4 shows the physical layout result for a 4×3
one-chip FED system. In the figure, MCFEA pixels of
300×300 µm size are arrayed as the core part. The row
and the column driver circuits are located on the left side
and at the bottom, respectively. Each pixel contains 625
field emitter tips with gate hole diameters of 1.5 µm.
The row line selection is used for the driving circuits,
and 256 gray levels are pursued by using the pulse amplitude modulation (PAM) method. The outputs of the
column driver circuits are connected to the cathode of
the FEA, and those of row driver circuits are connected
to the gate of the HVMOSFET. The line scanners and
the data drivers are basically composed of D-flip flop as
shown in Fig. 5(a), which shows a presettable static Dflip flops, operated using a complementary single phase
clock. Fig. 5(b) shows the circuit of the 8 bit D/A
converter. The sizes of the current sources in the D/A
converter are decided by considering that the maximum
current value is about several tens of µA when VREF is
1.25 V. That is a controllable value considering 0.75 V,
which is the threshold voltage of the MOSFETs used for
the current sources. As the HVMOSFET operates only
as a pass of current from the D/A converter to the FEA,
it does not limit the current at turn-on state.
III. MEASUREMENTS
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Journal of the Korean Physical Society, Vol. 40, No. 4, April 2002
the ID -VD characteristics obtained from the HVMOSFET. The breakdown voltage is about 120 V, which is
high enough compared with the FEA operating voltage.
Fig. 6(b) is the IG -VD characteristic curve. The threshold voltage measured using the constant current method
is about 0.75 V, and it is similar to the threshold voltage
of the normal MOSFET fabricated in the process. This
means that the threshold voltage is controlled by the active region, as expected. The leakage current measured
in the off-state is under 100 pA. It is also small enough to
restrict the emission current of FEA when it is turnedoff. Fig. 6(c) and 6(d) show the operating characteristics
of a shift register and a D/A converter, respectively. In
the case of the shift register, its operation under 50 MHz
is confirmed from the delay measurement. The operation
of the D/A converter is also confirmed, and the reference
voltage for adequate current is about 1.3∼1.5 V.
IV. CONCLUSIONS
Fig. 5. (a) The presettable static D- flip flop used for the
shift register. (b) The circuit of D/A converter adopting the
pulse amplitude modulation (PAM) method. The current
value is decided by controlling VREF .
In this paper, a method for fabricating driver circuits
for one-chip FEDs based on the CMOS process is proposed. Test patterns were fabricated using the ISRC
1.5 µm standard process. The tips and extraction gates
were formed using a Spindt process after the standard
CMOS process had been completed. The fabricated test
patterns showed that the HVMOSFET had a turn-off
current of under 100 pA with a drain voltage of 80 V,
which was small enough to restrict the emission currents
of FEAs. The drain breakdown voltage was measured
to be about 120 V, which also was high enough for 80
V operation of the FED. The circuits for the row and
the column drivers were simply designed with presettable
static D-flip/flops and 8 bit D/A converters by using the
pulse amplitude modulation (PAM) method. The operating characteristics of the driving circuits were also
confirmed by using test pattern measurement.
REFERENCES
Fig. 6. (a) ID -VD characteristics of high voltage MOSFET.
High breakdown voltage over 100 V is confirmed. (b) ID VG characteristics of the high voltage MOSFET. Low leakage
current under 100 pA at drain voltage of 80 V is confirmed.
(c) The operational characteristics of a shift register. (d)
The operational characteristics of 8 bit D/A converter. The
linearity is confirme.
The test patterns of the HVMOSFET and the driving
circuits were fabricated and measured. Fig. 6(a) shows
[1] H. J. Girolamo, C. E. Rash and T. D. Gilroy, SID Information Display 13, 3 (1997).
[2] Jong Duk Lee, Nam Seog Kim, Il Hwan Kim and Byung
Gook Park, J. Korean Phys. Soc. 35, S1102 (1999).
[3] Jong Duk Lee, Donghwan Kim and Il Hwan Kim, The
Fourth International Display Workshops (Nagoya, Nov.,
1997), p. 715.
[4] Jong Duk Lee, Il Hwan Kim and Chang Woo Oh,
IVMC’98 (Asheville, NC, July, 1998), p. 44.
[5] C. A. Spindt J. Appl. Phys. 39, 3504 (1986).