TK2633
8085 Memory Interface
DR MASRI AYOB
Requirement and memory
structure
• There are two types of memory:
– RAM: read and write
– ROM: read only
• Figure 1a shows the R/W memory chip:
–
–
–
–
–
–
–
2048 (2k) size.
8 bit data input line and 8 bit data output line.
11 address lines, A0-A10,
one chip select, CS.
RD: enable output buffer (penimbal keluaran).
WR: enable input buffer (penimbal masukan).
The internal decoder is used to decode the internal
memory address.
2
Requirement and memory structure
Figure 1
3
Requirement and memory
structure
• Figure 1b shows the typical diagram of EPROM (Erasable
Programmable ROM):
– 4096 (4k) size.
– A quartz window on it, that use to receive direct UV light to erase
programme.
– 8 bit data output line.
– 12 address lines, A0-A11,
– one chip select, CS.
– RD: enable output buffer (penimbal keluaran).
– The internal decoder is used to decode the internal memory
address.
• The technique to interface R/W and EPROM is the same except
the EPROM does not require WR control signals.
When the chip is programmed, the quartz window has to be
covered to avoid accidental program erase.
4
Basic concept of interfacing
memory chip.
• The basic function of memory interfacing
is that the μp should be able to read from
and/or write into memory chip.
• Therefore the μp has to:
– Be able to select certain memory chip.
– Identify memory location through memory
address.
– Enable input or output buffer as to read or
write to the memory.
5
Basic concept of interfacing
memory chip.
• A few basic steps to undertake in chip
interface design are:
– Connect certain address lines from address
bus of μp to address lines at memory chip.
– Decode the rest of the address lines to
generate Chip Select signal.
– Generate control signals MEMR and MEMW.
6
Decoding the address lines
• Figure 2 shows two techniques to decode
address lines:
– Using the NAND gates.
– Using the 3-to-8 decoder.
• The output of NAND gate can be activated
when all the input A12-A15 is at logic 1.
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NAND or Decoder
Figure 2
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Decoding the address lines
• Using the 3-to-8 (74LS138) decoder:
– combining the input A12-A14 to obtain output
at O7 when A12= A13= A14=1.
– The enable pins E1 and E2 are enabled by
grounding them and the A15 digital signal
should be at logic 1 to enable the E3.
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74LS138 3-to-8 Line Decoder
Inputs
E1
1
x
x
0
0
0
0
0
0
0
0
E2
x
1
x
0
0
0
0
0
0
0
0
E3
x
x
0
1
1
1
1
1
1
1
1
C
x
x
x
0
0
0
0
1
1
1
1
Outputs
B
x
x
x
0
0
1
1
0
0
1
1
A
x
x
x
0
1
0
1
0
1
0
1
0
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
2
1
1
1
1
1
0
1
1
1
1
1
3
1
1
1
1
1
1
0
1
1
1
1
4
1
1
1
1
1
1
1
0
1
1
1
5
1
1
1
1
1
1
1
1
0
1
1
6
1
1
1
1
1
1
1
1
1
0
1
7
1
1
1
1
1
1
1
1
1
1
0
10
Memory interface
Figure 3
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Reading and decoding address lines
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Address Decoding
• Referring to figure 3:
– the logic combination at address A15-A12 must
have logic 0000 to activate the Chip Enable,
– and the address A11-A0 can have all logic
combinations either 0 or 1.
– Therefore the range of address for this chip is
0000H until 0FFFH;
A15 A14 A13 A12
A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0
1
0
0
0
Chip Enable
1
1
1
1
1 1
1
1 1
1
1
Register Select
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Address Decoding 2K RAM
Address Range?
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Address Decoding
Note: A11 is not used for RAM.
ROM
RAM
Address Range ?
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Address Decoding
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Address Decoding
ROM1
A12
A
A13
B
A14
C
IO/M
E1
E2
E3
0
3-to-8 1
decoder 2
74LS138 3
4
5
6
7
CE
ROM2
CE
OE
RAM1
CE
OE
1K
+5V
RAM2
WE
CE
OE
WE
RD
WR
Address Range?
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Thank you
Q&A
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