Report for Experiment 7
Date : 2013. 2. 7
Class : CSE20102
Student ID : 20121314
Name : 안 혜 림
Report for Experiment 20
Objectives :
□ Design a synchronous counter with up to 16 states in any selected order.
□ Construct and test the counter. Determine the state diagram of the counter.
Data and Observations.
QC
0
0
0
0
1
1
Present State
QB
QA
0
0
0
1
1
1
1
0
1
0
0
0
QC
0
0
0
1
1
0
Next State
QB
0
1
1
1
0
0
QA
1
1
0
0
0
0
TABLE 20-1
Transition table for J-K flip-flop (repeated for reference).
Output Transitions
QN
QN+1
0
0
0
1
1
0
1
1
Inputs
JN
0
1
X
X
KN
X
X
1
0
QN = output before clock
QN+1 = output after clock
JN, KN = inputs required to cause trasition
X = don’t care
0
0
X
X
0
1
X
X
1
X
X
0
1
0
X
X
X
X
0
0
0
X
X
1
X
X
0
X
X
X
1
X
0
X
X
X
X
X
1
X
0
X
X
X
0
X
X
X
JC=QAQB
KC=QB
JB=QA
KB=QC
JA=QCQB
['Excitation Table', on Karnaugh Map]
KA=QB
Circuitdesign
[Figure1] set up the circuit
[Figure2]
set up the circuit using AND gate(simple)
[FIGURE 3]
The picture of the circuit.
:
Results and Conclusion:
This experiment is to design a synchronous counter in any selected
order, construct, and test it. The design of a synchronous counter
begins with a description of the state diagram that specifies the
required sequence. States that are not in the main sequence should be
shown only if the design requires these unused states to return to the
main sequence in a specific way.
First, draw the state diagram and draw next state table. Next,
determine inputs required for each flip flop, looking 'Excitation Table',
on Karnaugh Map. Using these inputs, we could draw circuit and
make it on bread board.
We can see counter clock image in LED lamp in figure 4.
[Figure 4]