Path Delay Test Compaction
with Process Variation Tolerance
Design Automation Conference
June 16, 2005
Seiji Kajihara Masayasu Fukunaga Xiaoqing Wen
(Kyushu Institute of Technology, JAPAN)
Toshiyuki Maeda Shuji Hamada Yasuo Sato
(STARC, JAPAN)
Outline

Introduction
– Path selection in path delay testing
– Test pattern compaction in ATPG
– Purpose of this work

Proposed Method
– Basic idea of the proposed method
– Advantages of the proposed method

Experimental Results

Conclusions
Background

Defects affecting timing behavior are becoming
dominant for DSM circuits.
– Path Delay Fault： Model the increased delay of a path
between two FFs.
– Test patterns generated for path delay faults can
detect many other types of delay faults.
FF
FF
Fault-Free
Faulty
Capture
Path Delay Testing Issue - 1

The number of paths is too large to allow efficient
test pattern generation if all paths are targeted
in ATPG.
4 paths
10 paths
16-Bit Multiplier：2000 gates / 1019 paths
Only a subset of paths can be targeted: Path Selection
Paths and Untestable Paths
Circuit
#paths
C880
17,284
C3540 57,353,342
C6288
1.978E+20
S13207 2,690,738
S15850
3.29E+08
S35932
394,282
S38417 2,783,158
S38584 2,161,446
#untestable %unt.
time
163
37,869,721
1.977E+20
1,946,331
2.75E +08
270,057
861,860
1,470,244
1
9
71
41
60
493
224
450
0.94
66.0
99.9
72.3
83.6
68.4
30.9
63.3
Runtime (sec.) was measured on HP735 [Kajihara, VLSID97]

The number of remaining paths which are not
identified as untestable is still large.
Path Selection Methods

N Longest Paths in a Circuit
– Select N longest paths in the order of path lengths.
– The selected paths may not be distributed all over
the circuit and may be locally concentrated in a part
of the circuit.

Longest Path through Each Line
– Contains at least one of the longest paths through
each line.

Statistical Method / Dynamic Method

Two Path Sets
Path Delay Testing Issue - 2 & 3

Process Variation
– Structurally longest paths may not be actual longest
paths in a manufactured circuit due to process
variation.
– It is difficult to know exact delay distribution of
manufactured circuits.
– The longest paths may be different for each
manufactured circuit.
– Statistical path selection approaches are still
insufficient.

Test Set Size
– The number of tests is usually large.
– The reasons are that a two-pattern test is required to
detect one delay fault and that the constraints for the
patterns are stronger than those for stuck-at faults.
Related Work – Test Compaction


A procedure to reduce the size of a test set
without causing fault coverage loss.
Dynamic Compaction
– Using unspecified values in a test cube to detect
other faults during ATPG.
test for the primary fault:
0xx1xx0
 test for one secondary fault:
01x1x00
 test for one more secondary fault: 0101100


Static Compaction
– Merging multiple tests into one after ATPG.
test for a fault :
 test for another fault :
 Merged test :

0x10
x1x0
0110
Goal of Our Work
All Faults
Path Selection
Target Faults
ATPG
Initial Test Set
Static Compaction
Compacted Test Set
Increase Accidental Detection
Coverage
of
Targeted
Faults
Compacted
Initial
# of tests
Problem Statement

Input
– Circuit: the netlist of a full scan circuit
– Target Fault List: selected by a path selection criterion
– Initial Test Set: uncompacted

Output
– Compacted Test Set:
Fault coverage for the target fault list remains unchanged.
 The number of two-pattern tests are small.
 The number of accidental detections is large.

Outline

Introduction
– Path selection in path delay testing
– Test pattern compaction in ATPG
– Purpose of this work

Proposed Method
– Basic idea of the proposed method
– Advantages of the proposed method

Experimental Results

Conclusions
Basic Idea of Our Method

Simultaneous Testing and Target Path Crossing
– Case 1 (simultaneous / no-crossing):
T
T: two paths tested
– Case 2 (simultaneous / crossing):
T
T: four paths tested
Accidental Detection

When two target paths with a common gate are
tested simultaneously with the same test, paths
other than the two target paths may also be tested.
p1
p3
p1
p2
Common Gate
p2
p4
Common Gate
p1: 10
11
10
11
p2: 10
10
11
10
10
11
10
10
Common Gate
– p1 and p2 are tested by the same two-pattern test.
– Simultaneous testing achieved by dynamic (multitargeting) or static compaction (merging).
– Certain conditions need to be satisfied at the common
gate in order for accidental detection to occur.
Conditions for Accidental Detection
(1)
(2)
(3)
The common gate has fanout branches.
Two paths have the same type of transition
at the inputs of the common gate.
The transition at the common gate is from the
controlling value to the non-controlling value.
Transition from CV to NCV
Transition from NCV to CV
Example
p1: 10
11
10
11
p2: 10
10
11
10
10
11
Common Gate
All three conditions are satisfied.
10
10
Increasing Accidental Detection

The more common gates (with fanout branches),
the more accidental detections.
p1
p1
p2
p2
4 paths are tested
8 paths are tested
Advantages

Smaller Number of Two-Pattern Tests

Better Process-Variation-Tolerance Capability
– With many accidental detections related to target
paths (longest by analysis), the chances of detecting
a real critical path (longest by fabrication) in a
manufactured circuit are higher.
p1
p3
p2
Targeted Paths
in ATPG
Longest Path
in a manufactured circuit
Outline

Introduction
– Path selection in path delay testing
– Test pattern compaction in ATPG
– Purpose of this work

Proposed Method
– Basic idea of the proposed method
– Advantages of the proposed method

Experimental Results

Conclusions
Experimental Results

Circuits
– Full-scan version of ISCAS’89 benchmark circuits

Conditions of Delay Fault Testing
– Two-pattern test application: enhanced scan
– Path sensitization: non-robust

Target Fault List
– Longest path through each line

Test Compaction Technique Used
– Simple static compaction
Static Compaction Flow - Ours
All Faults
Path Selection
Target Faults
ATPG (one target fault per test / keep don’t care bits)
Initial Test Set
Static Compaction (find two compatible tests whose target paths
have the largest number of common gates,
and merge them into one test)
Compacted Test Set
with many accidental detections
Comparison Flow - Uncompact
All Faults
Path Selection
Target Faults
ATPG (- one target fault per test
- random X-filling for all don’t care bits
- fault-simulation-based fault dropping)
Test Set
Statistics of Circuits and Faults
Circuit
Total Paths
Testable
Paths
Target
Paths
Testable
Target Paths
s5378
27,084
21,928
9,644
9,524
s9234
489,708
59,854
15,458
15,377
s13207
2,690,738
476,145
27,111
26,054
s15850
329,476,092
10,782,994
89,298
85,938
s35932
394,282
58,657
39,124
39,124
s38417
2,783,158
1,138,194
224,101
209,161
s38584
2,161,446
334,927
59,519
58,221
Tests and Fault Efficiency
Circuit
Number of Tests
Uncompact
Fault Efficiency
Ours
Uncompact
Ours
s5378
3,362
800
88.52%
84.81%
s9234
4,212
1,280
62.66%
58.25%
s13207
3,722
1,466
43.28%
40.72%
s15850
6,236
3,230
18.66%
18.16%
s35932
550
66
98.79%
82.83%
s38417
59,428
6,994
63.17%
55.91%
s38584
9,162
2,344
65.84%
65.28%
Test set sizes were reduced approximately to 25% of those of the uncompact
test sets; while the uncompact test sets have a little higher fault efficiency.
Effects of the Proposed Method
Circuit
Detected Faults per Test
Coverage for 10,000 Longest
Paths
Uncompact
Uncompact
Ours
Ours
s5378
5.77
23.25
92.26%
87.85%
s9234
8.90
27.24
62.39%
61.66%
s13207
55.37
132.26
78.91%
77.98%
s15850
322.72
606.18
96.00%
97.84%
s35932
105.36
736.18
99.66%
90.43%
s38417
12.10
90.99
99.97%
99.88%
s38584
24.07
93.27
81.80%
82.86%
For circuits s15850 and s38584, the compacted tests could test more paths
than the uncompact test sets, with a smaller number of test patterns.
Effects of the Proposed Method
Circuit
Crossing
Paths
Percentage of
Crossing Paths
Crossing Paths
per Test
s5378
1,556
8.37%
1.95
s9234
2,548
7.31%
1.99
s13207
2,721
1.40%
1.86
s15850
142,942
7.30%
44.25
s35932
1,349
2.78%
20.44
s38417
14,284
2.24%
2.04
s38584
7,306
3.34%
3.12
Conclusions

A Test Compaction Technique for Path Delay Testing
– Reducing the number of tests
– Improving the process-variation-tolerance capability

Key Idea
– Simultaneous testing of target paths with as many
common gates as possible

Future Work
– Better static compaction algorithm & implementation
– More experiments
– Extension to dynamic compaction