Optimum test selection for analog circuits with the
use of information channel concept.
J. Rutkowski #, B. Puchalski ##
#
Silesian Technical University in Gliwice, Institute of Electronics
ul. Pstrowskiego 16, 44-100 Gliwice, POLAND
e-mail : jr.boss.iele@[157.158.17.2]
##
Silesian Technical University in Gliwice, Institute of Electronics
ul. Pstrowskiego 16, 44-100 Gliwice, POLAND
e-mail : [email protected]
ABSTRACT
This paper deals with the problem of optimization of analog circuits. The concept of
information channel is utilized in selection and ordering of tests. A new criterion evaluating
the effectiveness of the test is proposed. Both information factor and time effort factor are
considered.
Keywords: analog circuits, faults, information channel, optimization, testing.
1 INTRODUCTION
Integration level of VLSI chips increases constantly. In consequence the development of
more advanced and sophisticated testing techniques is required. For digital circuits robust
solutions have been proposed. Test program development is facilitated by the use of
dedicated CAD tools. In case of analog circuits the problem is much more complicated. As
a result, although this subject has been investigated by researchers for more than three
decades, there is still not user-available CAD software supporting this process.
So far, many testing techniques of analog circuits have been proposed. Following [1,2],
they can be divided into two main categories: simulation before test (SBT) and simulation
after test (SAT). SBT is used to detect catastrophic faults (i.e. shorts and opens) while SAT
is used to detect parametric faults (i.e. small changes in parameter values due to variations
of manufacturing process). In practice, it is not possible to provide the desired fault
coverage performing a single test. In analog circuits many specifications must be verified
during post-production tests. Therefore series of many tests are performed. This may result
in unacceptable testing times. For mature products the reduction of time-to-market is the
aim. However, for selecting the most effective strategy of post-production testing,
knowledge of statistical data is necessary. In consequence in the stage of pre-production
testing information about failure modes must be maximized. Thus, the selection of
optimum set of tests and order of their performance is very significant.
In [3] it was proven that the utilization of information channel is very useful in
optimization of testing of analog circuits. However, the usage of this idea was confined to
a single test (i.e. fault diagnosis by means of Dictionary technique, which belongs to SBT
testing category). In this paper more general approach is presented. The concept of
information channel is used to optimize the whole testing process. Both, information about
failure modes and time effort of a particular test are considered.
2 OPTIMUM ORDERING OF TESTS
As mentioned before, fault location techniques can be categorized according to the stage in
the testing process at which simulation of the tested circuit occurs. We have simulationbefore-test and simulation-after-test approach. In [2], classification of testing techniques is
presented. The most popular are fault dictionary techniques which belong to SBT category.
The dictionary construction, optimum test point selection and fault simulation play very
important role in this approach. Thanks to the low on-line computational effort they are
suitable for practical use. Parameter identification techniques constitute another family,
belonging to SAT category. Under the assumption that enough independent measurements
are available, all network parameters could be identified. In case of unavailability of
enough measurements, all network parameters cannot be identified. Fault verification
techniques address this problem. The basic assumption is that only few elements are faulty
and the rest of the network elements are within tolerances. These techniques also belong to
SAT category. For both, SBT and SAT, different stimuli can be selected, such as dc, ac or
time domain. Moreover apart from SBT and SAT, which are fault driven tests, functional
tests can be performed. In such tests the design specifications are checked, usually at the
different selected frequencies ore time instants. As can be seen vast variety of tests can be
performed. However, it should be emphasized, that the detailed study of different testing
techniques is beyond the scope of this paper. It is presumed, that a “package” of well
known, optimized testing methods is given. The problem of choosing between particular
tests belonging to different categories is addressed.
We presume that the list of possible faults (x0, x1, … xn) has been created and the set of
possible tests (T1, T2, … Tm) has been proposed. Of course for selecting the most effective
strategy of testing, knowledge of statistical data is required. Following [1], one way of
acquiring such a statistical information is to exhaustively and nonoptimally test a sample of
chips during the pre-production test. Nevertheless, it may be desirable to optimally order
and/or select a best subset for production testing for a new product prior to the availability
of a large database of historical pass fail data. In order to find an optimal set of tests
inclusion strategy is used. For the first time the inclusion and exclusion concept was
proposed in [4]. Originally it was used in selecting the optimum test points for dictionary
techniques, but it can be exploited in selecting particular tests as well.
Initially the test set is empty. Subsequently, to find an optimum set of tests, one by one
tests are included in the set. To select the most effective test at the k-th stage of testing
process, the effectiveness factor will be introduced, as given by equation (1).
(k)
Q(Ti(k) )  a I(Yi(k) / X(k) ) / H(X(k) )  b t (k)
min / t i
(1)
where:
Ti(k) is the i-th test performed as the k-th in a row.
a,b are weights, such that a+b=1.
X(k) is the information channel input, i.e. circuit states not distinguished before the k-th test,
k=1,2,…,kmax.
H(X(k)) is a circuit entropy left before the k-th test.
Yi(k) is the channel output, the i-th test results when performed as the k-th one in a row.
I(Yi(k)/ X(k)) is the mutual information obtained from the i-th test when performed as the kth one in a row.
ti(k) is the time effort of Ti(k).
tmin(k) is the minimum value of ti(k) of all tests available at the k-th stage of test selection and
ordering.
Q factor consists of two parts: information factor and time effort factor. The weighs a
and b decide which factor should prevail. As mentioned earlier, reduction of testing time is
significant for mature products and in this case time effort should be the predominant factor
(b>a). On the contrary, in the early stages of production, it may be desired to acquire more
details about failure modes of the circuit and information factor should be predominant
(a>b). In case a=b=0.5 both factors are of equal significance. For the ideal test Q=1,
regardless the values of weighs a and b.
During the first step, the effectiveness factor Q for all tests is calculated. Test, for which
this factor has the maximum value, is included in the set. Subsequently, the check if there
are any faults, that have not been identified yet (i.e. there is still a circuit entropy left) is
done. If so, another test must be added to the set. Again, effectiveness factor is calculated
for all remaining tests, but only unidentified faults are taken into consideration. Test, which
gives the maximum value of Q is included in the set. The whole procedure is repeated until
all the faults are isolated.
Of course, to calculate the factor, probabilistic model of a channel has to be known, for
each test category and selected classification method. It is assumed that data necessary to
build such model have been acquired during pre-production tests and simulations. Also the
order of complexity of each testing method should be known, such that time effort can be
evaluated. No absolute value of such time has to be known, only its ratio to the minimum
time, denoted by ci(k)
(k) (k)
t (k)
i  c i t min
(2)
To better understand this concept, a simple example presented below is used. Let us
imagine a circuit with 8 different failure modes: x0, x1, … x7. By x0 we denote a circuit
without failures. There are 4 catastrophic faults (x1 … x4) and 3 parametric faults (x5 … x7).
Let us presume that 3 tests are available (T 1, T2, T3). They are presented in the diagram
form in Fig.1. Test T 1 is a simple go/no go test. It is aimed to detect only the healthy state.
As can be seen it properly differentiates between state without failures and catastrophic
faults, but is unable to detect parametric faults. T 2 and T3 are aimed to isolate catastrophic
and parametric faults respectively.
X
x0
x1
x2
x3
x4
x5
x6
x7
TEST 1
Y1
X
x0
x1
x2
x3
x4
B ( 1 , 2 ,3 , 4 ) x
5
x6
x7
A ( 0 , 5 ,6 , 7 )
TEST 2
Y2
A (2 )
B ( 0 , 1 ,6 )
C ( 3 ,5 )
D ( 4 ,7 )
X
x0
x1
x2
x3
x4
x5
x6
x7
TEST 3
Y3
A ( 0 , 5 ,2 )
B ( 1 , 3 ,6 )
C ( 4 ,7 )
Figure 1: Diagram representation of exemplary tests.
As can be seen, T2 distinguishes between 4 catastrophic faults but mistakenly identifies
healthy state and 3 parametric faults. Similarly T 3 properly identifies 3 parametric faults but
has problems with other circuit states. For our calculation uniform distribution of
probabilities is assumed (p(xj)=0.125, j=0…7). Time effort of these tests equals t 1=1.5 tmin,
t2=tmin, t3=1.9tmin. Input entropy equals H(X 1)=ld8=3 bits. Both weighs are equal a=b=0.5.
Now the mutual information and effectiveness factor may be calculated for three tests.
I(Y1/X)=1 bit
Q(T11)=0.5*1/3 + 0.5*1/1.5=0.17+0.33=0.5
I(Y2/X)=1.9 bit
Q(T21)=0.5*1.9/3 + 0.5*1=0.17+0.5=0.82
I(Y3/X)=1.56 bit
Q(T31)=0.5*1.56/3 + 0.5*1/1.9=0.26+0.26=0.52
Test T2 gives the maximum value of effectiveness factor and will be included in the test set.
As mentioned earlier, it is impossible to isolate all faults performing a single test.
Considering T1 from previous example, 8 failure modes are grouped in 2 sets corresponding
to 2 possible results. In case of 4 catastrophic faults, circuit is marked as faulty, but
particular circuit states (x1 … x4) cannot be identified. Similarly, distinction between
healthy state x0 and three parametric faults (x5 … x7) is also impossible. We may say, that
they belong to the same ambiguity set. The concept of ambiguity set has originally been
introduced in fault dictionary testing techniques [5,6]. For the particular testing point,
measurements taken under different circuit conditions, that could not have been
distinguished, were grouped into one ambiguity set. However, in this paper more general
approach is presented. As mentioned before, a package of well known and optimized
testing techniques is given. For the particular test, circuit states that cannot be
distinguished, are grouped into ambiguity sets, regardless category the test belongs to.
These ambiguity sets are denoted as: S kj where j denotes the test and k ambiguity set number
for the given test. It may happen, that a certain circuit state cannot be allocated to any of the
possible results of the test (e.g. occurrence of catastrophic fault not defined in fault
dictionary). In this case additional ambiguity set “unknown” should be introduced.
In following example a hypothetical circuit is examined. A list of 23 failure modes is
given (x0,..,x22). A nominal condition is denoted by x0. 15 tests are available (T1,..,T15).
Moreover, information about time effort of each test is known. According to (2) time effort
is expressed in the form of ratio (c1,..,c15). A hypothetical results of the tests are given in
Table 1, using the concept of ambiguity set. This representation can be compared with
integer-code fault dictionary presented in [6]. Time efforts are also included in Table 1. At
first, both weighs are equal a=b=0.5. The effectiveness factor Q(T i1) is calculated for all
tests (i=1..15). At the first stage, the second test T 2 is chosen, because it gives the highest
value of factor Q(T21)=0.8. Subsequently the operation is repeated. All the remaining tests
are evaluated. At the second stage, test T 5 returns the greatest value of effectiveness factor
Q(T52)=0.93, and is added to the optimum set. The whole procedure is repeated until the
input entropy is compensated by the mutual information. In our example tests T1, T7 and
T12 are added to the optimum test set. After the fifth stage of the procedure, the input
entropy has been compensated and the algorithm is stopped. All the failures may be
identified by performing 5 tests {T 2, T5, T1, T7, T12}. All the results are presented in Table
2. Subsequently weighs were changed. Information factor was increased (a=0.9) and time
effort factor was decreased (b=0.1). In this case the optimum test set consists of 3 tests {T 9,
T2, T5}. All the results are presented in Table 3. The first case (a=0.5) is suitable for mature
products where time-to-market is the aim whereas the second case (a=0.9) puts emphasis on
the failure mode information which is more important in pre-production testing.
4 CONCLUSIONS
The optimization of testing processes is very important for analog circuits. A completely
new approach has been proposed. The utilization of information channel concept is very
useful to optimize a single test (fault dictionary method [2]) as well as the whole testing
process. The proposed method takes into account both information and time effort.
Moreover, not uniform distribution of probabilities can be considered, which is a common
case as probability of a healthy state is normally much greater than all others. Another
benefit of this method is its low computational complexity. Very time consuming
exhaustive search and a shortest path search with heuristic modifications the only known
alternative approaches to test selection problem [1].
Table 2.Effectiveness factors for a=b=0.5 (5 stages)
T1
T2
T5
T7
Test
T3
T4
T6
T8
T9
Q(Ti1) 0.49 0.80 0.49 0.42 0.77 0.41 0.55 0.36 0.51
Q(Ti2) 0.67
0.59 0.58 0.92 0.60 0.75 0.52 0.64
Q(Ti3) 0.87
0.65 0.65
0.69 0.80 0.57 0.66
Q(Ti4)
0.64 0.64
0.69 0.79 0.57 0.66
Q(Ti5)
0.67 0.65
0.71
0.57 0.66
T10
0.40
0.54
0.58
0.58
0.58
T11
0.41
0.59
0.64
0.63
0.66
T12
0.49
0.67
0.76
0.76
0.78
T13
0.51
0.62
0.67
0.67
0.67
T14
0.44
0.54
0.62
0.62
0.62
T15
0.39
0.52
0.62
0.61
0.64
Table 3.Effectiveness factors for a=0.9, b=0.1 (3 stages)
T2
T5
T9
Test
T1
T3
T4
T6
T7
T8
T10 T11 T12 T13 T14 T15
Q(Ti1) 0.22 0.63 0.61 0.46 0.66 0.40 0.49 0.53 0.67 0.60 0.49 0.44 0.65 0.59 0.48
Q(Ti2) 0.78 0.98 0.89 0.84 0.95 0.83 0.92 0.85
0.90 0.91 0.81 0.91 0.88 0.91
Q(Ti3) 0.96
0.93 0.94 0.99 0.94 0.96 0.89
0.92 0.93 0.93 0.93 0.90 0.93
Table 1. Hypothetical tests results and time efforts for Example 2.Table 2.Effectiveness
factors for a=b=0.5 (5 stages)
Circuit state
x0 (nom)
x1
x2
x3
x4
x5
x6
x7
x8
x9
x10
x11
x12
x13
x14
x15
x16
x17
x18
x19
x20
x21
x22
Time effort
ci
Test results
T1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
T2
0
1
2
3
4
5
u
3
3
4
u
u
u
2
2
2
1
2
4
4
0
0
0
T3
u
u
5
3
5
1
2
3
4
5
6
7
8
u
u
2
7
3
u
u
1
1
1
T4
u
u
u
u
u
u
u
u
u
u
5
1
2
3
4
5
6
7
8
u
u
u
u
T5
2
1
2
3
u
u
5
2
3
6
1
3
4
u
u
1
3
5
2
7
2
7
3
T6
u
u
u
u
u
u
u
u
u
u
u
u
u
u
4
2
1
2
1
2
3
4
5
T7
2
1
3
4
2
3
0
1
3
3
2
1
3
0
2
3
4
2
3
4
2
1
2
T8
0
u
u
2
3
5
2
3
1
2
0
0
u
5
u
3
3
u
4
1
u
2
u
T9
u
5
3
2
1
8
9
7
5
6
4
3
2
5
7
8
9
3
u
8
6
2
3
T10 T11 T12 T13 T14 T15
5
u
0
9
0
u
1
0
1
0
u
0
2
0
2
0
u
0
2
0
1
0
u
0
2
0
1
3
1
2
3
0
2
2
2
1
5
3
1
1
3
4
4
2
2
4
3
3
6
3
1
6
3
3
4
2
2
6
4
3
3
1
3
9
5
3
u
1
3
9
6
3
u
1
3
5
7
3
7
1
3
8
8
u
6
1
2
7
u
u
5
2
2
1
u
u
4
2
1
u
u
u
8
4
2
u
u
u
3
3
4
u
5
u
4
2
3
u
4
4
4
1
3
u
3
4
4
2
3
u
4
4
3
2
2
u
u
4
1.2
1
3
2.7 1.1 2.4 1.6 7.3 3.2 6.3 3.2 1.8 2.9
4
3.7
REFERENCES
[1] Linda Milor. A tutorial introduction to research on analog and mixeds-signal circuit
testing. IEEE Trans. on CAS, vol.45, Oct 1998, pp.1389-1407
[2] J.W. Bandler, A. Salama Fault diagnosis of analog circuits. Proc. of the IEEE, vol. 73,
August 1985, pp. 1279-1325.
[3] Jerzy Rutkowski. A dc approach for analog fault dictionary determination. EECTD
Davos, 1993.877-880.
[4] V.C. Prasad, N.S.C. Babu. Selection of test nodes for analog fault diagnosis in
dictionary approach. IEEE Trans. on IAM, vol.49, December 2000, pp. 1289-1297.
[5] W. Hochwald, J.D. Bastian. A DC approach for analog fault dictionary determination.
IEEE Trans. on CAS, vol.26, July 1979, pp. 523-529.
[6] P.M. Lin, Y.S. Elcherif. Computional Approaches to Fault Dictionary, Analog
Methods for c.a. Circuit analysis and diagnosis. Edition T.Ozawa, M. Dekker, New
York 1988, pp. 325-363.