65 nm technology for HEP:
status and perspectives
Pierpaolo Valerio on behalf of the
RD53 collaboration
2
Outline
•
•
•
•
•
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The push for a more downscaled technology
RD53 collaboration
New developments and challenges
A first prototype: CLICpix
Other projects
Conclusions
3
Outline
•
•
•
•
•
•
The push for a more downscaled technology
RD53 collaboration
New developments and challenges
A first prototype: CLICpix
Other projects
Conclusions
4
Facing new challenges
• Current LHC pixel detectors have clearly
demonstrated the feasibility and power
of pixel detectors for tracking in high
rate environments
• Phase 2 upgrades: ~16x hit rates, ~4x
better resolution, 10x trigger rates, 16x
radiation tolerance, increased forward
coverage, less material…
• Relies fully on significantly improved
performance from next generation pixel
chips
5
LHC-Phase 2 requirements
ATLAS and CMS phase 2 pixel upgrades very challenging
• Very high particle rates: 500MHz/cm2
▫
Hit rates: 1-2 GHz/cm2 (factor ~16 higher than current pixel
detectors)
• Smaller pixels: ~¼ (~50x50µm2 or 25x100µm2)
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Increased resolution
Improved two track separation (jets)
Outer layers can be larger pixels, using same pixel chip
• Increased readout rates: 100kHz -> ~1MHz
▫
Data rate: 10x trigger X >10x hit rate = >100x !
• Low mass -> Low power
Unprecedented hostile radiation: 1 Grad, 1016 Neu/cm2
• Phase 2 pixel will get in 1 year what we now get in 10 years
Pixel sensor(s) not yet determined
• Planar, 3D, Diamond, HV CMOS…
• Possibility of using different sensors in different layers
Complex, high rate and radiation hard pixel chips required
6
The need for a new technology
A more downscaled technology can help achieveing
the needs for future developments in HEP
• Higher density
• Lower power consumption
• Allows for faster and more complex designs
• Better suited for “mostly digital” designs
• Potentially better radiation hardness
Drawbacks include:
• Higher costs
• More complex development
7
Why 65 nm?
• Mature technology:
▫ Available since ~2007
• High density and low power
▫ High density vital for smaller pixels and ~100x increased
buffering during trigger latency
▫ Low power tech critical to maintain acceptable power for
higher pixel density and much higher data rates
• Long term availability
▫ Strong technology node used extensively for
industrial/automotive
• Design tool set, Shared MPW runs, Libraries, Design
exchange within HEP community
• Affordable (MPW availability, ~1M NRE for final chips)
• Significantly increased density, speed and complexity
compared to 130nm !
8
Transistor density per pixel area [transistors/µm2]
“Moore’s law” for pixel detectors
10
CLICpix (2013) – 65 nm
1
Timepix3 (2013)
Medipix3RX (2012)
Medipix2 (2002)
FEI4 (2011)
0.1
FEI3 (2003)
Medipix1 (1998)
Rad-Hard designs
0.01
0.7
0.6
0.5
0.4
0.3
CMOS process [µm]
PSI46 (2005)
0.2
0.1
0
9
Risks and issues to address
• Deep submicron technologies are not designed
primarily for analog designs.
▫ Lower power supply voltage  lower dynamic range
▫ Process spread and device mismatch is worse for
smaller devices
• Higher complexity in the design flow
▫ The design manual is twice the size of the one for 130
nm
• Radiation performances need to be studied
10
Outline
•
•
•
•
•
•
The push for a more downscaled technology
RD53 collaboration
New developments and challenges
A first prototype: CLICpix
Other projects
Conclusions
11
RD53: an ATLAS-CMS-LCD collaboration
• RD53 is a collaboration between ATLAS, CMS and LCD
to set the ground to develop next generation of pixel
readout chips
• RD53 was organized to tackle the extreme and diverse
challenges associated with the design of pixel readout
chips for the innermost layers of particle trackers at
future high energy physics experiments (LHC – phase II
upgrade of ATLAS and CMS, CLIC)
• 19 Institutes
▫ Bari, Bergamo-Pavia, Bonn, CERN, CPPM, Fermilab,
LBNL, LPNHE Paris, Milano, NIKHEF, New Mexico,
Padova, Perugia, Pisa, Prague IP/FNSPE-CTU, PSI, RAL,
Torino, UC Santa Cruz.
• ~100 collaborators
12
RD53 working groups
RD53 is split in six different working groups:
• Radiation Tolerance
• Simulation
• Analog
• Top level
• IP Blocks
• I/O interfaces
13
RD53 timescale
• 2014:
▫
▫
Release of CERN 65nm design kit. RD53 eagerly awaiting NDA issues to be resolved.
Detailed understanding of radiation effects in 65nm
 Radiation test of few alternative technologies.
 Spice models of transistors after radiation/annealing
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IP/FE block responsibilities defined and appearance of first FE and IP designs/prototypes
Simulation framework with realistic hit generation and auto-verification.
Alternative architectures defined and efforts to simulate and compare these defined
Common MPW submission 1: First versions of IP blocks and analog FEs
• 2015:
▫
▫
▫
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Common MPW submission 2: Near final versions of IP blocks and FEs.
Final versions of IP blocks and FEs: Tested prototypes, documentation, simulation, etc.
IO interface of pixel chip defined in detail
Global architecture defined and extensively simulated
Common MPW submission 3: Final IPs and FEs, Initial pixel array(s)
• 2016:
▫
▫
Common engineering run: Full sized pixel array chip.
Pixel chip tests, radiation tests, beam tests…
• 2017:
▫
Separate or common ATLAS – CMS final pixel chip submissions.
14
Outline
•
•
•
•
•
•
The push for a more downscaled technology
RD53 collaboration
New developments and challenges
A first prototype: CLICpix
Other projects
Conclusions
15
Radiation effects in 65 nm CMOS
Thick Shallow Trench Isolation
Thin (rad-hard) gate oxide
Oxide (~ 300 nm); radiationfor core devices, becomes
induced charge-buildup may
thicker (and rad-softer) for
turn on lateral parasitic
I/O transistors
transistors and affect electric
G
field in the channel)
D
S
Doping profile
along STI
sidewall is
critical; doping
increases with
CMOS scaling,
decreases in
I/O devices
STI
N+
N+
Pwell
Spacer dielectrics may be
radiation-sensitive
STI
P-substrate
Increasing sidewall doping makes a device less sensitive to
radiation (more difficult to form parasitic leakage paths)
15
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TID effects: NMOS devices
• After 1000 Mrad : KPN loss is between 20% and 40%
• The GM recovery at room temperature is very slow
• 100°C annealing : KPN loss decreases to reach a values between 25% and
8%
• The loss is still higher for narrower devices
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TID effects: PMOS devices
•
•
•
For high level of dose (1000 Mrad), KPP decrease reaches 100%
for 120 nm and 240nm devices
With annealing, devices recover the most part of GM loss
Wider devices recovers practically the pre-irradiation GM value
18
Low temperature measurements
-15°C
• T room:
▫
T room
M. Barbero et al, CCPM
The KPP decay reaches 80% and more for the narrowed devices (~100% for 120n & 240n)
• -15°C:
▫
the decrease was less pronounced for low T, 35% and less excepted the 120n (55%)
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Effect on digital structures
1E-6
1
Current
Frequency
0.95
Cross Section [cm2/bit]
Current and frequency normalized [%]
Bonacini, CERN
0.9
0.85
0.8
0.75
1E-7
1E-8
130 nm
1E-9
90 nm
0.7
65 nm
1E-10
0.65
0.0
0
2
4
6
Dose [rad]
8
10
12
x 10
• Ring oscillator 2014 test at
–25C
• For same sized inverter:
▫ -10% @200Mrad
▫ -35% @1Grad
5.0
10.0
15.0
20.0
25.0
30.0
LET [MeVcm2/mg]
8
• 65nm cross-section seems
to saturate at a value 3.4×
smaller than 130nm
• About proportional to 4×
area reduction
35.0
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New architectures
• The classical continuoustime analog processing
channel is a wellestablished solution for
pixel sensors in highenergy physics
• In an advanced CMOS
process, a synchronous
architecture may be a good
alternative, with selfcalibration and discretetime signal processing
features (correlated double
sampling, autozeroing)
clocked by the bunchcrossing cadence
Asynchronous Architecture
INFN-PV/BG
Synchronous comparator
INFN-TO
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Analog/Digital integration
GND
D
Quiet configuration logic
GNDA
VDDA
• A correct layout is crucial to avoid digital
interferences in the low-noise analog front-end
• Just as for digital
columns, digital cores can
be subdivided into
Quiet configuration logic
regions for hit and
latency memory sharing.
• Physical layout must be
optimized for badwidth,
clock distribution and
other constraints
VDD
D
Abder Mekkaoui, RD53
22
Required Bandwidth
M. Garcia-Sciveres,
Berkeley National Lab
The bandwidth and hit-rate are major challenges
• The estimation is 2 MHz trigger rate, which
leads to a BW of 8 Gbps/chip  too high
New readout architectures are needed:
• On-chip data compression
• On-chip clustering
• Reduced information for some layers
• Readout electronics with bandwidths
comparable to high-speed memory chips!
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Standard IP blocks
• A Working Group is dedicated to the
development of standard IP blocks
• Effort is going on in defining guidelines on how
to build, test, document and distribute IP blocks
• A common IP blocks repository will greatly
decrease development time for future projects
and will increase their success, by using blocks
which were already tested and validated
24
Outline
•
•
•
•
•
•
The push for a more downscaled technology
RD53 collaboration
New developments and challenges
A first prototype: CLICpix
Other projects
Conclusions
25
CLICpix
• CLICpix is a hybrid pixel detector to be used
as the CLIC vertex detector
• Main features:
small pixel pitch (25 μm),
Simultaneous TOA and TOT measurements
Power pulsing
Data compression
• A demonstrator of the CLICpix architecture
with an array of 64x64 pixels has been
submitted using a commercial 65 nm
technology and tested
• The technology used for the prototype has
been previously characterized and validated
for HEP use and radiation hard design*
3 mm
▫
▫
▫
▫
*S.
Bonacini, P. Valerio et al, Characterization of a commercial 65
nm CMOS technology for SLHC applications, Journal of
Instrumentation, 7(01):P01015–P01015, January 2012
1.85 mm
26
A simple block diagram
Analog part of
adjacent pixels
share biasing
lines. Digital
part is shared
between each
two adjacent
pixels
64x64 pixel matrix
Chip periphery
Data IN
Data
OUT
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Pixel architecture
Top pixel
TOT ASM
Input
CSA
Clk divider
TOA ASM
Threhsold
Polarity
HF
Vtest_pulse
4-bit Th.Adj
DAC
Configuration data:
Th.Adj, TpulseEnable,
CountingMode, Mask
4-bit TOA 4-bit TOT
counter
counter
Clock
Feedback
network
Bottom pixel
• The analog front-end shapes photocurrent pulses and compares
them to a fixed (configurable) threshold
• Digital circuits simultaneously measure Time-over-Threshold
and Time-of-Arrival of events and allow zero-compressed readout
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Pixel logic summary
Technology
65 nm (High-Vt Standard Cells),
Asynchronous State Machines
Pixel size
25x25 µm
25x14 µm (Analog)
25x11 µm (Digital)
Acquired Data
TOT and TOA
Counter Depth (LFSR)
4 bits TOT + 4 bits TOA (or
counting, for calibration)
Target Clock Speed
100 MHz (acquisition)
320 MHz (readout)
Data type
Full Frame
Zero compression (pixel, superpixel and column skipping)
Acquisition Type
Non-continuous
Power Saving
Clock gating (digital part), Power
gating (analog part)
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TOT measurements



TOT gain variation is 4.2% r.m.s.
Tested for nominal feedback current
Corners have lower TOT gain


TOT integral non-linearity for different
feedback currents was tested
TOT dynamic range matches simulations
30
Threhsold equalization
• Routines for
equalizing the
threshold using
the pixel
calibration DACs
were
implemented,
finding the noise
floor for all pixels
• Calibrated spread
is 0.89 mV
(about 22 eassuming a 10 fF
test capacitance)
across the whole
matrix
31
Radiation Testing
• The chip was irradiated up to 800 Mrads.
• Above 200Mrad, the chip gradually turned off, as
damaged switches used for biasing structures are
unable to let the nominal current pass (their driving
current becomes too low).
• All I/O interfaces and digital structures did not show
any significant degradation during irradiation, even
after the analog front-end stopped working
• The chips regained some functionality after two
week of annealing at room temperature (the total
power consuption went back to pre-rad value).
Analog performances of the measured chip were
found to be considerably degraded.
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Lessons learned
• Feasibility of high density pixel chips with
advanced features using 65 nm technology has
been proved
• Design flow using new software tools was
estabilished, smulation models have been
validated
• The main challenges include analog/digital
integration and design of high performances
analog structures
33
Outline
•
•
•
•
•
•
The push for a more downscaled technology
RD53 collaboration
New developments and challenges
A first prototype: CLICpix
Other projects
Conclusions
34
Other 65 nm projects
• MPA (Macro Pixel ASIC) - CERN
▫ Front-end to be used CMS tracker upgrades for
HL-LHC
▫ 100 x 1446 μm pixels
▫ Modules with local pT discrimination
• LpGBT - CERN
▫ Low-power/small-footprint version of GPT chip
• Gigabit transmitter for the BELLE-II pixel
detector – University of Bonn
35
Outline
•
•
•
•
•
•
The push for a more downscaled technology
RD53 collaboration
New developments and challenges
A first prototype: CLICpix
Other projects
Conclusions
36
Conclusions and next steps
• Design work has started in 65nm (FEs, IPs)
▫ The technology has been validated and it can help face the
challenges of a new generation of pixel detectors
▫ Functionality of this CMOS process has been proved in
CLICpix and it will be studied further in a number of new
chips being developed in the following months/years
• There is a strong effort to develop new projects using 65
nm from multiple collaborations and institutes
• Radiation performance is good compared to previous
technologies, but it has to be studied for extremely high
doses
• Work must be done to build IPs and research new
architectures which can take advantage of a more
downscaled process
37