Hazard-non-increasing gate-level optimization algorithms
David S. Kung
IBM T. J. Watson Research Center, Yorktown Heights, NY 10598
Abstract
This paper presents hazard-non-increasing optimization algorithms. These are optimizations on
gate-level logic without introduction of any further static and dynamic hazards. Proofs are given
for general theoretical results on hazard-non-increasing transformations which serve as the basis
for these algorithms. The algorithms in this paper substantially augment the set of proven hazardnon-increasing optimization techniques in the literature. These algorithms are useful for hazardfree implementations of asynchronous designs.
1 keywords
logic synthesis, multi-level optimization, hazards, asynchronous circuits
2
2 Introduction
The control and elimination of transient behaviors, such as hazards, in logic networks is paramount in ensuring the correct functioning of digital circuits. In synchronous designs the clocklatch combination masks the transient behavior of signals by sampling them at prescribed intervals. In asynchronous design styles, constraints on the state graph [1] or signal transition graph [2]
guarantee that the circuit is hazard-free at the functional level. Even if a design is hazard-free at
the functional level, hazards might resurface in the implementation unless proper care is taken.
A two-level gate implementation can be made hazard-free with respect to a set of transitions if
certain conditions are met [3]. During multi-level synthesis, the optimization algorithms must
be hazard-non-increasing, ie. they do not introduce any further hazards into the circuit. The set
of multi-level optimization algorithms which have been proven to be hazard-non-increasing can
be summarized by a theorem in Ref. [4]:
Theorem 1 Let E1 be an algebraic expression and suppose E2 is an algebraic expression gener-
ated from E1 by using only the generalized DeMorgan law, the associative law, factoring (but not
multiplying out) and transformations of the form A + AB ! A and A + AB ! A + B , then a circuit corresponding to E2 will have no combinational hazard not present in circuits corresponding
to E1.
Therefore Thm. 1 provided a guideline for the synthesis and optimization of multi-level hazardfree circuits [5]. However the set of proven hazard-non-increasing optimization algorithms is quite
limited. The purpose of this paper is to extend such a set by providing a general theoretical
framework to identify synthesis transformations which are hazard-non-increasing.
This paper is organized as follows: Multi-value algebras for hazard detection and their relevance
to hazard-non-increasing transformations are discussed. A succinct criterion for the hazard-nonincreasing property is presented based on a partial order on the extended logic values. Theoretical results on hazard-non-increasing transformations from which the algorithms are derived are
proved. Based on these theoretical results a subset of the standard optimization algorithms are
shown to be hazard-non-increasing. An extended transduction method is presented and shown to
be hazard-non-increasing. A hazard-free multi-level synthesis procedure is outlined and applied
to an example from the literature.
3
3 Hazard Detection
A Boolean network is combinational and consists of n input gates with one output pin and no
input pin, R internal gates with one output pin and some number of input pins and m output
gates with no output pin and one input pin. The output pin of every non-output gate vi is
connected to some input pins by a net si and the connection from vi to vj is denoted by cij .
cij is an input connection of vj and is an output connection of vi. Nets (connections) that are
connected to the output pin of an input gate are referred to as primary input nets (connections).
Nets (connections) that are connected to the input pin of an output gate are referred to as
primary output nets (connections). Each internal gate, vi, is associated with a Boolean function,
Bi : Bn 7! B where B = f0; 1g, of the inputs of vi and the output net is associated with a
Boolean function of the n primary inputs, v^iB. The rest of the nets and connections are internal.
Gates are assumed to be free of delays. The connections of the network carry a bounded delay
and multiple input changes in arbitrary order are allowed.
A Boolean vector is denoted by I B = (a1; :::; an) where ai 2 B. Don't care values are denoted
by 's. A transition vector is denoted by I1B ! I2B , where I1B = (a1; ::; ak; ak+1::; an) and I2B =
(b1; ::; bk; bk+1::; bn). A transition vector involving I B where f (I B ) = is irrelevant, otherwise the
transition vector is relevant.
A Boolean function, f B , contains a static hazard for the transition, I1B ! I2B , i f B (I1B ) =
f B (I2B ) and for some combinations of delays and order of input change f B goes through f B (I1B)
at least once during the transition. A Boolean function, f B , contains a dynamic hazard for the
transition, I1B ! I2B, i f B (I1B ) = f B (I2B) and for some combinations of delays and order of input
change f B goes through f B (I1B) and then f B (I1B) at least once during the transition.
The time-dependent behavior of a transition is captured by its waveform. A waveform (t)
is an ordered pair (f (t); [t0; t1]) where t0; t1 2 < and f (t) : < 7! B is a time-dependent Boolean
function with the condition that f (t) = f (t0); 8t t0 and f (t) = f (t1); 8t t1. In the
following, we will take the liberty of referring to a waveform and its function interchangeably.
The waveforms are classied in terms of their hazards as follows. A waveform can either be
static, ie. f (t0) = f (t1), or dynamic, ie. f (t0) 6= f (t1). A static waveform can either be static-1,
ie. f (t0) = 1 or static-0, ie. f (t0) = 0. A static-1 waveform is of type 1 (always at 1) i
f (t) = 1; 8t 2 [t0; t1], otherwise it is of type S1 (static-1 hazard). A static-0 waveform is of
4
Value
Waveform
Description
1
always at 1
0
always at 0
0 to 1 transition
1 to 0 transition
S0
...
static 0 to 0 hazard
...
static 1 to 1 hazard
S1
D+
...
...
dynamic 0 to 1 hazard
D−
dynamic 1 to 0 hazard
*
any value at all
Figure 1: Waveform of the 9 values
type 0 (always at 0) i f (t) = 0; 8t 2 [t0; t1], otherwise it is of type S0 (static-0 hazard). A
dynamic waveform can either be dynamic-rising, f (t0) = 0 and f (t1) = 1, or dynamic-falling,
f (t0) = 1 and f (t1) = 0. A dynamic-rising waveform is of type D+ (dynamic 0-1 hazard) i
9t0 and t00, such that t0 < t0 < t00 < t1, f (t0) = 1 and f (t00) = 0, otherwise it is of type "
(0-1 transition). A dynamic-falling waveform is of type D- (dynamic 1-0 hazard) i 9t0 and t00,
such that t0 < t0 < t00 < t1, f (t0) = 0 and f (t00) = 1, otherwise it is of type # (1-0 transition).
All possible waveforms can be classied into one of these 8 types plus a don't care type * as
depicted in Fig. 1. An example of two dierent waveforms of the same type (D+) is shown in
Fig. 2. An equivalence relation, , on the set of signal waveforms is dened as follows: 1(t) 2(t) i both signal waveforms are of the same type. Reexitivity, symmetry and transitivity
are immediate, hence the set of all possible waveforms is partitioned into 9 equivalence classes.
Given two input waveform vectors, I1(t) = (1(t); ::; n(t)) and I2(t) = (1(t); ::; n(t)), I1(t) I2(t) i i(t) i(t), 8i 1 i n. Given an input waveform vector, I (t), the output waveform
of a Boolean function f B is f B (I (t)), which also belongs to one of the 9 equivalence classes.
5
t1
t0
Figure 2: Waveforms in the equivalence class +
D
These concepts can be formalized by associating a logic value with each of the 9 equivalence
classes as shown in Fig. 1 and imposing a partial ordering on the logic values. The partial
ordering > is dened as follows: all logic values are not comparable except for the orderings :
> 0, > 1, >#, >", > S 0, > S 1, > D,, > D+, S 0 > 0, S 1 > 1, D+ >" and
D, >#.
Lemma 1 Let 1(t) and 2(t) be 2 signal waveforms such that 1(t0) = 2(t0) and 1(t1) =
2(t1). Let li be the logic value associated with the equivalence class i(t) for 1 i 2. Then
either l1 l2 or l2 l1.
Proof: Follows straightforwardly from the denition of the logic values and the denition of the
partial ordering. Q:E :D:
Corollary 1 Suppose I1(t) I2(t). Let f B (Ii(t)) be in the equivalence class with logic value li
for 1 i 2. Then either l1 l2 or l2 l1.
6
Proof: I1(t) I2(t) implies I1(t0) = I2(t0) and I1(t1) = I2(t1). Let i(t) be the output waveform
of f B given input waveform vector Ii(t), for 1 i 2. 1(t0) = 2(t0) and 1(t1) = 2(t1). The
corollary follows immediately from lemma 1. Q:E :D:
Corollary 1 allows a 9-value extension of a Boolean function f B to be determined by its
Boolean truth table in a consistent way. Let the set of extended logic value be denoted by
E = f0; 1; "; #; S 0; S 1; D+; D,; g. An extended function, f : E n 7! E , is the 9-valued extension
associated with a Boolean function f B . The 9-valued truth table for an extended function f is
dened as follows. Given a 9-value input vector I , let S be the set of input waveform vectors,
fIj (t)g, in the equivalence class that corresponds to I . The set of output waveforms over S is
partitioned into equivalence classes, Fi. Let the logic value associated with Fi. be li. The output
value of the 9-value extension is given by f (I ) = maxi(flig). By denition the set of extended
functions is a subset of the set of all possible 9-valued functions. An input transition vector is
now represented by a 9-valued input vector.
As an example, consider the Boolean function f B = NOR(v; w) and the transition (0; 1) !
(1; 0) which is represented by the 9-valued input vector I = ("; #). Let S be the set of output
waveforms of f B over all the input waveforms in the equivalence class associated with I . S is
partitioned by into two equivalence classes, 0 and S 0. A representative output waveform from
each equivalence class is displayed in Fig. 3. Since S 0 > 0, f (I ) = S 0 and the transition contains
a static 0 hazard. The complete 9-valued truth table for the extended 2-input NOR is displayed
in Table 1.
The values 0 and 1 are the Boolean values and the rest are transient values. An input vector
which contains Boolean values only is a Boolean input vector, otherwise it is a transient input
vector. f is a Boolean compatible extension of g i f (I ) = g(I ) whenever I is a Boolean input
vector in the Boolean care set of g. If I represents an irrelevant transition f (I ) = . If the
value of an extended function is neither Boolean nor don't care then the input vector must be
transient. An extended network is a the same as an Boolean network except that extended
functions are associated with each internal gate and its output signal. A primary output of
an extended network contains a hazard for an input transition vector if there exists an input
waveform vector and a combination of connection delays in the network such that the output
waveform belongs to the equivalence class associated with the hazard. The 9-valued truth table
7
v(t)
v(t)
w(t)
w(t)
NOR(v(t),w(t))
NOR(v(t),w(t))
t
0
t
t
1
Figure 3: Waveform of
t
0
(
N OR v; w
1
)
for the extended function f of an output of an extended network is dened as follows. Given a
9-value input vector I , let S be the set of input waveform vectors, fIj (t)g, in the equivalence class
that corresponds to I . The set of output waveforms over S due to all combinations of connection
delay characteristics is partitioned into equivalence classes, Fi. Let the logic value associated
with Fi. be li. The output value of the 9-value extension is given by f (I ) = maxi(flig). This
is equivalent to a gate-wise incremental evaluation of the extended network because the delay
characteristics of every connection is independent from one another. Detection of dynamic and
static hazards in networks can be encapsulated by the following result in Ref. [6]:
Let f be the extended function at an output of an extended network. Let the transition, I1 7! I2, be represented by a 9-valued input I 0. The output contains a a hazard
of the specied type for I 0 i f (I 0) equals S 0, S 1, D+ or D,.
If only static hazards are considered, the transient values ", #, S 0, S 1, D+ and D, can be
collapsed into just one logic value, l, which represents transient behavior in general. A detailed
discussion of the logic value l is contained in Ref. [7]. The following theorem [7] shows that a
8
NOR 1
1
0
0
0
" 0
# 0
S1 0
S0 0
D+ 0
D, 0
0
0
0
1
#
"
S0
S1
D,
D+
"
# S 1 S 0 D+ D, #
#
"
0
S0
S0
D,
D,
S0
0
0
S0
S0
S0
S0
S0
S0
S0
S0
S0
"
S0
D+
S0
D+
0
S1
D,
D+
S0
S1
D,
D+
Table 1: 9-valued truth table for
0
D,
D,
S0
S0
D,
D,
S0
0
D+
S0
D+
S0
D+
S0
D+
0
S0
N OR
4-valued algebra suces for static hazard detection.
Theorem 2 Let I 0 = (t1; ::; tk; ak+1; ::; an), where ti =l, be the transient input vector which
corresponds to the transition I1 ! I2. A static hazard is possible i f (I 0) =l.
The 4-valued algebra can only give necessary condition for dynamic hazards: If the transition,
I1 ! I2, contains a dynamic hazard, then f (I 0) =l.
4 Hazard-non-increasing Extensions
f is a hazard-non-increasing extension of g i
1. f is a Boolean compatible extension of g.
2. If a relevant transition causes a hazard in f , it causes a hazard in g.
In particular, a hazard-non-increasing extension of a hazard-free function preserves the functionality as well as the hazard-free property. f is a hazard-preserving extension of g i f is a
hazard-non-increasing extension of g and g is a hazard-non-increasing extension of f .
To formalize these concepts, the following denitions are presented. I1 = (a1; :::; an) I2 =
(b1; :::; bn) i ai bi 8i. A function is monotone-non-decreasing i I1 I2 implies f (I1) f (I2).
9
Lemma 2 An extended function f is monotone-non-decreasing with respect to the 9-valued algebra and the 4-valued algebra.
Proof: Let I1 = (a1; ::; ak,1; ak ; ak+1::; an) and I2 = (a1; ::; ak,1; bk; ak+1::; an) such that bk > ak
so I2 I1. If f (I1) = then by the partial ordering f (I2) = . If f (I1) does not contain
any hazard then by the partial order f (I1) f (I2). Therefore only the case in which f (I1)
contains a hazard requires further consideration. Suppose (t) is a representative waveform in the
equivalence class f1(I ) and I (t) = (1(t); ::; n(t)) is the corresponding input waveform vector.
Let k(t) be a representative waveform in the equivalence class bk . The partial order requires
that k (t0) = k (t0) and k (t1) = k (t1). Let t0 be the time by which all the hazards (if any) of
f (I1) have occurred, ie., (t) = (t1) 8t t0. Then the waveform of k(t) is chosen as follows:
k (t) = k (t) t0 t t0 and the rest of the hazards of k(t) occurs after t0. By this construction
f (J ) is in the equivalence class of (t) where J = (1(t); ::; k,1(t); k(t); k+1(t); ::; n(t)),
therefore f (I2) = f (I1). The case in which I1 and I2 dier in more than one input follows easily
by induction. The case for the 4-valued algebra follows straightforwardly. Q:E :D:
Theorem 3 An extended function associated with a primary output net of an extended network
is monotone-non-decreasing with respect to the 9-valued algebra and the 4-valued algebra.
Proof: The theorem follows from lemma 2 and the fact that a montone-non-decreasing function
of montone-non-decreasing functions is montone-non-decreasing. Q:E :D:
The partial order allows a succinct criterion for the hazard-non-increasing property as described
in the following theorem.
Theorem 4 g is a hazard-non-increasing extension of f i g(I ) f (I ); 8I .
Proof: Suppose g(I ) f (I ); 8I . When I is in the Boolean care set, the values of f 0 or 1, hence
g(I ) = f (I ) must hold, since 0 and 1 are not comparable with each other and there are no logic
values less than 0 or 1. Hence g is a Boolean compatible extension of f . When the values of f is
not Boolean and not , either g = f or the value of g could be one of the 4 values 0, 1, +, and
,. Therefore no new hazards are introduced. Suppose it is false that g(I ) f (I ); 8I , then there
must be some I such that g(I ) > f (I ). If g is not a Boolean compatible extension of f , then g
is not a hazard-non-increasing extension of f . If g is a Boolean compatible extension of f , then
10
g(I ) > f (I ) can hold only for transient input vectors. The only possible values for (f (I ); g(I ))
are (0; S 0), (1; S 1), (+; D+) and (,; D,). In all 4 cases g(I ) contains a hazard while f (I ) does
not, therefore g is not a hazard-non-increasing extension of f . Q:E :D:
Theorem 5 Let C1 be a Boolean network which consists of one internal gate and primary input
signals with single fanout and C2 be a dierent single output Boolean network which represents
the same Boolean function as that of C1. Let f1 and f2 be the extended functions at the output
of C1 and C2 respectively. f1 is a hazard-non-increasing extension of f2 .
Proof: f1 is by denition a Boolean compatible extension of f2. Let the primary input signals in
C2 with multiple fanouts be denoted by si, 1 i p. For any input vector I let Si be the set
of waveforms at the output of Ci, for 1 i 2. Suppose (t) 2 S1 and the corresponding input
waveform is I (t). Let the connection delay characteristics in C2 be such that every connection
from the primary input gate, vi, have the same delay characteristics as si in C1 for 1 i p,
and that all internal connections have zero delay. f2(I (t)) = (t) therefore (t) 2 S2. Hence
S1 S2 which implies f1(I ) f2(I ). f1 is a hazard-non-increasing extension of f2 by Thm. 4.
Q:E :D:
A stronger theorem can be proved if C2 is restricted to a tree decomposition.
Theorem 6 Let C1 be a Boolean network which consists of one internal gate and primary input
signals with single fanout and C2 be any multi-level tree decomposition of C1 . Let f1 and f2 be the
extended functions at the outputs of C1 and C2 respectively. f1 is a hazard-preserving extension
of f2 .
Proof: f1 is obviously a Boolean compatible extension of f2 and vice versa. Consider the special case in which C2 is a two-level tree decomposition of C1 : v1 = g(x1; :::; xk; v2), v2 =
h(xk+1; :::; xn). For any input vector I let Si be the set of waveforms at the output of Ci, for
1 i 2. Suppose (t) 2 S1 and the corresponding input waveform vectoris (1(t); ::; n(t)).
By setting the delay of the connection c12 to zero, (t) = f2(I (t)) therefore (t) 2 S2. Hence
f1 is a hazard-non-increasing extension of f2. Suppose (t) 2 S2 and the corresponding input
waveform vector is I (t). Let the waveform vector at the input pin to gate v1 of signal s2 be (t).
Let (1(t); ::; n,k(t)) be the input waveform vector to the gate v2 such that the waveform at
the output pin of v2 is (t). Then f1(J (t)) = (t) for J (t) = (1(t); ::; k(t); 1(t); ::; n,k(t)).
11
Therefore (t) 2 S1 which implies f2 is a hazard-non-increasing extension of f1. The multi-level
case follows straightforwardly by induction. Q:E :D:
It is worth noting that Thm. 1 is a direct consequence of Thm. 5 and Thm. 6.
5 Hazard-non-increasing transformations
A hazard-non-increasing transformation is a logic transformation with the following property:
Let ^k and #^k be the functions at the kth primary output of an m-output Boolean network before
and after application of the hazard-non-increasing transformation, then ^k must be a hazard-nonincreasing extension of #^k for 1 k m. In this section, hazard-non-increasing transformations
which are derived from the theoretical results of section 4 are discussed.
Theorem 7 The transformation of removing an internal connection cij and replacing it with ckj
where v^k v^i is a hazard-non-increasing transformation.
Proof: Let ^k and #^k be the functions at the kth primary output of the Boolean network before
and after application of the hazard-non-increasing transformation. By Thm. 3 ^k #^k for
1 k m. The theorem immediately follows from Thm. 4. Q:E :D:
Redundancy removal in general is not hazard-non-increasing because it might remove some of
the hazard suppressing redundant covers. The criterion for disconnecting internal connections
in a Boolean network that consists of only NOR gates is given by the following theorem. The
criterion for NAND, AND and OR primitives can be similarly derived.
Theorem 8 Let fE; F g be a partition of the set of immediate predecessors of an internal NOR
W
W
gate vk . If v^k (I ) = 0 implies v2F v^(I ) = 1 where is the n-ary OR operation, the transformation
of removing the connections from the gates in E to vk is hazard-non-increasing.
Proof: Let the extended function associated with sk (the output net of vk) after disconnection be
gk . The input connections from the gates in E to vk are S-redundant [8] so gk is a Boolean compatible extension of v^k. If gk (I ) contains a hazard then Wv2F v^(I ) 6= 1. In this case Wv2E v^(I ) 6= 1
since otherwise v^k (I ) = 0, which implies Wv2F v^(I ) = 1. Therefore the the inputs in E must either be 0 or contain a hazard and cannot suppress the hazard caused by the inputs in F . Hence
12
v^k contains the same hazard which implies that gk is a hazard-non-increasing extension of v^k.
By Thm. 4, gk vk and the theorem follows from Thm. 7. Q:E :D:
Transformations in which connections are added to the network such that the Boolean functionality of the primary outputs are preserved are not hazard-non-increasing in general. Concrete
examples are provided in the next section as illustrations.
6 Hazard-non-increasing optimization algorithms
In this section, the set of standard optimization algorithms which do not introduce any extra
static nor dynamic hazards are identied based on the theoretical results of the previous sections.
An extended transduction method is presented and is shown to be hazard-non-increasing.
The following is a list of hazard-non-increasing optimization techniques:
1. Dual global ow [9] is hazard-non-increasing due to Thm. 5 and Thm. 7.
2. Tree decomposition of a gate is hazard-non-increasing due to Thm. 6 and Thm. 7.
3. Gate replication is hazard-non-increasing due to Thm. 7.
4. The COLLAPSE operation a la MIS [10] is hazard-non-increasing due to Thm. 5 and
Thm. 7.
5. Kernel-factoring and cube-factoring are hazard-non-increasing due to Thm. 1 and Thm. 7.
Further Boolean optimization algorithms which are hazard-non-increasing can be obtained via
an extended transduction method. As in Ref. [8], given a compatible set of extended permissible
function CSEPF (GC (vj )) at the output of a NOR gate vj , the CSEPF of an input connection
cij is given by
_
GC (cij ) = GC (vj )2 v^(I )
v2P
where P is the set of predecessor nodes of vj minus vi. The CSEPF of a node vk is in turn given by
the intersection of the CSEPF of the output connections of vk . The 2 operator is dened by the
9-valued truth table in Table 2. Empty entries represent congurations that cannot be logically
realized. The CSEPF of a primary output is just the Boolean function of the primary output with
external don't cares included. The CSEPF of every node is computed via a breadth rst traversal
13
W
2
1
0
GI (vk)
"
#
*
S1
S0
D+
D-
1
*
0
0
1
#
"
"
1
0,"
*
v2P
#
v^(I )
1
0,#
* S1
S0
D+
D-
1
1
1
1
1
*
*
* *
*
*
*
S0
0,S0
S1 #,S1,D- ",S1,D+
0,S1 S1
#,S1,D- ",S1,D+
DS0,D#,D0,#,S0,DD+ S0,D+
",D+ 0,",D+,S0
Table 2: 9-valued truth table for the 2 operator
from primary outputs to primary inputs. A CSEPF is hazard-non-increasing i replacing the
function of a node by an element of its CSEPF is a hazard-non-increasing transformation.
Theorem 9 The CSEPF dened by Table 2 for NOR networks is hazard-non-increasing.
Proof: Replacing the function of a primary output node by an element of its CSEPF is by
denition hazard-non-increasing. Replacing the function of a non primary output node by an
element of its CSEPF does not introduce any hazard into its sink nodes, according to Table 2.
Q:E :D:
In spite of this desirable property, the computation of the CSEPF for the 9-valued algebra is
very expensive and thus impractical, at least for circuits in which all primary input transitions
are possible. However, for a class of asynchronous design, namely burst-mode machines [1], in
which the set of allowed primary input transitions is very small, for example a few thousand,
relative to the total number of possible transitions. In such a case, the computation of CSEPF's
is tractable by exhaustive simulation of the allowed primary input transitions.
Some conventional optimization algorithms which are not hazard-non-increasing are illustrated
by the following example. Consider the network in Fig. 4 where the inputs are ordered according
to the quadruple (a; b; c; d). s = 1 implies f = 0 therefore according to the global ow algorithm,
the dashed connection can be made without aecting the functionality of f . The same conclusion
14
Figure 4: A hazard increasing transformation
can be drawn by using the standard transduction algorithm. Let the extended function of the
primary output be g and h for the network with and without the dashed connection. For the input
vector I = ("; "; 0; 1), g(I ) = D, > h(I ) =#. Hence this transformation is hazard-increasing
with respect to I . This example shows that both global ow and the standard transduction are
not hazard-non-increasing transformations.
7 Hazard-Free Synthesis
A multi-level synthesis procedure is outlined for a hazard-free implementation of the combinational logic of the self-timed state machine in Ref. [1]. There, the state variables are controlled
by a local clock but the combinational logic is made hazard-free by restricting the set of possible
input transitions through the state graph. Nowick and Dill presented algorithms to guarantee
that the two-level combinational logic is free from any static and dynamic hazards.
Multi-level synthesis begins by applying kernel factoring. Dual global ow can be applied
15
without change and the extended transduction transformations can be invoked to tie up the
loose ends. The next stage, technology mapping, is a more dicult issue. A detailed knowledge
at the transistor-level is required to understand the transient properties of the technology cells.
For the basic technology cells such as NAND, NOR, AND and OR, it might be justiable to
assume their transient properties is accurately modeled by the corresponding extended function.
Then by Thm. 5, technology mapping to these basic gates is hazard-non-increasing. If the
transient property of a technology cell can be modelled by an extended network, Thm. 4 can be
used to decide whether the mapping transformation is hazard-non-increasing or not.
This multi-level synthesis procedure is applied to the 5-input 3-output combinational logic of
the HP controller in ref. [1]. The sum of product representation of the combinational outputs of
the model is:
peack = y1 y0 ackpkt + y1 y0 treq + y1 y0 rdiq adbldout +
y1 adbldout ackpkt treq + y0 adbldout ackpkt treq;
tack = y1 y0 + y0 treq rdiq + y1 ackpkt + y1 treq + y0 ackpkt +
y0 treq rdiq + adbldout ackpkt treq
adbld = y1 y0 rdiq + y1 adbldout treq rdiq +
y1 adbldout reqsend treq rdiq:
Dual global ow and kernel-factoring reduce the literal count by 18 percent over the result
obtained by optimizations restricted to those in Thm. 1. For more complex networks, the gain
should be substantially better.
8 Summary and Conclusions
In this paper, general theoretical results which identify hazard-non-increasing transformations are
presented. Most of the theorems apply to Boolean networks which contain gates with arbitrary
function. A set of standard optimization algorithms is shown to be hazard-non-increasing. An
extended transduction method is introduced and shown to be hazard-non-increasing. These
results substantially enhance the arsenal of hazard-non-increasing optimization algorithms.
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Acknowledgements
The author would like to thank Daniel Brand for useful conversations and Louise Trevillyan and
Robert Damiano for reading the manuscript.
References
[1] S. M. Nowick and D. L. Dill, \Automatic synthesis of locally-clocked asynchronous state
machines," in Proceedings of the ICCAD, pp. 318{321, 1991.
[2] T. A. Chu, \Synthesis of self-timed control circuits from graphs: An example," in Proceedings
of the ICCD, pp. 565{571, 1986.
[3] S. M. Nowick and B. Coates, \Uclock: Automated design of high-performance unclocked
state machines," in Proceedings of the ICCD, pp. 434{441, 1994.
[4] S. H. Unger, Asynchronous Sequential Switching Circuits. Wiley Interscience, 1969.
[5] L. Lavagno, K. Keutzer, and A. Sangiovanni-Vincentelli, \Synthesis of veriably hazardfree asynchronous control circuits," in Advanced research in VLSI 1991: U C Santa Cruz,
pp. 87{102, 1991.
[6] G. Fantauzzi, \An algebraic model for the analysis of logic circuits," IEEE transactions on
Computers, vol. C-23, pp. 576{581, 1974.
[7] E. B. Eichelberger, \Hazard detection in combinational and sequential switching circuits,"
IBM Jouranl of Research and Development, pp. 90{99, 1981.
[8] Y. Muroga, S.and Kambayashi, H. C. Lai, and J. N. Culliney, \The transduction method design of logic networks based on permissible functions," IEEE transactions on Computers,
vol. C-38, pp. 1404{1424, 1989.
[9] L. Berman and R. F. Damiano, \Dual global ow," in Proceedings of the International
Workshop on Logic Synthesis, 1991.
17
[10] R. Brayton, R. Rudell, A. Sangiovanni-Vincentelli, and A. Wang, \MIS: A multiple-level
logic optimization system," IEEE Transactions on Computer-Aided Design, vol. CAD-6,
November 1987.
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