STATUS OF DHPT 1.0
PXD/SVD Workshop
Tomasz Hemperek,
5 th February 2013
DHP – Data Handling Processor
DCDB
(256 analog inputs)
JTAG
DAC/
ADC
DESERIALIZER
DESERIALIZER
COMMON MODE CORRECTION
MEMORY
MEMORY
MEMORY
MEMORY
MEMORY
MEMORY
MEMORY
MEMORY
ZERO SUPPRESSION
I/O
PAIRING
READ + FIFO
PLL
OUTPUT FRAMING
SER/TX
CONTROL
RX
Current Prototype: DHP 0.2 – IBM 90nm
• Area 12.5 mm2
• >1Mbit SRAM memory
• >200k gates
• 155 I/O pads (CMOS and LVDS)
• 1.6 Gbit/s output link
• JTAG configuration
• 11 DACS
• 10 bit ADC
• Temperature sensor
DHPT 1.0
TSMC 65nm
2
DHPT 1.0 Planner
http://bit.ly/DHPT10Planner
3
Run Modes
• Trigger On
• Trigger Off
Controls readout
• Veto
Starts Gated Mode sequence
• Run
• Stop
Standard operation mode
• Data Dump
Raw data transfer
Trigger line is not anymore level sensitive!
Commands are Manchester coded (4bit) send on trigger line.
4
New Sequencer
• 2 memories for run mode and gated mode
• Gated mode started be trigger command (at given row) stopped after
programmable time
• All switcher signals can be adjusted individually bit by bit (3.125ns)
• Memory protected by Hamming code, refreshed every frame
switcher gate
switcher clear
switcher data
switcher clock
256 rows
run mode memory
4x32 columns
5
gated mode memory
Memory organization – raw data & pedestals
•
•
•
Overall memory size: 3 frames (1x data + 2x pedestal)
Double buffer for pedestals:
• one is active
• one gets updated in the background (JTAG)
• Toggle memories once update is finished
Memory protected by Hamming code
DHP 0.2
16x1024x32 (2 frames)
6
MEMORY
MEMORY
MEMORY
MEMORY
MEMORY
MEMORY
MEMORY
MEMORY
MEMORY
MEMORY
MEMORY
MEMORY
MEMORY
MEMORY
MEMORY
MEMORY
DHPT 1.0
4x1536x128 (3 frames)
MEMORY
MEMORY
MEMORY
MEMORY
Other
Improve DCD clock transmission (320 MHz on single ended line)
• It is possible to send differential clock to DCD by keeping
backward compatibility
• Use of synchro output on DCD (currently unused)
• Alternative: single ended low swing clock input od DCD
Increase of FIFO depth
Anything else?  Have a dedicated meeting for discussion on
DHPT1.0 changes/improvements
7
Plan
February
Digital Design
Verification
Implementation
Analog Designs
Sign-off
8
March
April
Questions?
9