EX 5 DIGITAL ELECTRONICS (classes 1BM1 – 1BT4)
G________
After completing the task and studying Units 2.1, 2.2, 2.3, 2.4 and 2.5, you will be able to (tick all that apply):
 Explain the concept of memory in digital systems and why we talk about sequential systems for introducing the time
variable. What is the meaning of storing or saving a bit of information?
 Explain the concept of a state in a sequential system
 Describe the characteristics of basic asynchronous 1-bit memory cells or latches SR and D, using function table and
state and timing diagrams
 Describe the characteristics of basic synchronous 1-bit memory cells or flip-flops JK, D, and T, using function table and
state and timing diagrams
 Analyse simple circuits based on latches or flip flops using timing diagrams.
 Design 2-state latches and flip-flops using the direct method based on the techniques in Chapter 1
 Design timer and clock circuits based on the 555/74LS121/122/123 integrated circuits
 Design simple synchronous systems or finite state machines (FSM) using the canonical method
 Produce a written solution for the exercise using the instructions from:
http://epsc.upc.edu/projectes/ed/unitats/unitat_1_1/Criteris_Correccio_Exercici.pdf
 Work cooperatively in a team of 3 members using the method described in:
http://epsc.upc.edu/projectes/ed/problemes/metode_resolucio_cooperativa_recomanat.pdf
Write down the most significant questions you have had while or after completing the task:
STATEMENT:
My signature below indicates that I have (1) made equitable contribution to EX 5 as a member of the group, (2) read
and fully agree with the contents (i.e., results, conclusions, analyses, simulations) of this document, and (3)
acknowledged by name anyone outside this group who assisted this learning team or any individual member in the
completion of this document.
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Today’s date: __________________
Active members
Roles: (reporter, simulator, etc.)
(1) ___________________________
_______________
(2) ___________________________
_______________
(3) ___________________________
_______________
Acknowledgement of individual(s) who assisted this group in completing this document:
(1) _______________________
(2) _______________________
Study time
(in hours)
Group work
Sessions TGA,
TGB
Individual
Student 1
Student 2
Student 3
2
Sessions
TGC
A typical sequential system to control a DC motor
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We want to design a control system to turn ON or OFF a motor like the one represented in Fig. 3. The system has
to correspond to a canonical synchronous finite state machine (FSM) like the ones studied in Unit 2.5. Verify your
design in Proteus-ISIS downloading the initial project file from the ED web page and drawing your own
schematics inside the ON-OFF-CONTROL subsystem sheet.
VCC
MOTOR CONTROL SYSTEM
D4
RL1
1N4148
4V
B1
RUN/STOP
VCC
48V
B_L
R2
EMERGENCY
Z
Q1
R1
BC547
10k
DC-MOTOR
1k
E_L
48V
D1
GND
ON-OFF-CONTROL
GND
Fig. 1 Electrical schematic of the control system to drive a high power motor load. For
security reasons, the run/stop button must be pressed twice to set the motor ON.
The FSM canonical method design flow:
a) Specifications: function table, state diagram and an example of timing diagram.
Emergency
Run/Stop
Z
Function
1
X
0
Emergency stop
0
Two consecutive clicks in less than 15 s
1
Run (ON)
0
Next click
0
Stop (OFF)
b) Draw and match the FSM’s general architecture to the given problem
c) Code states in any valid or convenient coding system
a. Using binary
b. Using Gray
c. Using one-shot
d) Design using anyone of the Chapter 1 methods the combinational circuit CC2 to determine the outputs
a. Method of decoders
b. Method of multiplexers
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c. Set of gates NOT-AND-OR, NOT-OR-AND, or using only NOR or only NAND
e) Draw the state register circuit using a given flip flop type:
a. JK flip flops
b. D flip flops
c. T flip flops
f)
Design the combinational circuit CC1 to determine the future state. Use the state transition table and the
FF design table, to obtain the future state functions.
g) Verify your design in Proteus-ISIS downloading the initial project file from the ED web page and filling it
with your own design.
h) (demonstration) Write the VHDL code for the problem, and synthesise it in a sPLD GAL22V10. Run a
Proteus simulation to demonstrate how it works.
i)
(demonstration) Design an alternative control system with the same specifications using an commercial
microcontroller PIC16F84 or PIC16F627A and verify it using Proteus-VSM
Real time issues...
Deactivate the start sequence in case of the two consecutives clicks are not pressed before 15s
2
Enhance the basic hardware and the FSM state diagram with an analogue timer based on the classic 555
integrated circuit. Its mission will be to reset the system in case of the two consecutives clicks were not pressed
before 15s.
VCC
555 Timer delay = K · Rx · Cx
CHIP 555 constant K = 1.1
U1
8
a. Following the explanations in the didactical Unit 2.4,
analyse the circuit shown in Fig. 2. Deduce the
waveforms and the design equation which gives
R1
10k
4
R
VCC
R2
Q
DC
5
CV
TR
TH
1
2
TRIGGER
b. Connect the timer module to the motor system
using logic circuitry if necessary. The idea is to reset
the system if there is no second click before 15 s.
4
7
C1
GND
+
T0 = f(R1, C1)
3
Fig. 2 A 555-based timer
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555
?
Activating the motor for a limited time
3
Design a timer to connect to the previous control system using the classic 555 integrated circuit. Its mission will
be to keep the motor ON for only 12 s after having started the ON state.
Let’s continue controlling a deadbolt via a numeric keypad
This is a little enhancement of the previous problem. A numeric pad will be used to input data instead of a single
push button. Thus, you will appreciate the changes in hardware and FSM programming (state diagram).
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Search the web or the library to read about automated locks like the one presented in this problem. For
instance, start at: http://www.nokey.com/. Find out some common features for this kind of products and draw a
block diagram for a keyless lock.
5
Design a synchronous sequential system (FSM) by the canonical method to produce an OPEN/CLOSE control
signal for a deadbolt as shown in Fig. 3. The hidden code to open the door is ‘5#2’1.
The FSM canonical method design flow:
a) Specifications: Electrical schematic, function table, state diagram, timing diagram.
Keypad input
Output Z
sequence
5
Door closed
#
(# after a 5)
2
(2 after # after 5) Door opened (Z = 1)
Other
Door closed
Door closed
b) Draw and match the FSM general architecture to the given problem
c) Coding states in Gray
d) Design of the combinational system using the method of multiplexers with a MUX2
e) Draw the state register circuit using D-type flip flops.
f)
Design the combinational circuit CC1 to determine the future state. Use the state transition table and the
FF design table, to obtain the future state functions.
g) Verify your design in Proteus-ISIS downloading the initial project file from the ED web page and filling it
with your own design.
1
English language note: in Ireland, the UK, Australia, India and New Zealand, "hash key" refers to the # button on touch-tone
telephones, while in North America # is called the “number sign” (http://en.wikipedia.org).
5
0
4
8
K_L0
K_L4
K_L8
1
5
9
2
6
K_L1
K_L2
K_L5
K_L6
*
K_L9
3
7
#
K_L10
K_L3
VCC
K_L7
K_L11
DEADLOCK CONTROL
D4
RELAY
1N4148
4V
B1
VCC
KEY_ENCODER
ACTUATOR
K_L[11..0]
COD[3..0]
K_L[11..0]
120V
GS
R2
C[3..0]
Z
Q1
R1
BC547
12k
120V
1k
GS
D1
GND
ON-OFF-CONTROL
ENCODER
RA
100MEG
Fig. 3 Schematic for the proposed contr system to drive a signal for the deadbolt. (Image source: Ted Carmely, “Using Finite state machines to
design software”, Embedded Systems design magazine, vol. 22, num. 4, April 2009, http://www.nxtbook.com/nxtbooks/cmp/esd0409/#/18)
Other convenient enhancements...
Controlling the deadbolt by means of a remote control
Search information about how an infrared remote control2 can be interfaced with the previously designed
deadbolt activation system. Use your imagination, ask for information, surf the web, and discuss with your
colleagues.
6
Cells for storing bits.....the basic brick of any sequential system and
everything in electronics!
Find the datasheets and represent the entity of the classic chips in TTL-LS and CMOS technology which
correspond to:
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a. RS latch
b. D transparent latch
c. JK flip flop
d. D flip flop
2
http://www.infraredremote.com/8-14keys.htm
6
8
Deduce the output Q for the latches in Fig. 4 and flip-flops in Fig. 5 when the given excitation signals are applied
at the inputs.
t
E
D
D
Q
Latch
Q
D
E
Q_L
(use the transparent D-type latch function table)
t
S
S
Q
Latch
R
RS
R
Q_L
Q
(use the RS latch function table)
Fig. 4 D-type (data) and RS latches
(SD = 0)
CLK
t
CD
D
SD
Q
D
D-FF
CLK
Q_L
CD
Q
(use the D-type flip-flop function table)
J
SD
Q
JK-FF
CLK
K
Q_L
CD
7
(CD = 0)
SD
CLK
t
J
K
Q
(use the JK flip-flop function table)
Fig. 5 JK and D flip-flops
9
Design an internal circuit using the direct method for both, the RS and D latches, and demonstrate that the work
fine by a simulation in Proteus.
S
Q
D
Latch
R
RS
Q
Latch
Q_L
E
D
Q_L
Fig. 6
Direct method:
a. Function table, symbol, state diagram
b. Internal architecture for direct method
c. Coding (S0 (Q= 0), S1 (Q = 1)
d. Truth table and design of the combinational circuit using any method
e. Circuit capture in Proteus and simulation for verification
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Deduce a D-type flip flop internal design using RS latches and other elements if necessary. Demonstrate that
your design works fine performing a Proteus simulation.
a. Specs: function table, symbol, state diagram, time diagram
b. Proposed internal architecture
c. Design all the internal blocks
d. And capture your schematic and demonstrate the way it works
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D
SD
Q
CLK
D-FF
Q_L
CD
Fig. 7
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And finally, use the 555 to build a rectangular wave of 5 V and 100 KHz, to be used as the clock synchronization
signal (CLK) for the state registers and flip-flops in this EX5. Use the Proteus oscilloscope to demonstrate your
design.
CLOCK
SD
CLK
CLOCK=100kHz
t
J
K
Fig. 8 Example of a square wave CLK signal
Q
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DIGITAL ELECTRONICS
G________
Working plan3 for solving the exercise EX 5
Explain succinctly how the cooperative group has carried out the exercise: i.e., which was your working plan; in
which way did you divide the task fairly so that more or less all of you were doing a similar amount of work; how did
you learn each other’s materials; what was worked out in class time (sessions A and B) and what was resolved in
sessions C; and so on... write down also your impressions or opinions on the subject and how your group work is
going4 ...
3
This document, filled before delivering the exercise, will be included in the group learning portfolio
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Check similar documents in http://epsc.upc.edu/projectes/ed/ED/unitats/ED_05-06_Q1_Autoavaluacio_Grup_Base.pdf and
http://epsc.upc.edu/projectes/ed/ED/unitats/que_va_malament_al_grup.pdf
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Active members’ signatures
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