EGR 2131 Unit 5
Arithmetic Operations and Circuits



Read, Sections 1.5, 1.6, and 4.5 to
4.8. (Note that we’re going back to
material that we skipped in Chapter
1.)
Homework #5 and Lab #5 due next
week.
Quiz next week.
Useful Building-Block Circuits

Here are some kinds of digital circuits we’ll
study in the weeks ahead:










Adders
Comparators
Decoders
Encoders
Code converters
Multiplexers
Latches & Flip-flops
Shift registers
Counters
Memory
Chapter 4
Combinational
Chapter 5
Chapter 6
Sequential
Chapter 7
Some Representative Chips


Many of the chips in Circuit Type Typical Chips
the 7400 series
Adder
7483
contain circuits listed Comparator
7485
on the previous slide. Decoder
7442, 74138,
74154
In a sense these
Encoder
74147, 74148
chips are obsolete,
Code converter 7447, 74184
because new designs
Multiplexer
74150, 74151,
no longer use
74153, 74157
7400-series chips.
But these are typical of the kind of circuits
that are still widely used as building blocks
in digital systems. And tools like Quartus
let you place “virtual” copies of these chips.
Useful Building-Block Circuits
(Continued)

For each type of circuit listed above,
you should understand:
1.
2.
3.
What that type of circuit does, and why it’s
useful.
How you could build such a circuit out of
gates.
Specific details of actual chips in each
category.
Binary Addition
The rules for binary addition are
0+0=0
Sum = 0, carry out = 0
0+1=1
Sum = 1, carry out = 0
1+0=1
Sum = 1, carry out = 0
1 + 1 = 10
Sum = 0, carry out = 1
When a carry in = 1 due to a previous result, the rules are
1 + 0 + 0 = 01
1 + 0 + 1 = 10
1 + 1 + 0 = 10
1 + 1 + 1 = 11
Sum = 1, carry out = 0
Sum = 0, carry out = 1
Sum = 0, carry out = 1
Sum = 1, carry out = 1
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Binary Addition
Add the binary numbers 00111 and 10101 and show
the equivalent decimal addition.
0111
00111
10101
7
21
11100 = 28
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Half-Adder
The basic rules of binary addition are performed by
a half adder, which has two binary inputs (A and
B) and two binary outputs (Carry out and Sum).
The inputs and outputs can be summarized on a
truth table.
Inputs Outputs
A
0
0
1
1
B
0
1
0
1
Cout
0
0
0
1
S
0
1
1
0
The logic symbol and equivalent circuit are:
A
S
S
S
A
B
Cout
B
Cout
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Full-Adder
Inputs
By contrast, a full adder has three binary
inputs (A, B, and Carry in) and two binary
outputs (Carry out and Sum). The truth table
summarizes the operation.
A full-adder can be constructed from two
half adders as shown:
A
A
S
S
A
S
S
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
Outputs
Cin
0
1
0
1
0
1
0
1
Cout
0
0
0
1
0
1
1
1
S
0
1
1
0
1
0
0
1
Sum
S
B
B
Cout
B
A
Cout
B
Cin
Cin
Cout
S
Cout
Symbol for Full Adder
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Full-Adder
1
A
0
B
For the given inputs, determine
the intermediate and final outputs
of the full adder.
S
S 1
A
Cout 0
B
S
S
0
Cout
1
1
Sum
Cout
1
The first half-adder has inputs of 1 and 0;
therefore the Sum =1 and the Carry out = 0.
The second half-adder has inputs of 1 and 1; therefore the
Sum = 0 and the Carry out = 1.
The OR gate has inputs of 1 and 0, therefore the final carry
out = 1.
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Full-Adder
Notice that the result from the previous example can be
read directly on the truth table for a full adder.
Inputs
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
Outputs
Cin
0
1
0
1
0
1
0
1
Cout
0
0
0
1
0
1
1
1
S
0
1
1
0
1
0
0
1
1
A
0
B
1
S
S 1
A
Cout 0
B
S
S
0
Cout
1
Sum
Cout
1
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Convention for Writing Multi-Bit Numbers



We’ll use subscripts to refer to the
individual bits in a binary number.
The bit on the right-hand end, or least
significant bit (LSB), always gets the
smallest subscript, which may be
either 1 or 0.
Example: In a four-bit number A, the
bits are labeled either
A4A3A2A1
or
A3A2A1A0
Parallel Adders
Full adders are combined into parallel adders that can add binary
numbers with multiple bits. A 4-bit adder is shown.
A4 B4
A3 B3
A2 B2
A1 B1
C0
A B Cin
Cout
S
C4
S4
A B Cin
Cout
C3
S
S3
A B Cin
Cout
C2
S
S2
A B Cin
Cout
C1
S
S1
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Parallel Adders
The logic symbol for a 4-bit parallel adder is shown. This 4-bit adder
includes a Carry In (labeled C0) and a Carry Out (labeled C4).
Binary
number A
Binary
number B
Carry
In
1
2
3
4
1
2
3
4
C0
S
1
2
3
4
C4
4-bit
sum
Carry
Out
If you’re just using it to add two 4-bit numbers, you’ll tie C0 to
ground. If you’re adding two numbers with more than 4 bits,
you’ll use more than one of these adders connected together.
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Two Adder Chips


74283 Four-bit binary adder
7483 is an older chip that is
functionally identical to the 74283, but
the pins are laid out differently
Cascading Parallel Adders
When we connect the outputs from one circuit to the
inputs of another identical circuit to expand the number of
bits being operated on, we say that the circuits are
cascaded together.
For example, you can cascade two 4-bit parallel adders to
add two 8-bit numbers. To do this, connect the lowerorder adder’s Carry Out to the higher-order adder’s Carry
In.
See textbook’s Figure 7-18 (next slide).
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Terminology: One’s-Complement and
Two’s-Complement




The one’s-complement of a binary
number is the binary number that you
get when you invert each bit.
Example: What is the one’s-complement
of 0011 0101?
The two’s-complement of a binary
number is the binary number that you
get when you invert each bit and then
add 1 to the result.
Example: What is the two’s-complement
of 0011 0101?
Representing Negative Integers



The rules for doing binary subtraction by
hand are similar to the rules for doing binary
addition by hand.
But first we need to understand how to
represent negative integers in binary.
Over the years, people have developed
several ways of representing negative
integers in binary:
The easiest
 Sign-magnitude representation
for humans.
 One’s-complement representation
The best for
 Two’s-complement representation
computers.
Interpreting Strings of 1s and 0s



In digital systems we have nothing but
1s and 0s to represent all kinds of info:
text, numbers, images, music, etc.
To interpret a string of 1s and 0s, you
have to be told what kind of info it
represents.
Example:
What does 0100 00012 represent?
Possible answers:
The integer 65.
The letter A (in ASCII code).
A particular color in a JPEG file. …
Unsigned versus Signed Binary Integers



Up to now, whenever we’ve worked
with binary integers, we’ve assumed
they were unsigned binary integers.
In other words, we’ve assumed that the
integers were all positive.
Sometimes we also need to be able to
represent negative integers, in which
case we’re dealing with signed binary
integers.
To do this, we’ll use one bit to indicate
the integers’s sign (positive or
negative).
Range of Unsigned Binary Integers

Arranging unsigned 8-bit integers in
order from least to greatest would
give you a list that starts and ends like
this:
Binary
0000 0000
0000 0001
0000 0010

1111 1101
1111 1110
1111 1111
Decimal
0
1
2

253
254
255
Range of Unsigned Binary Integers

For unsigned integers with a fixed
number of bits n:



The least integer we can represent is 0.
The greatest integer we can represent is
2n-1.
Example: Using 8 bits,


The least integer is 0000 00002, which is
equal to decimal 0.
The greatest integer is 1111 11112, which
is equal to decimal 255 (=28-1).
Representing Signed Binary Integers

To represent both positive and negative
integers, we’ll use the leftmost bit as
a sign bit, like this (for 8 bits):
Negative integers
(sign bit = 1)
Zero and positive integers
(sign bit = 0)
Binary
1000 0000
1000 0001
1000 0010

1111 1111
0000 0000
0000 0001

0111 1110
0111 1111
Decimal
-128
-127
-126

-1
0
1

126
127
Two’s-Complement Representation



The scheme shown on the previous
slides is called two’s-complement
representation.
This is how almost all computers
represent signed integers, because
this scheme results in simple circuits
for doing binary arithmetic.
Other common names for it: two’s
complement notation or two’s
complement form.
Range of Signed Binary Integers


For signed integers with a fixed number of
bits n, the least integer we can represent
is −2n−1, and the greatest integer we can
represent is 2n−1−1.
Example: Using 8 bits,
 The least integer we can represent is
1000 00002, which is equal to decimal
−128 (= −27).
 The greatest integer we can represent is
0111 11112, which is equal to decimal
127 (= 27-1).
Steps for Converting from Decimal to
Two’s-Complement Form
1.
2.
If the integer is positive, convert it to
binary as we’ve always done.
If the integer is negative:
a)
b)
c)

Ignoring the sign, convert it to binary as
we’ve always done.
Invert each bit. (That is, change each 0
to 1, and change each 1 to 0.)
Add 1 to the result.
Examples


Convert 2310 to two’s complement form using
8 bits.
Convert −2310 to two’s complement form using
8 bits.
Steps for Converting from Two’sComplement Form to Decimal
1.
2.
If the sign bit = 0, the integer is
positive. Convert to decimal as we’ve
always done.
If the sign bit = 1, the integer is
negative. Follow these steps:
Invert each bit.
b) Add 1.
c) Convert the result to decimal as we’ve
always done.
d) Write a negative sign in front.
 Examples: Convert 0110 0010 to decimal.

Convert 1110 0010 to decimal.
a)
Binary Subtraction


The rules for doing binary subtraction are
similar to the rules for addition.
Just as with decimal numbers, when you
subtract you might have to borrow from the
column to the left. (This is similar to the carry
into the next column that you sometimes get
when adding.)
The rules for binary subtraction are
0-0=0
Difference = 0, borrow = 0
0 - 1 = -1
Difference = 1, borrow = 1
1-0=1
Difference = 1, borrow = 0
1-1=0
Difference = 0, borrow = 0
Adding Signed Numbers
Using two’s complement form for negative integers
simplifies addition and subtraction of signed numbers.
Rules for addition: Add the two signed numbers. Discard
any final carry out of the MSB. The result is in two’s
complement form.
Examples:
0001 1110 30
+ 0000 1111 + 15
0010 1101 45
0000 1110 14
+1110 1111 + -17
1111 1101 -3
1111 1111 -1
+ 1111 1000 + -8
11111 0111 -9
Discard carry
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Subtracting Signed Numbers
Rules for subtraction: Negate the number being subtracted,
and then add. Discard any final carry out of the MSB. The
result is in two’s complement form.
Us the same numbers as on previous slide, but subtract:
0001 1110 30
- 0000 1111 – 15
1111 1111 -1
- 1111 1000 – -8
0000 1110
14
- 1110 1111 – -17
Negate the number being subtracted, and then add:
0001 1110 30
+1111 0001 +-15
10000 1111 15
Discard carry
0000 1110 14
+ 0001 0001 +17
0001 1111 31
1111 1111 -1
+ 0000 1000 + 8
10000 0111 7
Discard carry
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
An Adder/Subtractor Circuit


By combining parallel adder chips (such as
the 74283 or the 4008) with a controlled
inverter, we can make a circuit that either
adds or subtracts, depending on the
value of a control input.
See next slide.
Figure 7.23
8-bit two’s-complement adder/subtractor illustrating the subtraction 42 – 23 = 19.
Digital Electronics: A Practical Approach with VHDL, 9th Edition
William Kleitz
Copyright ©2012 by Pearson Education, Inc.
All rights reserved.
Comparators
The function of a comparator is to compare the magnitudes of two
binary numbers to determine the relationship between them. In the
simplest form, a comparator can test for equality using XNOR gates.
How could you test two 4-bit numbers for equality?
AND the outputs of four XNOR gates.
A1
B1
A2
B2
Output
A3
B3
A4
B4
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Comparators
IC comparators provide outputs to indicate which of the input
numbers is larger or if they are equal. Cascading inputs are provided
to expand the comparator to larger numbers.
A0
A1
A2
A3
Cascading
inputs
B0
B1
B2
B3
0
COMP
A
3
A>B A>B
A=B A=B
A<B A<B
0
B
3
Outputs
The IC shown is the
4-bit 7485.
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Comparators
IC comparators can be expanded using the cascading inputs as shown.
The lowest order comparator has a HIGH on the A = B input.
LSBs
A0
A1
A2
A3
+5.0 V
B0
B1
B2
B3
MSBs
0
COMP
A
3
A>B A>B
A=B A=B
A<B A<B
0
B
3
A4
A5
A6
A7
B4
B5
B6
B7
0
COMP
A
3
A>B A>B
A=B A=B
A<B A<B
0
B
Outputs
3
© 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved
Comparator Chip

7485 Four-bit magnitude comparator