Global Triggers,
TCA Technology
M. Stettler, M. Hansen (CERN)
C. Foudas, G. Iles (Imperial College)
J. Jones (Princeton)
A. Taurok, H. Bergauer, C.-E. Wulz (Vienna)
Presented by
C.-E. Wulz
SLHC Meeting
CERN, 21 May 2008
Global Trigger Concepts for LHC and SLHC
LHC
GTL
Sync
delay
FDL
GMT
COND
 ALGO
GTL
REC
GCT
Totem, Castor, ZDC,
BTPX, BSC, …
SLHC
Sync
delay
Sync
delay
Sync
delay
COND
 ALGO
PSB
128
Algo
Final
OR
Technical Triggers
Prescalers
&
Trigger
Counters
PSB
Optical links
GMT
COND chip
FDL chip
FPGA:
Standard Conditions
GTL
GCT
Sync
delay
COND chip
- FPGA: DSPs (XC5V100T)
- FPOA: DSP array
Tracker
Trigger
Sync
delay
Totem, Castor, ZDC,
BTPX, BSC, …
C. - E. Wulz
Tracker ‘Conditions’
Sync
delay
‘Conditions’
nn
Algo
(and,
or,
not)
Final
OR
Prescalers
&
Trigger
Counters
SYNC
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SLHC Trigger Meeting, May 2008
Global Trigger Concepts for LHC and SLHC
•
Synchronize all Trigger Objects to arrive at the same time at the logic chip
–
–
•
•
2008 Version: Muons: done by GMT; Calo_objects: done by PSB; Technical Triggers: done by PSB
SLHC Version: Muons: done by GMT; Calo_objects: done by GCT; TechTrig: done by SYNC chip
Tracker: done by Tracker_Trigger
Send all Trigger Objects into one chip to be able to make any correlations between them
Use an FPGA to change trigger conditions as required by physics
–
–
–
New trigger setup: -> configure FPGA with new trigger conditions
New parameter values for same setup:
2008 Version: Load new ET and pT thresholds by software
– SLHC Version: Load all values by software ( Upgrade Version)
•
Calculate physics trigger algorithms in parallel (FPGA branch)
–
–
•
Final OR mask for all Algorithm bits; Prescaler & Counter for each Algorithm
–
•
2008 Version: 128 Algorithms, limited by board layout, connectors and chip size
SLHC Version: Extend to ‘nn’ Algorithms <- ‘Algo’ signals inside chip
(chip size will be the only restriction)
SLHC: maybe more requirements
SLHC Version:
–
–
C. - E. Wulz
Array of DSPs for complex physics triggers
• C++ code -> trigger program with constant latency(!)
Each trigger object is received twice, on 2 optical links
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SLHC Trigger Meeting, May 2008
Input to Global Trigger
• Global Calorimeter Trigger (GCT): redefinition (reduction?) of trigger data
• 4 e/, 4 isolatetd e/
(ET, h, f)
• 4 central jets, 4 forward jets (ET, h, f)
• 4 tau jets
• total_ET, HT
 4 e/ with ISOLATION bit
 n jets
 apply set of thresholds in GCT
and send resulting bits to FDL chip
• missing_ET
(ET, f)
• “jet counts” (now towers above thr., ring ET’s)
• More than 4 objects per type: 5 or 6 (?)  Simulation for SLHC
• Global Muon Trigger (GMT):
• 4 muons
(pT, h, f, mip, iso, charge, quality)
• Tracker Trigger:
• Tracks/jets with h and f
• ‘Conditions’ calculated in Tracker Trigger
C. - E. Wulz
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 COND chips
 FDL chip
SLHC Trigger Meeting, May 2008
CMS GT Standard Algorithm in FPGA: Example
Standard CONDITION chip
ieg1
ieg2
ieg3
ieg1
ieg2
ieg3
ieg4
ieg4
ieg1
Single particle thr1,
Single particle thr1,
h, f window1
Single
particle thr1,
h, f window1
Single
particle thr1,
h, f window1
h, f window1
Predefined
VHDL code
Missing Energy
TEMPLATE
Single particle thr2,
Single particle thr2,
h, f window2
Single
particle thr2,
h, f window2
Single
particle thr2,
h, f window2
h, f window2
ieg3
ieg2
Dh, Df Correlation
TEMPLATE
ieg4
Single particle
TEMPLATE
Dh, Df Correlation
Parameters
ET thresholds 1,2
h, f window 1,2
Find 2 out of 4 particles fulfilling all conditions
Missing Energy
threshold
IEG condition:
ieg2wsc
Missing ET condition:
FDL chip
Combinatorial logic:
C. - E. Wulz
Mask, Veto_mask
Algorithm = ieg2wsc and MET
ALGO bit (i)
prescalers
5
MET
Final_OR
SLHC Trigger Meeting, May 2008
Condition chip with DSP array or RISCs
Trigger objects
(GCT, GMT, TrackerTr…)
Parameters
Hardwired logic*
DSP
Condition program
XC5VFX100T:
256 DSP48E(550MHz),
4 Ethernet MAC,
3 PCIexpress end points,
16 GTX RocketIO (6.5Gb/s)
680 IO (1.25Gb/s LVDS)
Latency = # of instructions
Condition bit
*) if DSPs are implemented in FPGA
Constraints:
Parallel or tree structures
Trigger objects
DSP
DSP
DSP
DSP
DSP
DSP
Latency
Latency
OR
Condition bit
 Algorithm logic in FDL chip
C. - E. Wulz
• # of Conditions  # of DSPs
• # of instructions  latency limit
• Keep pipeline structure
Trigger objects
DSP
Condition bit
 Algorithm logic in FDL chip
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SLHC Trigger Meeting, May 2008
Global Trigger board for SLHC
Ethernet IP
Ethernet
IO
Control
CPU
DAQ chip
CMS - DAQ
Event builder
Preliminary!
Ethernet IP
Control
CPU
L1A_daq + Serial TX
L1A_daq + Serial TX
Spy_mem‘s &
Ringbuffers
RX:
Serial parallel
COND_logic
or
DSP array
Condition bits
GCT: 5 ...
GMT: 2
Tracker: ~2 ..
Parallel
data
CLK,
BCRES, ...
LVDS
Spy_mem‘s &
Ringbuffers
nn
Algo
(and,
or,
not)
Prescalers
2 sets of
opt. rcvers
Final
OR
LVDS
COND chip
LVDS
LVDS
Sync
circuits
TIMING
circuits
Trigger
Counters
LVDS
Condition bits
FDL chip
Ethernet IP
LVDS
CLK, BCRES, ..
SYNC Chip
C. - E. Wulz
Ethernet IP
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SLHC Trigger Meeting, May 2008
Trigger system design based on Telcom developments
C. - E. Wulz
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SLHC Trigger Meeting, May 2008
ATCA standard
C. - E. Wulz
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SLHC Trigger Meeting, May 2008
ATCA connectivity
C. - E. Wulz
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SLHC Trigger Meeting, May 2008
TCA
C. - E. Wulz
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SLHC Trigger Meeting, May 2008
TCA for GCT Quiet/ MIP Bits
• Data processing TCA module + custom active switching backplane
• Data processor card schematics have been designed (M. Stettler) and
parts have been bought. The card is under layout at Los Alamos.
Advanced PCB manufacturing techniques (e.g. micro-vias that
penetrate several layers) are needed. Board stackup has been
completed and verified with vendor.
• The Backplane has been designed (J. Jones + M. Stettler) but will be
tested after the processor card.
• A TCA crate and a commercial backplane have been bought and are
already at CERN.
• The first prototypes are expected to arrive at CERN in Summer 2008.
C. - E. Wulz
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SLHC Trigger Meeting, May 2008
Main QM Data Processing Module
• Receives and transmits data via front panel optical links.
• On board 72x72 Cross-Point Switch allows for dynamical routing of the data either
to a V5 FPGA or directly to the uTCA backplane.
• The module can exchange data with other modules either via the backplane or via the
front panel optical links.
C. - E. Wulz
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SLHC Trigger Meeting, May 2008
Custom TCA Backplane
• Instrumented with 144x144 cross-point switch for extra algorithm flexibility.
• Allows dynamical or static routing of the data to different Data Processing Modules.
C. - E. Wulz
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SLHC Trigger Meeting, May 2008
Routing detail
C. - E. Wulz
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SLHC Trigger Meeting, May 2008
BACKUP
C. - E. Wulz
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SLHC Trigger Meeting, May 2008
C. - E. Wulz
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MIP/QUIET bits
8 RPC muons
4 DT muons
4 CSC muons
TTC - GPS-TIME
S-links: DAQ, EVM
CLK, ORBIT
TOTEM
(ET*=total ET, HT, MET)
4TAU-JET, ET*, JetNr,
4IEG, 4EG, 4JET, 4fJET
21
20
PSB
PSB
19
18
GMT
PSB
17
16
15
14
13
GTFE
TIM
PSB
PSB
PSB
12
11
GTL
spare
10
FDL
9
PSB
7
6
5
TECHNICAL
TRIGGER SIGNALS
TCS
L1A_OUT
L1A_OUT
3
FREE VME
8
128 Algo
L1A
2
FREE VME
4
1
CAEN VME
CONTROLLER
STATUS SIGNALS
aTTS DAQ
APV-EMULATORS
Detector subsystems
PC: RUN Control
Global Trigger Crate 2008
Backplane
SLHC Trigger Meeting, May 2008
I/O, Hardware
I/O requirements:
4 calo objects(jet, ieg,..)  64 bits/40MHz  2.56 Gbps
4 calo objects(jet, ieg,..)  64 bits/80MHz  5.12 Gbps
1.25 Gbps LVDS IO for each pin pair:  31 bits/40MHz // 15 bits/80MHz
Virtex5
XC5VFX100T:
256 DSP48E(550MHz),
4 Ethernet MAC,
3 PCIexpress end points,
16 GTX RocketIO (6.5Gb/s)
680 =340 pairs IO (1.25Gb/s LVDS)
DSP48E Slices :
add/subtract o = Z ± (X + Y +CIN)
Accumulate o = o + A&B + C
//concatenate
Accumulate & shift
Multiply Accumulate(MACC)
MUX, BarrelShifter, Counter, multiply, divide,
square_root, square_root of sum of squares,
Parallel FIR Filters,…
Altera Stratix III
DSP block :
EP3SE110 : for DSP+Memory applications
DSP: 448 18x18 Multipliers for 550 MHz clock
896 18x18 sum_of_multipliers
56(88) LVDS 1.25Gb/s with serializer/deserializer (SERDES)
programmable pre-emphasis, (RapidIO, … )
64(96) LVDS low speed
300 MHz;
8 mult18x18, regs, adders,
subtractors, accumulators, multiplexer, …
FPOA (..object arrays)
1GHz clock
256 ALU Arithmetic Logic Units 16 bit
64 MAC multiply&accumulate units
80 RF register set( 64 regs 16 bit)
2 fast serial IO links
C. - E. Wulz
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SLHC Trigger Meeting, May 2008