### Lecture 5: Timing Verification and Optimization

```ELEC 7770
Spring 2008
Timing Verification and Optimization
Vishwani D. Agrawal
James J. Danaher Professor
ECE Department, Auburn University, Auburn, AL 36849
[email protected]
http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr08/course.html
Spring 08, Feb 6
ELEC 7770: Advanced VLSI Design (Agrawal)
1
Proof of Correctness
 Static timing analysis proves the timing



correctness. That is, the circuit is guaranteed to
work at the clock rate determined by the critical
path.
But the circuit may also work correctly at faster
speeds.
Because the critical path identified by STA (static
timing analysis) may be a “false path”.
STA overestimates the delay of the circuit.
Spring 08, Feb 6
ELEC 7770: Advanced VLSI Design (Agrawal)
2
False and True Paths
 A false path cannot propagate an event and hence

cannot affect the timing of the circuit. False paths are
dynamically unsensitizable.
Dynamically sensitizable path (true path): All off-path
inputs must settle down to their non-controlling values
when the event propagates through the path.
a
b
c
1
0
d 1
True path of length 3
e
y
2
1
f
1
1
3
z
1
0
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1
ELEC 7770: Advanced VLSI Design (Agrawal)
4
True path of
length 4
3
Static Sensitization of Path
 Static sensitization of path: All off-path inputs can

be set to their non-controlling values.
Longest path in the following example is statically
unsensitizable. Such paths are often referred to,
though not correctly (why?), as false paths.
True path of length 3
a
1
d 1
e
2
1
1
b
0
Spring 08, Feb 6
1
y
1
3
f
ELEC 7770: Advanced VLSI Design (Agrawal)
z
1
4
False path of
length 4
4
An Example
 Statically unsensitizable (false) path.
 P. C. McGeer and R. K. Brayton, Integrating
Functional and Temporal Domains in Logic
Design, Springer, 1991.
a
False path of delay 3
e
1
0
0
1
g
d
b
c
1
1
1
f
0
Spring 08, Feb 6
ELEC 7770: Advanced VLSI Design (Agrawal)
5
Example (Cont.)
 Another statically unsensitizable false path.
 P. C. McGeer and R. K. Brayton, Integrating
Functional and Temporal Domains in Logic
Design, Springer, 1991.
a
1
False paths of delay 3
e
1
0
0
1
g
d
b
c
1
1
f
0
Spring 08, Feb 6
ELEC 7770: Advanced VLSI Design (Agrawal)
6
Example (Cont.)
 Paths are dynamically sensitizable and will affect the timing

if both are together faulty.
P. C. McGeer and R. K. Brayton, Integrating Functional and
Temporal Domains in Logic Design, Springer, 1991.
a
False paths of delay 3
e
1
2 3
1
g
d
b
c
1
1
f
0
Spring 08, Feb 6
ELEC 7770: Advanced VLSI Design (Agrawal)
7
Static Sensitization Condition
x
y
z
Off-path inputs
There must exist an input vector (PI) that satisfies the following conditions:
∂y/∂x = 1, ∂z/∂y = 1, . . .
Where ∂y/∂x = y(x=1, PI)  y(x=0, PI) is Boolean difference
Spring 08, Feb 6
ELEC 7770: Advanced VLSI Design (Agrawal)
8
An ATPG Method
x
y
z
Stuck-at-0
Path is false if this
fault is redundant
Spring 08, Feb 6
ELEC 7770: Advanced VLSI Design (Agrawal)
9
Optimism and Pessimism
Statically
Dynamically
sensitizable
sensitizable
Paths
paths
(optimistic)
Structural paths analyzed by STA (pessimistic)
Spring 08, Feb 6
ELEC 7770: Advanced VLSI Design (Agrawal)
10
Theorem 1
 Every statically sensitizable path is dynamically


sensitizable.
Proof: Since a vector exists to sensitize the path,
if that vector does not specify the path input,
then toggling the primary input at the origin of
the path will propagate an event through the
path.
P. C. McGeer and R. K. Brayton, Integrating
Functional and Temporal Domains in Logic
Design, Springer, 1991, p. 35.
Spring 08, Feb 6
ELEC 7770: Advanced VLSI Design (Agrawal)
11
Theorem 2
 The longest path in a circuit is dynamically


sensitizable iff it is statically sensitizable.
Proof: Because this is the longest path, all offpath inputs will settle to their sensitizing values
at the inputs of any gate before the on-path
event propagates through that gate.
P. C. McGeer and R. K. Brayton, Integrating
Functional and Temporal Domains in Logic
Design, Springer, 1991, p. 37.
Spring 08, Feb 6
ELEC 7770: Advanced VLSI Design (Agrawal)
12
Proof of Theorem 2
 Case 1: Static sensitization does not specify the


value at the path origin.
Toggling the path origin will propagate an event
through the path causing dynamic sensitization.
Example:
1
0
A 01 or 10
here will propagate
through the path
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Statically sensitized path
ELEC 7770: Advanced VLSI Design (Agrawal)
13
Proof of Theorem 2 (Cont.)
 Case 2: Static sensitization specifies the value at the path origin.
 Toggling the path origin will propagate an event through the path
causing dynamic sensitization because the event on the longest
path will see all gates sensitized through shorter paths.
 Example:
This event
Shorter path sets this to
1 before the event arrives on
the longest path
0
propagated
through
longest path
01
1
Apply 01 event here
Spring 08, Feb 6
Statically sensitized path
ELEC 7770: Advanced VLSI Design (Agrawal)
14
Proof of Theorem 2 (Cont.)
 Case 3: Longest path is statically unsensitizable.
 Toggling the path origin will not propagate any

event through the path. Toggling other input only
dynamically sensitizes
shorter
This event did
Shorter path
sets this path.
to
not propagate
1 before the event arrives on
Example:
through
the longest path
01
01
Apply 01 events
Spring 08, Feb 6
longest path
01
Statically unsensitizable path
ELEC 7770: Advanced VLSI Design (Agrawal)
15
Speeding Up a Circuit
2
False path
w
a
x
2
w
a
3
u
2
2
v
2
y
z
u
v
x
y
z
0 1 2 3 4 5 6 7 time
Spring 08, Feb 6
ELEC 7770: Advanced VLSI Design (Agrawal)
16
Speeding Up a Circuit
2
False path
w
a
x
2
w
a
3
u
2
2
v
2
y
z
u
v
x
y
z
0 1 2 3 4 5 6 7 time
Spring 08, Feb 6
ELEC 7770: Advanced VLSI Design (Agrawal)
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Speeding Up a Circuit
Reducing the delay of a false path can increase circuit delay.
2
w
a
x
2
w
a
1
u
2
2
v
2
y
z
u
v
x
y
z
0 1 2 3 4 5 6 7 time
Spring 08, Feb 6
ELEC 7770: Advanced VLSI Design (Agrawal)
18
Speeding Up a Circuit
2
False path
w
a
x
2
w
a
1
u
2
2
v
2
y
z
u
v
x
y
z
0 1 2 3 4 5 6 7 time
Spring 08, Feb 6
ELEC 7770: Advanced VLSI Design (Agrawal)
19
A Delay Optimization Algorithm
 REDUCE_DELAY (Circuit graph (V, E), ε)
Repeat {
Compute critical paths and critical delay Δ
Set output data ready time to Δ
Compute slacks
U = vertex subset with slack < ε
W = select vertices in U
Apply transformation to vertices in W
} until (no transformation can reduce Δ)

}
G. De Micheli, Synthesis and Optimization of Digital
Circuits, McGraw-Hill, 1994, p. 427.
Spring 08, Feb 6
ELEC 7770: Advanced VLSI Design (Agrawal)
20
Example of a Transformation (1)
a
b
c
2
1
2
d
e
3
2
1
2
x
1
g
y
2
Δ = 11
x = a’ + b’ + c’ + d’ + e’
Spring 08, Feb 6
ELEC 7770: Advanced VLSI Design (Agrawal)
21
Example of a Transformation (2)
a
b
c
2
1
2
d
e
3
2
1
2
x
Isolate and resynthesize
1
g
y
2
Δ = 11
x = a’ + b’ + c’ + d’ + e’,
Spring 08, Feb 6
all inputs are symmetric.
ELEC 7770: Advanced VLSI Design (Agrawal)
22
Example of a Transformation (3)
d
3
b
c
2
a
e
1
2
1
2
1
2
1
2
x
y
2
g
Δ=8
x = a’ + b’ + c’ + d’ + e’,
Spring 08, Feb 6
a and d are interchanged.
ELEC 7770: Advanced VLSI Design (Agrawal)
23
c0
a0
b0
sum0
FA0
a1
b1
sum1
FA1
a2
b2
sum2
FA2
sum31
a31
b31
Spring 08, Feb 6
ELEC 7770: Advanced VLSI Design (Agrawal)
FA31
c31
24
ci
ai
bi
Spring 08, Feb 6
FAi
XOR
AND
sumi
XOR
AND
ELEC 7770: Advanced VLSI Design (Agrawal)
OR
Ci+1
25
b0-b15
cin
a16-a31
b16-b31
0
a16-a31
b16-b31
1
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16-bit
ripple
carry
16-bit
ripple
carry
16-bit
ripple
carry