מבנה מחשב – מבוא למחשבים ספרתיים
תרגול מספר 5
Encoders, Decoders & Shifters
EncoderF
• Specification:
input : x , weight ( x) 1
output : y, F
Functionality:
y[n 1 : 0] i x[i] 1 , i 1,2,....
y[n 1 : 0] 0 x[0] 1 or x 0
F 1 x 0
2n
2n
Proof of Correctness
• By induction.
• Base:
n 1
y[0 : 0] 1 y[0] 1
x[1] 1
y[0 : 0] 0 x[0] 1 or x[1] x[0] 0
F NOR ( x[0], x[1]) 0 x[1] x[0] 0
Proof of Correctness
• Induction assumption:
EncoderF(n-1) is correct
• Induction step:
Prove that if the design is correct for k-1, it is
also correct for k.
Proof of Correctness
• Induction step:
• We need to examine the output closer
n 1
y[n 2 : 0] OR ( EncoderF ( x[2 1 : 2 ]) ,
n
EncoderF ( x[2
n 1
1 : 0])
Since weight(x)=1, one of the components must be all
zeros.
)
Induction step - continued
• There is at most one i for which x[i] = 1
• First case:
i 2 n 1
y[n 2 : 0] i
y[n 1] NOT ( F ( x[2 n 1 : 2 n 1 ])) NOT (1) 0
y[n 1 : 0] i
Induction step continued
• Second case: i 2 n 1
y[n 2 : 0] i 2
n 1
y[n 1] NOT ( F ( x[2n 1 : 2n1 ] ) NOT (0)
y[n 1 : 0] y[n 2 : 0] 2
y[n 1 : 0] i
n 1
Induction Step continued
• Third case:
x0
2n
n 1
n 1
y[n 2 : 0] OR (0 ,0 ) 0
n 1
n 1
y[n 1] NOT ( F ( x[2 1 : 2 ]) NOT (1) 0
n
Induction Step continued
• Calculating F
F ( x) AND( F ( x[2 n 1 : 2 n 1 ]) ,
F ( x[2 n 1 1 : 0]) ) 1
x[2 1 : 2
n
x0
2n
n 1
]0
2 n1
and x[2
n 1
1 : 0] 0
2 n1
Induction Conclusion
• If EncoderF(k-1) is correct then
EncoderF(k) is correct.
• Since EncoderF(1) is correct (base), it
follows that EncoderF(n) is correct for all n.
Cost of EncoderF
C (1) C ( NOR )
C (n) 2 C (n 1) C ( AND) C ( NOT ) (n 1) C (OR )
2 C (n 1) O(n)
O(2 n )
O(n) in terms of input size
Delay of EncoderF
D(1) D( NOR )
D(n) D(n 1) max{ D( AND), D( NOT ), D(OR )}
D(n 1) const
O ( n)
O(log n) in terms of input size
Cost of Decoder
• Each of the 2n output gates is fed by a
different non-trivial gate, therefore the cost
must be at least that much.
Cost of Encoder*
• There are 2n inputs which are fed into nontrivial gates. If the fan-in is bounded, then
there must be an order of that size of input
gates
• Another way to view it: each output bit has
a cone of exactly 2n-1. Why?
Delay of Decoder & Encoder*
Decoder - Using the theorem shown in class:
Delay log c | cone( f ) | O(log n)
Encoder - Using the same method:
Delay log c | cone( f ) | log c 2 O(n)
n
Barrel Shifter
Functionality Preservation
• If we swap the order of the blocks with
their inputs will the functionality be
preserved?
• If we swap the order of the blocks without
swapping their inputs will the functionality
be preserved?
Asymptotic Optimality of Delay
• The delay of the circuit is log(n)
• How can we prove optimality?
• We can view the circuit as having n+log(n)
inputs.
• Each output bit is in a certain situation
affected by every input bit. Therefore the
cone of every output bit is n+log(n)
• This results in a delay that is O(log(n)).
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