Questions on High Level Synthesis
1. Considering a unscheduled version of the following graph, and
assuming only two ALUs and two multipliers, compute how many
possible binding exist for the six multiplication and the overall
number of binding when using two resources per type.
2. For the HDL code shown below, do the following:
a. Draw the CDFG [Control & Data Flow Graph]
b. DO scheduling & allocation (Assuming infinite resources to
start with)
While (a < f) loop
X: = X + 2;
Y:= X + S + (X/Z);
Z := (W + 2) / (W*Y);
F = Z;
End loop
c. Derive the scheduling for a resource constrained scenario
with two adders, one multiplier and one division data
component.
Logic Synthesis, Multi Level Optimization
3. Consider the following model fragment ---- Exercise for Multi
level optimization [logic synthesis]
X = ac + de,
Y = a + b,
W = p + a,
Z = q + b,
P = ac + ad + e,
Q = ap + b
a. Draw the corresponding logic network graph while
considering a, b, c, d, e as primary input variables and X,
Y, W, Z as primary output variables.
b. Apply common sub-expression elimination and check if the
graph is optimized.
c. Draw the data-flow graph/circuit representation of the
optimized graph after applying above elimination
technique.
Logic Synthesis: Two Level Optimization
1. Derive the optimized SOP for the following function:
F (w,x,y,z) = X’Y’ + WXY + X’YZ’ + WY’Z
d. Using Quine McCluskey method
e. Derive the same using Karnaugh maps (plot the 4 variable
map) and plot the result on the three dimensional cube,
Floorplaning Problems
1. Consider the following slicing floor plan with 8 modules represented
with
Polish Expression [E]: 235V4HV18VH7V6V
f. Draw the slicing tree for the above expression.
g. Consider the dimensions of the modules 1 through 8 are
{(2, 4), (2, 4), (3, 3), (5,3), (1,3), (1, 4), (3,6), (4,2) }.
i. Find out the area of the smallest rectangle that can
accommodate these modules with no overlap, each
module is free to rotate by 90Degrees.
ii. Draw optimally-sized slicing floorplan using (x,y) coordinates doing M1, M2, M3 operations as discussed
in class.
Routing Problems
1. Wire length Estimation, consider the following two nets n1: b-de-f, n2: a-b-c-d-e. Cells a, b, c, d, e and f are placed at (3,0),
(2,8), (1,5), (4,5), (11,7) and (3,9) respectively.
h. Draw the cell arrangement using a grid of (12, 12)
i. Compute the estimated wire length using half-perimeter,
minimum spanning tree method, Assume the 1st cell is the
source.
Partitioning Problems
1. KL algorithm: Consider the following netlist NL1, Assume that the
first gate is the source, and gate area is all 1.
NL1: n1 = a-b-c, n2=b-d-e-f, n3=c-f-g, n4=a-g, n5=d-e-h,
n6=f-h
j. Where n1…n6 are the gates in the netlist and respective
literals represent the pins for these gates. Nothing to be
assumed as input or output.
k. Model the netlist by edge-weighted undirected graph. The
edge weight is 1/(k-1) where k is the number of gates,
e.g: ½ for n1 and 1/3 for n2 etc.
l. Given the initial partition P1={a,b,c,d | e,f,g,h} of G1
perform a single pass of KL algorithm and tell the cut size
after swap.
[Hint: map the wires to gates and do the KL optimization]
Logic Synthesis Timing problem
1.Consider the simple circuit below. Do the following:
m. Assume each gate has a delay equal to the number of its
inputs, i.e., the inverters have delay = 1 and NAND have
delay = 2. Ignore the wires for delay. Draw the fully delay
graph with one source and one sink node.
n. What is the fastest cycle time we could use if this was the
logic we had between latch stages in our design? Show
how you computed this.
o. Using this cycle time number, show the Arrival Time
(AT(node)) and Required Arrival Time (RAT(node)) times
for each node in your graph. Use the algorithm from the
class notes. You can do the topological sorts and use these
to generate the AT and RAT numbers. Use only single
delay per gate (delay = number of gate inputs). Given the
AT and RAT numbers, show the slacks at each node.
p. Is the longest path statically sensitizable? Explain why or
why not?
Partitioning Problem
1. Consider the bisectioning of the graph with 2n nodes depicted in
the following figure (where n is atleast 4). Suppose the initial
partitioning is X = {1, 2,…n} and Y = {n+1, n+2,…..2n}
a. Apply K-L algorithm to this problem. In each iteration (i.e
swapping of subset of nodes to reduce cut size), you need to
give atleast 3 complete steps (each step is a selecting of a
pair of nodes to swap and lock), then you can use
observations to give the results of iteration.
b. If in each iteration we only consider swapping a pair of
nodes, what will be the solution?
Floorplaning Problem
2. Consider the Polish expression 123V45HHV, is it normalized? If
not, normalize it. Then draw a slicing tree corresponding to it.
3. Given the floorplan topology in Problem 2, and module shapes as
follows: 1: (4,3), 2: (3,5), 3: (6,4), 4: (5,2), 5: (7,4), find the
orientation for each module such that the chip perimeter is
minimized.
Partitioning Problem
4. You are given the following circuit for partitioning.
a. Model the circuit by a flow network.
b. Find a maximal flow from a to e in the network, and
identify a min-cut corresponding to it. Is the min-cut giving
a balanced partitioning?