Accellera Systems Initiative Overview
April 2013
Dennis Brophy, Vice Chairman
Welcome
Agenda
 Current News
 About Accellera
 IEEE collaboration
 Technical activities overview
 SystemC Working Groups status
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© 2013 Accellera Systems Initiative, Inc.
April 2013
SystemC AMS 2.0 Completed
Announced 19 March
2013
Presentations on
standard at ESCUG
- See http://www.ti.unituebingen.de/ESCUGWS27
-Grenoble2013.1508.0.html
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© 2013 Accellera Systems Initiative, Inc.
April 2013
Multi-Language Working Group
Launched
Announced 3 April
2013
Industry Invited to Join
Mission
- Create a standard and
functional reference for
interoperability of multilanguage verification
environments and
components.
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© 2013 Accellera Systems Initiative, Inc.
April 2013
To Be Announced:
forums.accellera.org
Forums
- Accellera System Initiative
- SystemC
- UCIS
(Unified Coverage Interoperability Standard)
- UVM
(Universal Verification Methodology)
- Commercial Announcements
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© 2013 Accellera Systems Initiative, Inc.
April 2013
To Be Announced: UVMWorld 3.0
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© 2013 Accellera Systems Initiative, Inc.
April 2013
Welcome
Agenda
 Current News
 About Accellera
 IEEE collaboration
 Technical activities overview
 SystemC Working Groups status
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© 2013 Accellera Systems Initiative, Inc.
April 2013
Accellera Systems Initiative
Our Mission
 To provide design and verification
standards required by systems,
semiconductor, IP and design tool
companies to enhance a front-end
design automation process.
 To collaborate with its community
of companies, individuals and
organizations in delivering the
standards that lower the cost to
design commercial EDA, IC and
embedded system solutions.
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© 2013 Accellera Systems Initiative, Inc.
April 2013
We Have Broad Industry Support
Corporate Members
Associate Members
Welcome new members Altera, Broadcom,
Ericsson, Maxim and NVIDIA!
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© 2013 Accellera Systems Initiative, Inc.
April 2013
Promoting Accellera Systems Initiative
 Feasibility study to establish “DVCon Europe” event
- Evaluating industry interest via web survey
https://www.surveymonkey.com/s/AccelleraDVConEuropeSurvey
 Meet at ISCUG to discuss expanded event a la “DVCon India”
 ESCUG Meeting to be held at FDL Conference, September 2013
• EDS Fair, Yokohama
• Japan Users Group
• Taiwan Users Group, TBD
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© 2013 Accellera Systems Initiative, Inc.
April 2013
2013 Technical Excellence Award
• Candidates peer-nominated from across the organization
• Recognizes work by people across all working groups
Janick Bergeron
Mr. Bergeron is recognized for his
outstanding achievements made to the
Universal Verification Methodology
standardization effort and the many
technical advancements he has brought
to the field of functional verification
methodology.
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© 2013 Accellera Systems Initiative, Inc.
April 2013
Welcome
Agenda
 Current News
 About Accellera
 IEEE collaboration
 Technical activities overview
 SystemC Working Groups status
12
© 2013 Accellera Systems Initiative, Inc.
April 2013
Strong Partnership with IEEE
 IEEE Get program to allows access to EDA & IP standards worldwide
- IEEE 1666 SystemC
- IEEE 1685 IP-XACT
- IEEE 1800 SystemVerilog
 Ongoing collaboration with the IEEE Standards Association
- 1076 VHDL
- 1666 SystemC Language
- 1685 IP-XACT
- 1800 SystemVerilog (SV)
- 1801 Unified Power Format (UPF)
- 1850 Property Specification Language (PSL)
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© 2013 Accellera Systems Initiative, Inc.
April 2013
IEEE 1666 SystemC Downloads
Cumulative Downloads
12000
10000
10382
9900
9136
9095
8581
8182
7705
6575
6204
5158
4476
2000
3558
4000
5738
6000
9474
8000
0
IEEE 1666
http://standards.ieee.org/getieee/1666/download/1666-2011.pdf
Plus 47,165 downloads of IEEE1666-2005 through
January 2012
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© 2013 Accellera Systems Initiative, Inc.
April 2013
IEEE 1685 IP-XACT Downloads
Cumulative Downloads
8000
7000
6000
1000
7089
6879
6691
6547
6344
6193
6017
5802
5621
5380
5117
1495
2000
4927
4429
3000
4712
4000
6537
5000
0
IEEE 1685
http://standards.ieee.org/getieee/1685/download/1685-2009.pdf
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© 2013 Accellera Systems Initiative, Inc.
April 2013
IEEE 1800 SystemVerilog Downloads
Cummulative Downloads - 2013
5000
4690
4500
4000
3500
3000
2500
2405
2000
1500
1000
500
0
Feb
Mar
Apr
May June July
Aug Sept Oct
Nov
Dec
http://standards.ieee.org/about/get/index.html#get1800
Published on February 21, 2013
with 2,405 downloads in the first
week!
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© 2013 Accellera Systems Initiative, Inc.
April 2013
Welcome
Agenda
 Current News
 About Accellera
 IEEE collaboration
 Technical activities overview
 SystemC Working Groups status
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© 2013 Accellera Systems Initiative, Inc.
April 2013
Accellera Systems Initiative
Board of Directors
Promotions Committee
Technical Committee
Interface (ITC)
Verilog-AMS
OVL
Multi Language
IP Tagging
VIP (UVM)
Administration
IP-XACT
Schema WG
SystemC
Language
SystemC
Verification
SystemC TLM
SystemC
Synthesis
SystemC AMS
SystemC CCI
Registers
SystemRDL
UCIS
Extensions
User Group
Supported IEEE Working Groups
1076
VHDL
1801
UPF
1800
SystemVerilog
1666
SystemC
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© 2013 Accellera Systems Initiative, Inc.
Compliancy
April 2013
Standards and Initiatives at a Glance
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© 2013 Accellera Systems Initiative, Inc.
April 2013
Multi-Language Working Group
 Mission to create a standard and functional reference for interoperability of
multi-language verification environments and components
 Review requirements and develop an open source proof-of-concept for
creating a standards-based approach to combine verification environments
developed in different languages/frameworks
 Enable introduction of UVM concepts in other environments and languages
that come from legacy projects or developed with other frameworks for
beneficial reasons
 Accellera members encouraged to participate!
Sign up at www.accellera.org/apps/org/workgroup/mlwg/
Or contact us at [email protected]
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© 2013 Accellera Systems Initiative, Inc.
April 2013
Ongoing Technical Activities
Current Standards
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Verification Intellectual Property (VIP) Universal Verification Methodology (UVM) 1.1
Open Verification Library (OVL) 2.7
Verilog-AMS (V-AMS) 2.3.1
Standard Co-Emulation Modeling Interface (SCE-MI) 2.1
Unified Coverage Interoperability Standard (UCIS) 1.0
IP-XACT - Update of IEEE 1685
Intellectual Property (IP) Tagging 1.0
Multi-Language (launched)
SystemC Synthesizable Subset Draft 1.3
SystemC Analog Mixed-Signal (AMS) 2.0
SystemC Configuration, Control & Inspection (CCI Requirements)
SystemC Language Standard
SystemRDL (launched)
Transaction Level Modeling (TLM) 1.0 and 2.0
Open Source Companions:
- UVM Reference Implementation 1.1d
- SystemC Proof of Concept Library (POCL)
- SystemC Verification Library 1.0p2
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th Annual DVCon – Our flagship conference
10© 2011-2012
Accellera Systems Initiative, Inc.
SystemC AMS 2.0 standard released!
Specification
CPU
Interface
RF
Functional
AMS
Dig
2.0
Architecture
Implementation
SystemC
AMS extensions
VHDL-AMS,
Verilog-AMS
Analog/Mixed-Signal
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© 2013 Accellera Systems Initiative, Inc.
SystemC
VHDL,
Verilog
Digital HW/SW
April 2013
2.3
Features in SystemC AMS 2.0
 The Timed Data Flow now facilitates a more dynamic behavior for
AMS computations
- Time steps, data rates and delays can be changed during simulations
 Enables a tighter, yet efficient and time-accurate, synchronization for
AMS signal processing and control systems
- TDF module activations can be triggered by events from the SystemC side
 Zero time steps are now possible
- Suitable for DSP modelling or to perform (analog) iterations
 Select the most suitable mode of operation for the signal processing
functionality
- Dynamic mode of operation can be combined with traditional static mode of
operation using dedicated decoupling ports
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© 2013 Accellera Systems Initiative, Inc.
April 2013
SystemC AMS 2.0 in the industry
 Growing interest in the industry for SystemC AMS
- All supportive companies listed on the SystemC AMS quote sheet
 First commercial tools supporting SystemC AMS appear in the
market
- EDA vendors are encouraged to support the SystemC AMS 2.0 standard
in their ESL tools
- Ask your preferred EDA vendor what their plans are to support SystemC AMS !
 The AMS Working Group will continue to promote and explain the
benefits of SystemC AMS
- Ambition is to have an open source proof-of-concept made available by any of
the Accellera Systems Initiative member companies
- Technical update presented at DATE ESCUG Workshop on Friday March 22
http://www.ti.uni-tuebingen.de/ESCUGWS27-Grenoble-2013.1508.0.html
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© 2013 Accellera Systems Initiative, Inc.
April 2013
Welcome
Agenda
 Current News
 About Accellera
 IEEE collaboration
 Technical activities overview
 SystemC Working Groups status
25
© 2013 Accellera Systems Initiative, Inc.
April 2013
SystemC Language WG
 Charter:
- Responsible for the definition and development of the SystemC core language, the
foundation on which all other SystemC libraries and functionality are built.
 Current status
-
Released version 2.3 of the reference simulator to reflect IEEE 1666-2011
-
Final package reorganized to include TLM 2.0
 Plans for 2013
- Discuss new concepts affecting modeling performance
- Collect and resolve submitted issues as needed
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© 2013 Accellera Systems Initiative, Inc.
April 2013
SystemC Synthesis WG
 Charter:
To define the SystemC synthesis subset to allow synthesis of digital hardware from highlevel specifications.
 Current status
- Release of standard targeted for Q4 2013
- www.accellera.org/apps/org/workgroup/swg
 Plans for 2013
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-
Review and edit draft to make sure it fully covers the SystemC LRM
-
Decide on remaining open items
-
Start work on new topics for the second version of the standard
© 2013 Accellera Systems Initiative, Inc.
April 2013
SystemC AMS WG
 Charter:
The SystemC AMS Working Group is responsible for the standardization of the SystemC
AMS extensions, defining and developing the language, methodology and class libraries for
analog, mixed-signal and RF modeling in SystemC
 Current status
- Released the SystemC AMS 2.0 standard in March 2013
- www.accellera.org/downloads/standards/
 Plans for 2013
- Update SystemC AMS User’s Guide to explain all Dynamic TDF features,
to be released H2 2013
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© 2013 Accellera Systems Initiative, Inc.
April 2013
SystemC Control Configuration &
Inspection WG
 Charter:
To define standards that allow tools to interact with models in order to perform activities such
as configuration, debug and analysis; target topics are:
- Configuration parameters
- Command and control
- Registers
- Save and restore
 Current Status
- Currently preparing a draft of the Configuration standard for public review
- www.accellera.org/apps/org/workgroup/cciwg
 Plans for 2013
-
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Gather and incorporate feedback on the Configuration draft standard then prioritize and
start working on the Control and Inspection standards
© 2013 Accellera Systems Initiative, Inc.
April 2013
SystemC TLM WG
 Charter:
To define industry standard interfaces for interoperable transaction-level models supporting
architectural exploration, performance analysis, building virtual platforms for software
development, and functional verification.
 Current status
- Delivered TLM library update to conform the IEEE1666 2011 standard
- Integrated TLM 2.0 library with the SystemC core language package
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© 2013 Accellera Systems Initiative, Inc.
April 2013
SystemC Verification WG
 Charter:
The Verification Working Group (VWG) is responsible for defining verification extensions to
the SystemC language standard, and to enrich the SystemC reference implementation by
offering an add-on SystemC Verification (SCV) library to ease the deployment of a
verification methodology based on SystemC.
 Current Status
-
Currently updating the OSCI SCV library
-
www.accellera.org/apps/org/workgroup/vwg
 Plans for 2013
-
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To further develop and integrate verification methodologies in SystemC/TLM.
© 2013 Accellera Systems Initiative, Inc.
April 2013
Advancing Standards Together
 Share your experiences
- Visit www.accellera.org and register to post on Forums & use new UVMWorld
 Show your support
- Record your adoption of standards
 Become an Accellera member
- Join working groups
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© 2013 Accellera Systems Initiative, Inc.
April 2013
Questions?
THANK YOU
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