UC San Diego Computer Engineering
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VLSI CAD Laboratory
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UC San Diego Computer Engineering
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VLSI CAD Laboratory
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UC San Diego Computer Engineering
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VLSI CAD Laboratory
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UC San Diego Computer Engineering
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VLSI CAD Laboratory
Puneet Sharma ( [email protected] ), ECE
Puneet Gupta ( [email protected] ), ECE
Ion Mandoiu ( [email protected] ), CSE
Advisor: Prof. Andrew B. Kahng
Layout-Aware Scan-Based Delay Fault Testing
( http://vlsicad.ucsd.edu )
Proposed Solutions
Results
Delay fault testing is required with increased clock rates
and process variation; it requires careful ordering of scan
flip-flops (FFs) and insertion of dummy flip-flops in the
scan chain. We present algorithms to maximize delay fault
coverage while minimizing inserted dummy flip-flops and
total scan chain wirelength (WL). Previous works on scanbased delay fault testing have disregarded the large
(~10%) impact of scan on total on-chip wiring.
ILP for Optimal Max-Coverage Dummy Insertion
Given:
•Valid scan order, i.e., permutation  = (0, 1,…, n+1)
of F{SI, SO} with 0 = SI and n+1 = SO
•Set  of m delay fault tests with weights wt  0 t 
•Upper bound D on number of inserted dummy FFs
Formulation:
• xi=1 if dummy FF inserted
between I and i+1, else =0
•yt =1 if test t does not forbid
any of the scan chain edges
after inserting the D dummy
FFs, and =0 otherwise
• ILP (Maximum Coverage Dummy Insertion) runtimes
with CPLEX 7.0 are on the order of minutes for up to
10000 FF instances, due to sparse vectors with many
don’t-cares
• Note: ILP formulation applies to a given scan order
• Results of proposed heuristics on testcases eth and fpu
shown in bar graphs below
• Scanopt = purely WL-driven LAS
• TSP* = 100% coverage-constrained LAS
0
0
Wirelength
eth
100.50%
100.00%
100.00%
99.50%
Scanopt
TSP*
MFG
MFG*
LAS
TPMFG
99.00%
98.50%
98.00%
MFG
1 tour  empty
2 while number of fragments in tour > n+1
3
pick the cheapest edge in G, (u,v)
4
if (u,v) forms a cycle or tour contains
an edge with tail u or head v
5
then delete (u,v) from G
6
else
7
if wirelength of (u,v) > threshold
8
then delete (u,v) from G
9
else
10
include (u,v) in tour
11
remove vector pairs incompatible
with (u,v) from F
12
update costs of all edges in G
fpu
120.00%
Scanopt
TSP*
MFG
MFG*
LAS
TPMFG
80.00%
60.00%
40.00%
20.00%
97.50%
0.00%
97.00%
Coverage
eth
fpu
Tradeoff between wirelength and faults made incompatible
25,000,000
Wirelength
20,000,000
15,000,000
Series1
Series2
10,000,000
5,000,000
Algorithm Multi Fragment Greedy (MFG)
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
MFG*: MFG with Thresholded WL-Coverage Control
• Modification of MFG, with an edge eligible to be included
in the tour only if a linear combination of WL and faults
made incompatible by it is less than a given threshold
Layout-Aware Scan (LAS): Combined WL +
Coverage objective
• Edge cost = linear combination of WL and #faults
incompatible with edge
• Iterated k-opt based (asymmetric) TSP heuristic
Future Directions
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VLSI CAD Laboratory
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UC San Diego Computer Engineering
(*not discussed in this poster)
VLSI CAD Laboratory
Two-Phase MFG (TPMFG):
• Phase 1: Use MFG to generate a tour that is compatible
with a large number of vector pairs, called live vectors
• Phase 2: Populate tour with edges that are compatible
with live vectors; invoke LAS with pure WL objective
• Modern test tools generate compacted vectors which
are multiple vectors collapsed into one  modified
heuristics needed to deal with resulting redundancy
• Construction of multiple scan chains may be desirable
since this can significantly reduce testing time
• Layout flows have spare sites for dummy FF insertion
(ECOs)  need spare site aware scan chain synthesis
that inserts dummies at preferred locations
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• Multi-fragment greedy (MFG) TSP heuristics to maximize
delay fault coverage with minimum WL and bounded
#dummy flip-flops
• Integer linear program (ILP) formulations:
• Optimal insertion of given #dummy FFs in a given
scan chain to maximize delay fault coverage
• WL-driven with bounded #dummy flip-flops
• Optimal insertion of a minimum number of dummy
flip-flops to guarantee 100% delay fault coverage
• Comprehensive empirical evaluation of tradeoffs among
coverage, wirelength, and #dummies tradeoffs
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Our Contributions
Observations
• Scan WL is minimum for Scanopt at cost of coverage
• Scan WL is maximum for TSP* by order of magnitude
• TPMFG WL comparable to Scanopt; coverage
comparable to TSP*
UC San Diego Computer Engineering
Incompatible faults
VLSI CAD Laboratory
VLSI CAD Laboratory
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50,000,000
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VLSI CAD Laboratory
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UC San Diego Computer Engineering
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VLSI CAD Laboratory
UC San Diego Computer Engineering
100,000,000
UC San Diego Computer Engineering
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150,000,000
200,000,000
• Edge cost in TSP = # faults incompatible with the edge
• Edge costs change dynamically as algorithm proceeds
• Scan-based testing requires scan FFs to be connected
into a scan chain that implements a shift register;
finding a good ordering is a Traveling Salesman Problem
• TSP in a Graph: Vertices = flip-flops, Edge costs
dependent on optimization objective
• Conflicting objectives for scan-based delay fault testing
• Maximize Coverage: Order FFs and insert minimum
#dummy FFs to maximize percentage of delay faults
covered (e.g., achieve 100% coverage)
• Minimize Wirelength: Order FFs to minimize total
wiring overhead of scan chain implementation
• Previous work: optimize one objective, ignore the other!
Our Goal: Maximize delay fault coverage while
minimizing wirelength and # of dummy flip-flops
200,000,000
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VLSI CAD Laboratory
800,000,000
Scanopt
TSP*
MFG
MFG*
LAS
TPMFG
VLSI CAD Laboratory
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1,000,000,000
400,000,000
Multi-Fragment Greedy (MFG) Heuristic
Given:
• FF placement, test vector pairs, max #dummy FFs
Output:
• Scan order with low wirelength, high coverage
250,000,000
Scanopt
TSP*
MFG
MFG*
LAS
TPMFG
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UC San Diego Computer Engineering
1,200,000,000
600,000,000
Basic Optimization Framework: Traveling Salesman
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300,000,000
1,400,000,000
UC San Diego Computer Engineering
• Sequentially apply initialization, launch test vector pairs
that differ by 1-bit shift
• A vector pair induces constraints on scan ordering
(= how FFs are chained to form a shift register); vector
pairs with more “don’t cares” create fewer constraints
• Two FFs may always be adjacent in the scan chain if we
insert a dummy FF (which acts as buffer) between them
• Coverage = percentage of faults tested using a given
scan ordering
350,000,000
1,600,000,000
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Background: Scan-Based Delay Fault Testing
VLSI CAD Laboratory
Abstract
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UC San Diego Computer Engineering
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( This project is supported by MARCO GSRC )
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UC San Diego Computer Engineering
VLSI CAD Laboratory
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