Regular Flow Line Models for
Semiconductor Cluster Tools:
A Case of Lot Dependent Process Times
James R. Morrison
Assistant Professor - KAIST
Industrial & Systems Engineering
©2009 – James R. Morrison – IEEE CASE 2009 – August 25, 2009
Presentation Outline
• Motivation
• System description: Clustered photolithography tools & flow
line model
• Recursions for wafer delay & extensions
• Computation
• Application to a clustered photolithography tool
• Concluding remarks
©2009 – James R. Morrison – IEEE CASE 2009 – August 25, 2009 - 2
Motivation (1)
• Fab simulation is very commonly used in semiconductor mfg
– Assess implications of changes to equipment & operations
– Trade-offs between model fidelity/data collection and computation
• Existing fab-level simulation models
– Simplified equipment representation is good for computation
– Generally of adequate fidelity for most purposes
– Detailed wafer robot models NOT used
• Industry trends: Render existing simulation models obsolete
– Cluster tools have become increasingly more common
– Anticipated 450 mm wafer era and/or many products
Image source:
©2009 http://www.semiconductor-design.com/uploads/images/wafer.jpg
– James R. Morrison – IEEE CASE 2009 – August 25, 2009 - 3
Motivation (2)
• Current equipment models do NOT well address
– Internal wafers buffers & state dependent setups
– These are common in photolithography clusters!
• Need expressive yet computationally tractable equipment
models of semiconductor manufacturing equipment
• Goals
–
–
–
–
Develop models for cluster tools (clustered photolithography)
Expressive: Incorporate internal wafer buffers & setups, transient
Tractable: Ignore wafer transport robot & appeal to system structure
Practical: High fidelity when describing actual tool behavior
Image©2009
source:–http://www.fabtech.org/
James R. Morrison – IEEE CASE 2009 – August 25, 2009 - 4
System Description: Clustered Photolithography
• Conceptual diagram of a clustered photolithography tool
Pre-scan track
Wafers
Enter
Process 2:
3 modules
P1
P1
P2
P2
Buffer
Scanner
P6
P4
P3
P5
P4
P2
Bottleneck
process
Wafer handling robots
P11
Wafers
Exit
P11
P11
P9
P10
P8
P8
P9
P7
P8
Post-scan track
Buffer
• Internal wafer buffer may be present before/after the scanner
• Setups are of two types
– Pre-scan track: Can start only after all of its modules are empty
– Scanner: Setup starts once the first wafer arrives
©2009 – James R. Morrison – IEEE CASE 2009 – August 25, 2009 - 5
System Description: Flow Line Model (1)
• Modeling relaxations
– Ignore wafer transport robot except for addition to process time
– Process 2 is modeled as 3 modules each with 1/3 original process time
– Each buffer space modeled as a server with zero process time
…
Wafers
Enter
Pre-scan track
Buffer Scanner
Wafers
Post-scan track
• Process times are deterministic, but wafer class dependent
– tjk, for module j an d wafer class k (there are K classes)
• To enable the analysis, we make further assumptions
– Restrictive, but as we will see, they still allow for high fidelity
©2009 – James R. Morrison – IEEE CASE 2009 – August 25, 2009 - 6
Exit
System Description: Flow Line Model (2)
• Let xj(w) := start time of wafer w in module mj
• Let aw := arrival time of wafer w to the queue
• Assume wafers are served in a FIFO manner (this can be
relaxed easily)
• There are M modules in the system
• Wafer advancement in the flow line obeys the elementary
evolution equations
x1 ( w)  max aw , x2 ( w  1)

( w)  max x
x j ( w)  max x j 1 ( w)  t
xM
c ( w)
j 1

, x j 1 ( w  1)
c ( w)
c ( w)
(
w
)

t
,
x
(
w

1
)

t
M 1
M 1
M
M

©2009 – James R. Morrison – IEEE CASE 2009 – August 25, 2009 - 7
FS: Full
Simulation
System Description: Flow Line Model (3)
• Assumption A1: Service times between wafer class
tj1
…
m1
m2
m3
m4
mM-3 mM-2 mM-1 mM
tjk = hk tj1 , 0 < hk < 1
tjk
…
m1
m2
m3
m4
mM-3 mM-2 mM-1 mM
©2009 – James R. Morrison – IEEE CASE 2009 – August 25, 2009 - 8
System Description: Flow Line Model (4)
• Definition: Dominating Modules. For each wafer, the
modules that have strictly greater process time than all
preceding modules
tj1
…
m1
m2
m3
m4
mM-3 mM-2 mM-1 mM
• Note: They are the same for all wafers by Assumption A1
• Definition: Channel. The modules including and between any
two adjacent dominating modules
©2009 – James R. Morrison – IEEE CASE 2009 – August 25, 2009 - 9
System Description: Flow Line Model (5)
• Assumption A2: Service times in the channels decay
geometrically in each channel at constant rate h = h1*…* hK
h = 1/2
tj1
…
m1
m2
m3
m4
mM-3 mM-2 mM-1 mM
• This assumption guarantees that wafers will not experience
contention unless all downstream modules are full
©2009 – James R. Morrison – IEEE CASE 2009 – August 25, 2009 - 10
Recursions for Wafer Delay (1)
•
•
•
•
•
Terminology:
dj(w) := delay wafer w experiences in module mj
Ya(w) := total delay wafer w experiences in channel-a
Sa(w) := max delay wafer w can experience in channel-a
xj(w) := start time of wafer w in module mj
• Key Result 1: Under Assumptions A1 and A2,
• where Y(0) = 0, a0 = -∞, d0(0) = 0, d1(0) = 0. Further,
©2009 – James R. Morrison – IEEE CASE 2009 – August 25, 2009 - 11
Recursions for Wafer Delay (2)
• The following features can be incorporated:
– Wafers arrive in batches called lots (batch arrivals – wafer lots)
– Track setups
– Setups at the bottleneck module (scanner)
• Key Result 2: The equations for each channel can be strung
together to give recursions for the wafer delay in the entire
flow line
• Features of the results
– Don’t have to conduct full simulation (FS)
– Simply keep track of the state of each channel
©2009 – James R. Morrison – IEEE CASE 2009 – August 25, 2009 - 12
Computational Complexity
• Key Result 3: Allow setups and batch arrivals of wafers
– Let G be the number of lots, each with W wafers
– Let B be the number of modules
– Let K be the number of classes
Method
FS
Result 1
# of Add
0
K(K-1)(B-1)
# of Mult
0
0
– Computations for initialization
Method
FS
Result 1
# of Add
GWB-1
27G+9G(W-2)
# of Max
GWB-B
8G+2G(W-2)
– Computations for recursions
©2009 – James R. Morrison – IEEE CASE 2009 – August 25, 2009 - 13
Application to a Clustered Photolithography Tool (1)
•
•
•
•
Let K = 20 classes of lots
W = 12 wafers/lot
B = 40 modules (about right for a clustered scanner with buffer)
Want to simulate the system for G wafer lots
Method # of Add # of Mult
FS
0
0
Result 1 10898
0
Computation for initialization
Method # of Add # of Max
FS
480G-1 480G-40
Result 1 117G
28G
Computation for recursion
• FS requires approximately 960G/145G = 6.6 times more
computation
©2009 – James R. Morrison – IEEE CASE 2009 – August 25, 2009 - 14
Application to a Clustered Photolithography Tool (2)
• How good is the model when compared against data from a real
tool?
• Throughput accurate to within 1%
• Cycle time accurate to within 4%
• Quite acceptable for use in fab level simulation
©2009 – James R. Morrison – IEEE CASE 2009 – August 25, 2009 - 15
Concluding Remarks
• Semiconductor manufacturing environment & needs
– Increase in setups, product diversity & transient behavior
– Simulation is the tool of choice to assess changes at the fab level
– Simulation models do not well address such features in key tools
• Developed a flow line model for cluster tools
• Computationally, the method can be more efficient than full
simulation for typical clustered scanners
• Future work
– Simplified models: Can we improve computation with minimal loss of
fidelity?
©2009 – James R. Morrison – IEEE CASE 2009 – August 25, 2009 - 16