Topics
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•
•
•
Buses and networks-on-chips.
Networks-on-chips.
Data paths.
Subsystems as IP.
Modern VLSI Design 4e: Chapter 6
Copyright  2008 Wayne Wolf
Bus-based systems
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A bus is a common connection:
box1
box2
box3
ctrl
data
Modern VLSI Design 4e: Chapter 6
Copyright  2008 Wayne Wolf
Bus circuits
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•
•
Cannot support full connectivity between
all data path elements—must choose
number of transfers per cycle allowed.
A bus circuit is a specialized multiplexer
circuit.
Two major choices: pseudo-nMOS,
precharged.
Modern VLSI Design 4e: Chapter 6
Copyright  2008 Wayne Wolf
Pseudo-nMOS bus circuit
Modern VLSI Design 4e: Chapter 6
Copyright  2008 Wayne Wolf
Precharged bus circuit
Modern VLSI Design 4e: Chapter 6
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Three-state bus
Modern VLSI Design 4e: Chapter 6
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Asynchronous timing constraints
•
Must satisfy setup, hold times.
adrs
Setup time
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Hold time
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Bus system design
•
Requirements:
– Imposed by the other side of the system.
•
Constraints:
– Imposed by this side of the system.
requirements
a
b
constraints
Modern VLSI Design 4e: Chapter 6
Copyright  2008 Wayne Wolf
Views of the bus
•
Hardware:
D
Q
a
D
Q
b
Combinational
logic
Modern VLSI Design 4e: Chapter 6
Copyright  2008 Wayne Wolf
Views of bus system, cont’d.
•
Timing diagram:
x
y
x
D Q
a
Modern VLSI Design 4e: Chapter 6
D Q
y
b
Combinational
logic
Copyright  2008 Wayne Wolf
Bus protocols
•
Basic transaction:
– four-cycle handshake.
a
b
Modern VLSI Design 4e: Chapter 6
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Handshake machine
•
Each side is an FSM (possibly
asynchronous):
Go
0
a
ack
Modern VLSI Design 4e: Chapter 6
enq
enq
1
0
ack
b
1
ack
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Basic protocols
•
Handshake transmits data:
Modern VLSI Design 4e: Chapter 6
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Box 1 logic
Modern VLSI Design 4e: Chapter 6
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Box 2 logic
Modern VLSI Design 4e: Chapter 6
Copyright  2008 Wayne Wolf
Bus timing
t1 = tc1 - td1 >= tr
td1 = d stable
t2 = tack1 - tc1 >= th
td2 = d not stable
tc1 = c rises
tc2 = c falls
tack1 = ack rises
t3 = tc2 - tack1 >= th
Modern VLSI Design 4e: Chapter 6
Copyright  2008 Wayne Wolf
Busses and systems
•
Microprocessor systems often have several
busses running at different rates:
CPU
mem
High-speed
I/O
Modern VLSI Design 4e: Chapter 6
bridge
Low-speed
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Basic signals in a bus
Modern VLSI Design 4e: Chapter 6
Copyright  2008 Wayne Wolf
Bus characteristics
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Physical
– Connector size, etc.
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Electrical
– Voltages, currents, timing.
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Protocol
– Sequence of events.
Modern VLSI Design 4e: Chapter 6
Copyright  2008 Wayne Wolf
Advanced transactions
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Multi-cycle transfers:
– Several values on one handshake.
– May use implicit addressing.
Modern VLSI Design 4e: Chapter 6
Copyright  2008 Wayne Wolf
PCI bus
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•
Used for box-level system interconnect.
Two versions:
– 33 MHz.
– 66 MHz.
•
Supports advanced transactions.
Modern VLSI Design 4e: Chapter 6
Copyright  2008 Wayne Wolf
PCI bus read
Modern VLSI Design 4e: Chapter 6
Copyright  2008 Wayne Wolf
Multi-rate systems
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Logic blocks
running at different
clock rates may
communicate:
– Multi-chip.
– Single-chip.
» Slow bus connects
to fast logic.
Modern VLSI Design 4e: Chapter 6
Logic 1
Logic 2
100 MHz
33 MHz
Copyright  2008 Wayne Wolf
Metastability
•
Registers capturing
transitioning
signals may take
an arbitrarily long
time to settle.
Modern VLSI Design 4e: Chapter 6
Copyright  2008 Wayne Wolf
Resynchronization
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Use cascaded registers to minimize the
chance of using a metastable value.
d
D
Q
D
Q
dout
f
Modern VLSI Design 4e: Chapter 6
Copyright  2008 Wayne Wolf
Networks-on-chips
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NoC is an on-chip interconnection
network.
– Bus is simplest case.
– Many NoCs have multiple stages.
•
Packet-based NoCs:
– Nodes connected by links.
– Packet may be divided into flits (flits are
always of equal size, packets may not be).
Modern VLSI Design 4e: Chapter 6
Copyright  2008 Wayne Wolf
Bus electrical model
core i
Length 1
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Bus delay
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Major components of delay:
– Drivers.
– Bus backbone.
– Sink capacitive loads.
•
Delay formula:
Modern VLSI Design 4e: Chapter 6
Copyright  2008 Wayne Wolf
Crossbar
•
•
Crossbar allows any
combination of
connections.
Allows arbitrary
multicasting.
Modern VLSI Design 4e: Chapter 6
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Switch-based crossbar
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Mux-based crossbar
2-to-1 mux cell
Modern VLSI Design 4e: Chapter 6
Mux tree
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Crossbar delay
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Switch-based crossbar dominated by
buffered transmission line:
•
Multiplexer-based crossbar delay:
Modern VLSI Design 4e: Chapter 6
Copyright  2008 Wayne Wolf
Network comparison
Modern VLSI Design 4e: Chapter 6
Type
Delay
Bus
O(N2)
Switch-based
crossbar
O(sqrt(N))
Mux-based
crossbar
O(log N)
Copyright  2008 Wayne Wolf
Data paths
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A data path is a logical and a physical
structure:
– bitwise logical organization;
– bitwise physical design.
•
•
Datapath often has ALU, registers, some
other function units.
Data is generally passed via busses.
Modern VLSI Design 4e: Chapter 6
Copyright  2008 Wayne Wolf
Data path logical organization
constant
shifter
Register
file
carry
out
ALU op
memory
addresses
Modern VLSI Design 4e: Chapter 6
Shift control
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Register file porting
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•
•
Register file is an SRAM.
Additional ports add area, increase access
time.
But additional ports also reduce number of
cycles required for an operation.
Modern VLSI Design 4e: Chapter 6
Copyright  2008 Wayne Wolf
Operand fetch from register file
1 port
2 ports
3 ports
First
Firstcycle
cycle
+
Third
cycle
First
cycle
Second
cycle
Second
cycle
First cycle
Modern VLSI Design 4e: Chapter 6
Copyright  2008 Wayne Wolf
Register file tradeoffs
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•
•
SRAM delay grows approximately linearly
in number of ports.
Driver area grows considerably with added
ports.
At least two ports makes sense for data
path through put.
Modern VLSI Design 4e: Chapter 6
Copyright  2008 Wayne Wolf
Data path clocking
•
Major signals:
 f1
 f2
– precharge s f1
– adrs s f2
– data v f2
Modern VLSI Design 4e: Chapter 6
Copyright  2008 Wayne Wolf
Data path timing
s f1
s f2
s f1
shifter
Register
file
s f1
s f2
s f1
f1
s f2
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f2
s f1
Copyright  2008 Wayne Wolf
Typical data path structure
Slice includes one bit of function units,
connected by busses:
registers
Modern VLSI Design 4e: Chapter 6
shift
ALU
bus
Copyright  2008 Wayne Wolf
Bit-slice structure
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•
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Many arithmetic and logical functions can
be defined recursively on bits of word.
A bit-slice is a one-bit (or n-bit) segment
of an operation of minimum size to ensure
regularity.
Regular logical structure allows regular
physical structure.
Modern VLSI Design 4e: Chapter 6
Copyright  2008 Wayne Wolf
Abutting and pitch-matching
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•
Cells in bit-slice may be abutted
together—requires matching positions on
terminals.
Pitch-matching is designing cells to ensure
that pins are at proper positions for
abutting.
Modern VLSI Design 4e: Chapter 6
Copyright  2008 Wayne Wolf
Modern VLSI Design 4e: Chapter 6
ALU
shifter
latch
mux
constant
Register file
latch
mux
Data path floorplan
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Data path color plan
control
VDD
result
cell
Shifter input
Register file
VSS
Modern VLSI Design 4e: Chapter 6
Copyright  2008 Wayne Wolf
Subsystems as IP
•
Standards for subsystems are more
complex:
– More variations.
– More parameters.
•
•
Open Core Protocol (OCP) defines socket
for plug-and-play operation.
SPIRIT defines standard documentation
for subsystem IP.
Modern VLSI Design 4e: Chapter 6
Copyright  2008 Wayne Wolf
Wishbone standard
•
Basic unit is master-slave interface.
– Defines handshake.
•
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Interface defines CLK, ADRS, DATA,
WE, STB, ACK, CYC, RST.
Three types of bus transfers: single
read/write, block read/write,
read/modify/write.
Modern VLSI Design 4e: Chapter 6
Copyright  2008 Wayne Wolf
Functional verification
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•
•
Particularly
important for soft IP,
but performed even
for hard IP.
input
Compare design
vectors
module against
known good design.
QIP metric standard
defines verification
standards.
Modern VLSI Design 4e: Chapter 6
golden
reference
IP
module
Copyright  2008 Wayne Wolf