Digital Design with SM Charts
발표자 : 김 태 완
발표일자 : 2004.01.09
Contents

SM Charts properties

Derivation of SM Charts

Implementation of the Dice game


Alternative realizations for SM Charts using
Microprogramming
Linked State Machine
SM Charts properties





ASM (Algorithmic State Machine)
Often used to design control units for digital
systems
Useful in the H/W design of digital systems
Easier to understand the operation
Leads directly to a hardware realization
Components of SM chart
Optional
State code
xxx
State_name/
(true branch)
1
condition
(false branch)
0
Conditional
Output list
Output list
(a) State box
(b) Decision box
(c) Conditional
Output box
Example of an SM chart
One entrance path
S1/Z1Z2
Link
Path a
One state
0
SM
block
1
X1
Link
Path b
Z3 Z4
0
0
1
1
Z5
X2
1
X3
2
3
n exit paths
n
Equivalent SM Blocks
S1/Z1
0
Z2=1 if X1=0
S2 if X2=0
S3 if X2=1
1
X1
0
1
Z2
0
X2
(a)
X2
1
X1
X1
0
0
1
S3/
S2/
Z2=1 if X1=0
S2 if X2=0
S3 if X2=1
S1/Z1
Z2
Z2
S2/
S3/
(b)
Equivalent SM Charts for a combinational Network
S0/
0
S0/
A+BC
1
C
1
0
0
B
Z1
1
A
1
0
Z1
(a)
(b)
Z1=A+A`BC=A+BC
SM Block with feedback
-Every valid combination of input variables
must have exactly one exit path defined
-No internal feedback within an SM block
is allowed
S0/
S0/
0
x
1
(a) Incorrect
0
x
1
(b) Correct
Conversion of a state Graph to an SM chart
1/0
1/0
S2/
Zc
S1/
Zb
So/
Za
0/0
1/Z2
(a) State graph
0/0
0/Z1
00
S0/Za
Link 1
0
x
(b) Equivalent SM chart
1
01
S1/Zb
Link 2
0
x
1
S2/Zc
0
Z1
x
11
Link 3
1
Z2
Derivation of SM Charts



First, draw a block diagram of the system we are
controlling
Next, define the required input and output signals
to the control network
Then, construct an SM char that tests the input
signals and generates the proper sequence of
output signals
EX1.SM Chart for Binary Multiplier
S0/
0
St
1
Load
St : start, M : LSB, Ad : add,
Sh : shift, K : last shift
S1/
0
0
1
M
Sh
Ad
K
S2/Sh
1
S3/Done
1
K
0
EX1.VHDL for SM Chart
Entity Mult is
port(CLK,St,K,M: in bit;
Load,Sh,Ad,Done: out bit);
End Mult;
Architecture SMbehave of Mult is
signal State, Nextstate : integer range 0 to 3;
begin
process(St, K, M, State)
begin
Load<=‘0’ ; Sh<=‘0’ ; Ad<=‘0’ ;
case State is
when 0 => if St=‘1’ then (state 0) --- St
Load<=‘1’;
Nextstate<=1;
else Nextstate<=0;
--- St’
when 1 => if M=‘1’ then
--- M
(state 1)
Ad<=‘1’ ;
Nextstate<=2;
else
--- M’
Sh<=‘1’;
if K=‘1’ then Nextstate<=3; --- K
else Nextstate<=1;
--- K’
end if
end if
when 2 => Sh<=‘1’;
--(state 2)
if K=‘1’ then Nextstate<=3;
--- K
else Nextstate<=1;
--- K`
end if
when 3 => Done <= ‘1’; Nextstate <= 0;
--(state 3)
end case;
end process;
process(CLK)
begin
if CLK = ‘1’ then
State <= Nextstate;
--- update state on
rising edge
end if ;
end process;
End SMbehave ;
EX2.Dice Game
Rule


The player wins if the sum is 7 or 11
The player loses if the sum is 2,3,12
otherwise, the sum is referred to as a point and roll again
The second or subsequent,
the player wins if the sum equals the point
the player loses if the sum is 7,
Otherwise, the player roll again until player wins or loses
EX2.Dice Game
Display
DiceGame Module
Display
Rb
1-to-6
Counter
1-to-6
Counter
Roll
Reset
D7
Adder
Control
Win
Test
Logic
Sum
D711
D2312
Point
Register
Comparator
Eq
Sp
<Block Diagram for Dice Game>
Lose
Flowchart for Dice Game
Roll dice
Y
N
Sum =
7 or 11
N
Sum =
2,3,12
Y
Store sum in
Point register
Roll dice
Y
Sum =
Point
N
Sum = 7
N
Y
Win
Y
Reset
Lose
N
N
Reset
Y
S0 /
SM chart for Dice Game
0
1
S1 /
Roll
1
Press and Release
Rb
Rb
0
1
D711
0
D2312
1
0
S0 : No button
S3/Lose
Sp
Reset
S1 : Button Pressed
S4 /
0
S2 : Win
S3 : Lose
Roll
S4 : No button
1
S5 : Button Pressed
1
1
Reset
Rb
1
S5 /
Rb
0
Eq
0
S2 / Win
0
1
D7
1
0
0
Behavioral Model for Dice Game
Entity DiceGame is
port (Rb, Reset, CLK: in bit;
Sum: in integer range 2 to 12;
Roll, Win, Lose: out bit);
End DiceGame;
Library BITLIB;
Use BITLIB.bit_pack.all;
Architecture DiceBehave of DiceGame is
signal State, Nextstate: integer range 0 to 5
signal Point: integer range 2 to 12;
signal Sp: bit;
begin
process(Rb, Reset, Sum, State)
begin
Sp<=‘0’ ; Roll<=‘0’ ; Win<=‘0’ ; Lose<=‘0’ ;
case State is
when 0 => if Rb=‘1’ then Nextstate<=1; end if;
when 1 =>
if Rb=‘1’ then Roll<=‘1’;
elsif Sum =7 or Sum=11 then Nextstate<=2;
elsif Sum=2 or Sum=3 or Sum=12 then
Nextstate<=3;
else Sp<=‘1’ ; Nextstate<=4;
end if;
Behavioral Model for Dice Game
when 2 => Win<=‘1’;
if Reset=‘1’ then Nextstate<=0; end if ;
when 3 => Lose<=‘1’;
if Reset=‘1’ then Nextstate<=0; end if ;
when 4 => if Rb=‘1’ then Nextstate<=5; end if
when 5 =>
if Rb=‘1’ then Roll<=‘1’;
elsif Sum=7 then Nextstate<=3 ;
else Nextstate<=4;
end if;
end case;
end process;
process(CLK)
begin
if rising_edge(CLK) then
state<=Nextstate;
if Sp=‘1’ then Point<=Sum; end if;
end if;
end process;
end DiceBehave;
Complete Dice Game
Entity Game is
port(Rb, Reset,Clk : in bit; Win, Lose: out bit);
component Dicegame
port(Rb, Reset,Clk : in bit;
end Game;
Architecture Play of Game is
component Counter
port(Clk, Roll : in bit; Sum :
out integer range 2 to 12);
end component;
Sum : out integer range 2 to 12;
Roll, Win, Lose : out bit);
end component;
signal roll1 : bit;
signal sum1: integer range 2 to 12;
begin
Dice:Dicegame
port map(Rb,Reset,Clk,sum1,roll1,Win,Lose);
Counter port map(Clk,roll1,sum1);
end Play1;
Implementation of Dice game
Rb
Reset
D711
D7
D2312
Eq
Win
Lose
Roll
Sp
PLA
C
B
C+
D
Q
B+
CK
D
A+
CK
D
Q
A
Q
CK
Clock
<PLA Realization of Dice Game Controller>
PLA Table for Dice Game
ABC
Rb
Reset
D7
D711
D2312
Eq
A+
B+
C+
Win
Lose
Roll
Sp
1
000
0
-
-
-
-
-
0
0
0
0
0
0
0
2
000
1
-
-
-
-
-
0
0
1
0
0
0
0
3
001
1
-
-
-
-
-
0
0
1
0
0
1
0
4
001
0
-
-
0
0
-
1
0
0
0
0
0
1
5
001
0
-
-
0
1
-
0
1
1
0
0
0
0
6
001
0
-
-
1
-
-
0
1
0
0
0
0
0
7
010
-
0
-
-
-
-
0
1
0
1
0
0
0
8
010
-
1
-
-
-
-
0
0
0
1
0
0
0
9
011
-
1
-
-
-
-
0
0
0
0
1
0
0
10
011
-
0
-
-
-
-
0
1
1
0
1
0
0
11
100
0
-
-
-
-
-
1
0
0
0
0
0
0
12
100
1
-
-
-
-
-
1
0
1
0
0
0
0
13
101
0
-
0
-
-
0
1
0
0
0
0
0
0
14
101
0
-
1
-
-
0
0
1
1
0
0
0
0
15
101
0
-
-
-
-
1
0
1
0
0
0
0
0
16
101
1
-
-
-
-
-
1
0
1
0
0
1
0
17
110
-
-
-
-
-
-
-
-
-
-
-
-
-
18
111
-
-
-
-
-
-
-
-
-
-
-
-
-
Maps Derived from the previous table
A+ = A’B’CRb’D’711D’2312+AC’+ARb+AD’7Eq’,
B+ = A’B’CRb’(D711+D2312)+Breset’+ACRb’(Eq+D7)
C+ = B’Rb+A’B’CD’711D2312+BCReset’+ACD7Eq’,
Win = BC’,
Lose = BC,
Sp = A’B’CRb’D’711D’2312
Roll = B’CRb
Data Flow Model for Dice Game
architecture Dice_Eq of DiceGame is
signal Sp, Eq, D7, D711, D2312 : bit : =‘0’;
signal DA, DB, DC, A, B, C, : bit : =‘0’;
signal Point : integer range 2 to 12 ;
begin
process(CLK)
begin
if rising_edge(CLK) then
A<=DA; B<=DB; C<=DC;
if Sp=‘1’ then Point<=Sum; end if;
end if
end process ;
Data Flow Model for Dice Game
Win <=B and not C:
Lose <=B and C;
Roll <= not B and C and Rb;
Sp <= not A and not B and C and not Rb and not D711 and not D2312;
D7 <=‘1’ when Sum=7 else ‘0’;
D711 <=‘1’ when (Sum=11) or (Sum=7) else ‘0’;
D2312<=‘1’ when (Sum=2) or (Sum=3) or (Sum=12) else ‘0’;
Eq
<=‘1’ when Point=Sum else ‘0’;
DA
<= (not A and not B and C and not Rb and not D711 and not D2312) or
(A and not C) or (A and Rb) or (A and not D7 and not Eq)
DB
<=( (not A and not B and C and not Rb) and (D711 or D2312) ) or (B and not Reset)
or ( (A and C and not Rb) and (Eq or D7) );
DC <= (not B and Rb) or (not A and not B and C and not D711 and D2312) or (B and C
and not Reset) or (A and C and D7 and not Eq);
End Dice_Eq;
Alternative realizations for SM Charts using Microprogramming
<Control Network Using an Input MUX to Select the Next State>
PLA or ROM or PAL
TEST NSF NST OUTPUT
Register
Inputs
．
．
MUX1
MUX2
◁ The only input to PLA come from state register
◁ Test controls MUX1 with inputs
◁ NSF or NST decided by input’s BOOLEAN
(NST: Next State True)
◁ Must have only Moore outputs (Outputs depend on only current state)
Linked State Machine



A sequential machine becomes large and complex,
Desirable to divide the machine into several smaller machines linked together.
Each of the smaller machines is easier to design and implement.
Machine A
(calling machine)
SOME
STATES
Machine B
(called machine)
IDLE
ZA
SA / ZA
0
ZB
1
OTHER
STATES
1
OTHER
STATES
SB/ ZB
0