Lecture 10
u Logistics
n HW3 due Friday (cover materials up to this lecture)
n Lab3 going on this week
n Midterm 1: a week from today --- material up to this lecture
u Last lecture
n Don’t cares
n POS minimization with K-map
n K-maps design examples
u Today
n "Switching-network" logic blocks (multiplexers/demultiplexers)
CSE370, Lecture 10
1
Switching-network logic blocks
u Multiplexer (MUX)
n Routes one of many inputs to a single output
n Also called a selector
u Demultiplexer (DEMUX)
n Routes a single input to one of many outputs
n Also called a decoder
multiplexer
control
CSE370, Lecture 10
demultiplexer
We construct these
devices from:
• logic gates
• networks of transistor switches
control
2
The “WHY” slide
u Multiplexers/Demultiplexers
n If you had the ability to select which input to operate, the same part
of a circuit can be used multiple times. So if you have a lot of
inputs and all of them are supposed to go through same complex
logic functions, you can save a lot of space on your circuit board by
using a multiplexer.
n Then you will also need a demultiplexer to decode the output
coming out in serial into separate output ports.
CSE370, Lecture 10
3
“WHY”: Sharing complex logic functions
u Share an adder: Select inputs; route sum
A0
Sa
A1
B0
B1
MUX
MUX
A
B
Sb
multiple inputs
single adder
Sum
Ss
DEMUX
Z0
CSE370, Lecture 10
multiple output destinations
Z1
4
Multiplexers
u Basic concept
n
n 2 data inputs; n control inputs ("selects"); 1 output
n
n Connects one of 2 inputs to the output
n “Selects” decide which input connects to output
n Two alternative truth-tables: Functional and Logical
Functional truth table
Example: A 2:1 Mux
Z = SIn1 + S'Ino
S
0
1
I0
Z
S
I1
CSE370, Lecture 10
Z
In0
In1
Logical truth table
In1
0
0
0
0
1
1
1
1
In0
0
0
1
1
0
0
1
1
S
0
1
0
1
0
1
0
1
Z
0
0
1
0
0
1
1
1
5
Multiplexers (con't)
u 2:1 mux:
Z = S'In0 + SIn1
u 4:1 mux:
Z = S0'S1'In0 + S0'S1In1 + S0S1'In2 + S0S1In3
u 8:1 mux:
Z = S0'S1'S2'In0 + S0'S1S2In1 + ...
I0
I1
2:1
mux
S0
Z
I0
I1
I2
I3
4:1
mux
S0 S1
Z
I0
I1
I2
I3
I4
I5
I6
I7
8:1
mux
Z
S0 S1 S2
CSE370, Lecture 10
6
Logic-gate implementation of multiplexers
2:1 mux
4:1 mux
I0
I0
S
Z
I1
I1
Z
I2
Z
CSE370, Lecture 10
I3
S0
S1
7
Cascading multiplexers
u Can form large multiplexers from smaller ones
n Many implementation options
8:1 mux
I0
I1
I2
I3
I4
I5
I6
I7
8:1 mux
4:1
mux
2:1
mux
4:1
mux
S0 S1
S2
Z
I0
I1
2:1
mux
I2
I3
2:1
mux
I4
I5
2:1
mux
I6
I7
2:1
mux
S0
CSE370, Lecture 10
4:1
mux
Z
S1 S2
8
Multiplexers as general-purpose logic
u A 2n:1 mux can implement any function of n variables
n A lookup table
n–1
n A 2
:1 mux also can implement any function of n variables
u
Example: F(A,B,C) = m0 + m2 + m6 + m7
= A'B'C' + A'BC' + ABC' + ABC
= A'B'(C') + A'B(C') + AB(0) + AB(1)
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
C
0
1
0
1
0
1
0
1
CSE370, Lecture 10
F
1
0
1
0
0
0
1
1
C'
C'
0
1
1
0
1
0
0
0
1
1
0
1
2
3
4 8:1 MUX
5
6
7
S2 S1 S0
A
B
C
F
C'
C'
0
1
0
1
2 4:1 MUX
3
S1 S0
A
F
B
9
Multiplexers as general-purpose logic
u Implementing a 2n-1:1 mux as a function of n variables
n (n-1) mux control variables S0 – Sn–1
n One data variable Sn
n Four possible values for each data input: 0, 1, Sn, Sn'
n Example: F(A,B,C,D) implemented using an 8:1 mux
AB
CD 00
C
A
01 11 10
00 1
0
1
1
01
1
0
0
0
11
1
1
0
1
10
0
1
1
0
B
CSE370, Lecture 10
D
Choose A,B,C as
control variables
Choose D as a
data variable
1
D
0
1
D'
D
D'
D'
0
1
2
F
8:1
3
MUX
4
5
6
7
S2 S1 S0
A
B
C
10
Demultiplexers (DEMUX)
u Basic concept
n
n Single data input; n control inputs (“selects”); 2 outputs
n
n Single input connects to one of 2 outputs
n “Selects” decide which output is connected to the input
n When used as a decoder, the input is called an “enable” (G)
1:2 Decoder:
Out0 = G  S'
Out1 = G  S
CSE370, Lecture 10
2:4 Decoder:
Out0 = G  S1'  S0'
Out1 = G  S1'  S0
Out2 = G  S1  S0'
Out3 = G  S1  S0
Out0
Out1
Out2
Out3
Out4
Out5
Out6
Out7
3:8 Decoder:
= G  S2'  S1'  S0'
= G  S2'  S1'  S0
= G  S2'  S1  S0'
= G  S2'  S1  S0
= G  S2  S1'  S0'
= G  S2  S1'  S0
= G  S2  S1  S0'
= G  S2  S1  S0
11
Logic-gate implementation of demultiplexers
1:2 demux
2:4 demux
G
G
Out0
Out1
Out0
S
Out2
Out1
Out3
CSE370, Lecture 10
S1
S0
12
Demultiplexers as general-purpose logic
u A n:2n demux can implement any function of n variables
n DEMUX as logic building block
n Use variables as select inputs
n Tie enable input to logic 1
n Sum the appropriate minterms (extra OR gate)
1
0
1
2
3:8 3
Demux 4
5
6
7
S2 S1 S0
A
CSE370, Lecture 10
B
A'B'C'
A'B'C
A'BC'
A'BC
AB'C'
AB'C
ABC'
ABC
demultiplexer “decodes”
appropriate minterms
from the control signals
C
13
Demultiplexers as general-purpose logic
Example
F1 = A'BC'D + A'B'CD + ABCD
F2 = ABC'D' + ABC
F3 = (A'+B'+C'+D')
Enable = 1
CSE370, Lecture 10
0
1
2
3
4
5
6
7
4:16 8
Demux 9
10
11
12
13
14
15
A'B'C'D'
A'B'C'D
A'B'CD'
A'B'CD
A'BC'D'
A'BC'D
A'BCD'
A'BCD
AB'C'D'
AB'C'D
AB'CD'
AB'CD
ABC'D'
ABC'D
ABCD'
ABCD
F1
F2
F3
A B C D
14
Cascading demultiplexers
u 5:32 demux
F
0
2:4 1
Demux 2
S1 S0 3
A
CSE370, Lecture 10
B
0
1
2
3:8 3
Demux 4
5
6
7
S2 S1 S0
0
1
2
3:8 3
Demux 4
5
6
7
S2 S1 S0
C
D
E
A'B'C'D'E'
ABCDE
0
1
2
3
3:8
Demux 4
5
6
7
S2 S1 S0
0
1
2
3:8
3
Demux 4
5
6
7
S2 S1 S0
C
D
A'BC'DE'
AB'C'D'E'
AB'CDE
E
15
Programmable logic (PLAs & PALs )
u Concept: Large array of uncommitted AND/OR gates
n Actually NAND/NOR gates
n You program the array by making or breaking connections
í Programmable block for sum-of-products logic
• • •
inputs
AND
array
product
terms
OR
array
outputs
• • •
CSE370, Lecture 10
16
All two-level logic functions are available
u You "program" the wire connections
A 3-input, 5-term,
4-function PLA
CSE370, Lecture 10
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