Invited Paper
Laser-assisted ultrathin bare die packaging: a route to a new class of
microelectronic devices
Val R. Marinov*a,b, Orven Swensona,c, Yuriy Atanasova, Nathan Schnecka
a
Center for Nanoscale Science and Engineering, bDept. of Ind. and Manuf. Eng.; cDept. of Physics,
North Dakota State University, 1301 12th Avenue North, Fargo, ND USA 58102
ABSTRACT
Ultrathin flip-chip semiconductor die packaging on paper substrates is an enabling technology for a variety of extremely
low-cost electronic devices with huge market potential such as RFID smart forms, smart labels, smart tickets, banknotes,
security documents, etc. Highly flexible and imperceptible dice are possible only at a thickness of less than 50 µm,
preferably down to 10-20 µm or less. Several cents per die cost is achievable only if the die size is ≤ 500 µm/side. Such
ultrathin, ultra-small dice provide the flexibility and low cost required, but no conventional technology today can
package such die onto a flexible substrate at low cost and high rate. The laser-enabled advanced packaging (LEAP)
technology has been developed at the Center for Nanoscale Science and Engineering, North Dakota State University in
Fargo, North Dakota, to accomplish this objective. Presented are results using LEAP to assemble dice with various
thicknesses, including 350 µm/side dice as thin as 20 µm and less. To the best of our knowledge, this is the first report of
using a laser to package conventional silicon dice with such small size and thickness. LEAP-packaged RFID-enabled
paper for financial and security applications is also demonstrated. The cost of packaging using LEAP is lower compared
to the conventional pick-and-place methods while the rate of packaging is much higher and independent of the die size.
Keywords: Laser-assisted die transfer, ultrathin die, advanced packaging of bare die, economics of laser die transfer
1. INTRODUCTION
1.1 Ultrathin ultra-small chips in paper: the ultimate cost-efficient approach
A technology gap between semiconductor technology and electronics packaging exists. While the semiconductor
technology continues to evolve at high growth rates, typically doubling in functionality every couple of years, the
advances in electronics packaging have fallen behind. Traditional electronics packaging methods are quickly reaching
their limits in size, cost, and performance1. The chip packages and the methods used to interconnect them are costly and
bulky and, in most cases, simply not applicable to one rapidly evolving class of electronics products – the extremely
low-cost, disposable electronics packaged on flexible substrates. The ultrathin (< 30 µm) and ultra-small (< 500 µm per
side) semiconductor dice are of particular importance for these applications. RFID tags, financial and security paper,
lottery and other tickets, electronic paper, foldable e-devices, micro LEDs, and similar are just a few examples of lowcost, often disposable electronic products with a huge market potential and the power to transform society in more than
one aspect. With product volumes customarily measured in billions, the product cost is often the decisive factor that
determines the success or failure of these products.
The market potential of the ultra-small, ultrathin chip technology is enormous. According to the market research
company IDTechEX the value of the entire RFID market in 2012 was $7.67 billion, up from $6.51 billion in 20112. This
number does not include some of the non-conventional future RFID applications such as RFID-enabled banknotes.
Virtually every country in the world uses some form of banknotes as currency. Using RFID technology, a chip could be
placed inside banknotes in order to reduce or possibly eliminate the effectiveness of counterfeiting3. The banknotes
could be passed through a reader to check the legitimacy of the banknotes, ensuring legal tender. The European Central
Bank4 and the Bank of Japan5 have been considering embedding chips into the banknotes for years. Another exciting
new application with a huge market potential is RFID financial and security papers. Smart forms, which are paper forms
with RFID inlays inside them, cost 50¢ - $1.50 on the average.
* [email protected]; phone 1 701 231-8073; fax 1 701 231-7195; www.ndsu.edu/ndsu/marinov/
Laser-based Micro- and Nanopackaging and Assembly VII, edited by
Udo Klotzbach, Yongfeng Lu, Kunihiko Washio, Proc. of SPIE Vol. 8608, 86080L
© 2013 SPIE · CCC code: 0277-786X/13/$18 · doi: 10.1117/12.2004344
Proc. of SPIE Vol. 8608 86080L-1
During the last few decades, lottery tickets, including instant tickets, have become an increasingly popular form of legal
gambling in the United States. Unlike currency bills, which are printed on a specially designed paper using state-of-theart printing techniques, lottery tickets are simply printed on pasteboard and hence are prone to counterfeiting. The RFID
technology would reduce or possibly eliminate this problem. The market for these products is huge and is growing both
in North America as well as in many other countries. According to the North American Association of State and
Provincial Lotteries (NASPL, www.naspl.org), 53% of all adults in North America currently play or have played instant
games in lotteries. One of the leading suppliers of instant tickets, Pollard Banknote, prints 18 billion instant tickets
annually6. Their scratch tickets have contributed over $1.3 billion in sales. Similarly, smart tickets could be used for
large sporting and entertainment events if the RFID cost was low enough.
The use of ultra-small, ultrathin dice in the low-cost, disposable electronics is dictated by two important considerations reliability and cost.
Reliability: External bending stresses are critical for ultrathin dice as they are packaged on flexible substrates. Under a
bending load, tensile and compression strains and stresses develop in the die. The maximum engineering strain on the
outer and inner surfaces of the die, , is proportional to the die thickness and bending radius. If the bending radius, r, is
much bigger than the die thickness, t, which is usually the case, ≅ . If the thickness, t, is small enough, as in the
ultrathin dice, the resulting bending stresses are below the fracture limit of silicon, turning the intrinsically brittle and
rigid monocrystalline silicon into a flexible material. Obviously, the thinner the die the more flexible it is. At 10 µm and
less silicon acquires an excellent flexibility and unconditional mechanical stability7. This is the reason why the
recommended chip thickness for chip-in-paper applications is 25 μm or less7-9, many times smaller than the typical flipchip thickness.
Another important fact is that the strain/stress conditions change from tension on the outer surface to compression on the
inner surface and at the center of the die, along the so-called neutral plane, they become equal to zero. Therefore, if the
die is placed at or near the neutral plane, the bending stresses in the silicon will be minimized thus further reducing the
probability for fracture failure. This is best achieved by embedding the die in the substrate. The mechanical reliability of
the die depends also on its size. As Takaragi et al.10 have shown, the probability for mechanical fracture decreased by a
few orders of magnitude when the die size was reduced from 1×1 mm to about 0.4×0.4 mm.
Cost: Extensive resources have been and are spent on the RFID systems design and implementation strategies; however,
very little is being invested in the process technology for RFID-based devices1. Obviously, the presumption is that once
a great concept has hatched, the industry can figure out the most efficient way of turning it into a profitable reality.
Alas, that didn’t happen with the RFID tags or at least is happening slower than expected. Probably the single most
important reason for the stagnant market penetration of RFID technology is its cost12. The cost of a passive RFID tag
today is anywhere between $0.15 and $1.1012-15 depending on the production volume and complexity of tags. The
consensus among the industry experts is that a reduction in cost by a factor of ten is needed to make RFID technology
competitive. For example, it is expected that the cost of RFID chips in banknotes needs to start at 10 cents and then drop
to 4 cents to make them attractive for this particular application3. Interestingly, in 2004 Patrick J. Sweeney II, an
entrepreneur and technology visionary, predicted that $0.05–0.075 tags will be available by the end of 2007, brought to
the market, as he envisioned, by large Asian manufacturers16. The underlying assumption in this prediction is clear – the
cost reduction would come from mostly using cheap labor and cheap raw materials. While this line of reasoning works
for many other products, it is mostly moot when it is applied to RFID tags. The cost of labor in an RFID inlay is
negligible considering the fact that more that 70% of the total cost comes from the RFID die and the packaging
technology.
The RFID chip is the major cost component in an RFID device accounting for about 45 – 60% of the total production
cost12,17. Cost of packaging constitutes another 25 – 45%13,15,18. When it comes to chips on semiconductor wafers,
smaller is cheaper. The Seeds model used later in Section 4 (Equation 2) and the other similar models compute die yield
as a function of chip area and number of defects per wafer. Assuming the same density of defects (relatively high in
RFID wafers12), the model shows that the die yield will exponentially increase by reducing the chip size. This will in
1
A similar tendency is evident in other branches of the U.S. industry. In 2011, The President’s Council of Advisors on Science and
Technology found that the U.S. is lagging behind in manufacturing innovations relative to nations such as Germany and Japan. We are
losing leadership in manufacturing industries based on inventions and knowledge that originated in the U.S. Foreign firms now
manufacture many products invented here11
Proc. of SPIE Vol. 8608 86080L-2
turn decrease the cost per chip since the non-recurrent engineering costs will essentially remain the same. Assuming a
cost target of 1-2 cents per die for a future 5-cent tag and a wafer processing cost of $1000, a die size budget of 500
μm/side has been proposed by MIT’s Auto ID Center, an influential industry promotion group19. It is envisioned that the
RFID chip size can be reduced to 300 μm/side or less for even further cost reduction. For example, in the early 2000s,
Alien Technology, Morgan Hill, CA, experimented with 150 μm/side RFID chips assembled using their proprietary
fluidic self-assembly technology (see Section 1.2).
Another major cost component in the RFID inlay is the substrate and the antenna located on it. One substrate material
that has recently attracted significant attention is paper. Among the major benefits of this material is its cost (paper is
arguably the cheapest substrate material) and the fact that paper is recyclable, which makes the notion of “green”
electronics possible, at least for the disposable electronic products packaged on paper substrates. The use of paper in the
RFID tags would eliminate the need for a polymer inlay substrate, which will further reduce cost. Several research
groups have presented solid arguments in support of using paper and inkjet printing of RFID antennas, followed by
assembly of ICs, as a very low-cost, eco-friendly solution for fabricating RFID tags20-22.
1.2 Limitations of the current technology
Ultrathin, ultra-small chips have been around for years. For example, more than ten years ago Hitachi demonstrated a
series of ultrathin silicon-on-insulator (SOI)-based RFID chips called a “μ-chip,” including a 75 μm/side, 7.5-μm thick
RFID die10,23-25, intended for embedding in paper. Ultrathin SOI chips have been demonstrated by other groups, as
well26-29. SOI is a technology well-suited for ultrathin Si chips but it is expensive and not readily available30.
Alternatively, the ultrathin bulk Si technology has been and is still being actively investigated mostly in Europe,
especially by Fraunhofer-affiliated groups in Germany31. An excellent in-depth discussion on the ultrathin chip
technology and applications is provided by Burghartz and co-authors in a recent publication7. Most of the current
research in this area has been directed towards thinning, handling, and embedding ultrathin dice, very little has been
accomplished in chip assembly.
The question is: Since the ultra-small and ultrathin chip technology has already reached a certain level of maturity and
considering its obvious benefits, why aren’t ultrathin chips everywhere? Our thesis is that the limitations of the current
packaging technology are the major roadblock to the widespread implementation of the ultra-small, ultrathin chip
technology. The semiconductor industry is more than capable of reducing chip cost by miniaturizing the chips, but the
current packaging methods cannot handle ultra-small chips effectively and efficiently7. Others have reached the same
conclusion, most notably Noda and Usami23, the researchers behind Hitachi’s μ-chip.
Traditional assembly methods designed for thicker wafers are not very well suited for ultra-small, ultrathin chip
assembly. Various techniques, most still in the early R&D phase, have been suggested in the literature for assembly of
dice with thicknesses of around 50 μm or less31-35. The majority of the work has been done using prototype equipment
optimized for handling thin silicon, e.g., flip-chip die bonders with adapted tooling and special release tapes36-39.
Temporary carriers were suggested for supporting the thin dice during assembly40. In some instances, thin chips were
assembled using a mask aligner41.
The complications with die packaging increase exponentially when the chip thickness falls below 50 μm. There are only
a few reports in the literature describing assembly of ultrathin (30 μm or less) dice42,43 using die bonders for chips that
are relatively big in size (e.g., 5×5 mm2 chips42). Few details are available, but it’s logical to assume that, based on the
results for thicker chips, the use of die bonders for such ultrathin dice would impose substantial limitations in terms of
packaging cost and packaging rate.
The equipment that can handle ultrathin bare dice is unique and costly32. The die bonders are “pick-and-place” machines
that work by picking up bare dice with a vacuum nozzle from the carrier tape after the wafer was diced and mounted on
the tape. Picking the ultrathin die is a challenging task. If the die is not fixed to the carrier tape, stiction may become a
problem especially for components with a characteristic length of less than 300 μm44. The small forces observed on
surfaces, such as van der Waals, surface tension, and electrostatic forces do not need to be considered for large-scale
components. However, when components reduce to the scale where the gravitational force exerted on them is
comparable to the magnitude of these surface effects, pick-and-place begins to fail as a high precision, high volume
process45,46. Placement heads could conceivably be scaled and configured to approach an ultrathin component with
sufficient precision to pick it up without shattering it. However, due to the stiction effects, when the nozzle is in close
Proc. of SPIE Vol. 8608 86080L-3
proximity to a component these forces can cause a component to “jump” to the nozzle before it is in position to pick it
up. The stiction problem can be alleviated if the dice are fixed to the carrier tape using adhesives. Then, the problem
becomes how to lift the die from the adhesive film without damaging it. Various approaches using penetrating and nonpenetrating needle ejectors as well as thermal release tapes were attempted with variable success. Some of these methods
are discussed in the literature34,36,47 but in general, the conventional technique of ejecting the die from the tape with a
needle is very critical and can easily destroy the die34,48. Peng et al.49 provided evidence that a single ejecting needle can
only peel off 1 mm/side chips from the substrate when the die thickness is ≥ 37 μm (the critical thickness is smaller for
smaller chips). Additionally, as the scale of dice continues to reduce, the nozzle vacuum force alone begins to raise
concern as it causes the thin and flexible semiconductor components to flex.
The problems do not end with picking the die. Placement head down-force is used to establish contact between the die
bumps and the pads on the substrate. The ultrathin dice are so delicate that the down-force often cracks the die when it is
placed on the substrate34. The physical limitations are not the only issues with the pick-and-place assembly of ultrasmall, ultrathin chips. As discussed later (see Figure 9), the cost of packaging when using the conventional pick-andplace methods increases substantially when the die size decreases.
Some unique methods such as fluidic self-assembly (FSA)50,51 and even single bead-manipulating apparatus using micro
vacuum tweezers23 and others40,41 have been suggested as alternatives to pick-and-place assembly with various degrees
of success. FSA was heavily promoted by the Alien Technology Corp., as a technique for parallel assembly of large
numbers of bare dice that is still considered by some authors as one of the most promising solutions to the ultra-small
chip packaging dilemma8,13. In this process the bare dice with a typical size of several hundred micrometers and a flattop pyramidal shape are suspended in liquid and flowed over the receiving substrate which has correspondingly shaped
receptor holes into which the dice settle and self-align. Alien has successfully demonstrated FSA for assembly of tens of
thousands of RFID chips52. Some of the problems with FSA are related to the shape and orientation control of the dice.
Since the substrate is submerged in the processing liquid and receptors need to be precisely shaped in it, FSA is limited
in the number and type of substrate materials. Obviously, this technology is not applicable to paper-based substrates. But
maybe the biggest issue with FSA is that it places the die on the substrate face up. Subsequent post assembly processing
steps such as coverlay bonding, via hole drilling and plugging, and interconnect metallization need to be employed,
which has an adverse effect on the production cost and complicates R2R processing.
In conclusion, the conventional methods can be modified for assembling ultra-small and ultrathin dice on a flexible
substrate but they are neither effective nor efficient. Therefore, the die placement is increasingly becoming the limiting
factor for the widespread use of the ultra-small, ultrathin die. Instead of trying to adapt the conventional methods, radical
innovations in packaging techniques are required to realize the full potential of ultra-small, ultrathin chip technology.
One such innovation is the LEAP technique briefly described in the next section.
2. PRINCIPLES OF LEAP
The method identified as the flexible electronics packaging technology for with the lowest cost in high volume is the
direct-chip attach approach in which a bare semiconductor die is flip-chip assembled to a flexible substrate using
anisotropic conductive adhesives53. This method has been successfully applied for attaching RFID chips to a paper
substrate54. In our work, we attach the die using the Laser-Enabled Advanced Packaging (LEAP) method, a patentpending technology recently developed by our team at the North Dakota State University in Fargo, North Dakota and
explained in detail elsewhere55,56. LEAP is a comprehensive, wafer-to-product technique, based on using the energy of a
carefully controlled and confined laser ablation to precisely and accurately transfer and assemble semiconductor die and
other discrete components with dimensions well below those possible with the conventional robotic (“pick-and-place“)
methods. LEAP is arguably the only electronics packaging technology with a potential of bringing the production cost of
RFID tags and similar ultra-low cost products down to several cents while supporting packaging rates several times
higher than those possible with the conventional pick-and-place equipment. A central part of the LEAP technology is the
thermo-mechanical Selective Laser-Assisted Die Transfer (tmSLADT) technique, illustrated in Figure 1, which includes
the use of a dual dynamic release layer (DRL) to attach the dice, to be transferred, to a laser-transparent glass carrier.
tmSLADT is a modification of the so-called Laser-Induced Forward Transfer (LIFT) technique57,58. The basic concept of
LIFT begins with a laser-transparent carrier substrate, which has a sacrificial layer deposited on its surface. The
components to be transferred are bonded to the sacrificial layer. Once ready for transfer, the sacrificial layer is ablated by
Proc. of SPIE Vol. 8608 86080L-4
a short laser pulse through the carrier substrate to generate gases that propel the component towards a receiving substrate
placed in close proximity.
UV laser beam
UV transparent
glass carrier
dynamic
release ]
lawor
blistering layer
adhesive laver
/ /I\\
blister
receiving
substrat
7
(a)
(b)
(c)
Figure 1. (a) A schematic illustrating the principles of tmSLADT process; (b) an SEM photograph taken after die transfer
showing blisters formed in the DRL when irradiated with a scanning laser beam in a circular pattern; (c) SEM image of
670×670 μm, 50-μm thick laser-diced Si dice on the receiving substrate after tmSLADT transfer.
LIFT has been already demonstrated by Karlitskaya et al.59,60 and A. Piqué et al.61-63 for transfer of semiconductor bare
dice as an alternative to conventional pick-and-place method. LIFT has the potential to place chips with transfer rates an
order of magnitude higher than those achievable with conventional pick and place63,64. However, LIFT suffers from
significant drawbacks including low precision and accuracy of placement, something acknowledged by Karlitskaya60 and
also observed in our earlier experiments. The lower velocity thermal release LIFT makes the process more controllable
but still not precise enough64. In addition, the die size is limited in one of the more precise LIFT techniques, the thermal
release LIFT suggested by Karlitskaya60.
What makes tmSLADT different from LIFT is that it does not rely on the kinetic energy of a plume of vaporized
material or solely on the gravitational force to transfer the die. Instead, the UV laser pulse creates a blister in the
sacrificial layer, confining the vaporized material within the blister without rupturing it. The force exerted by the blister,
in addition to the gravitational force on the die, initiates the contactless die transfer from the wafer onto the receiving
substrate where the die is interconnected to the rest of the circuitry.
The original LIFT concept relies on a jet of gas to initiate the die transfer. By the nature of gas dynamics, the use of a
relatively low density gas to push a higher density component, such as a semiconductor die, results in a process which is
highly sensitive to initial conditions. Small variations in the heat absorption mechanism, irregularities in the sacrificial
layer thickness and homogeneity, presence of contamination as well as variations in the intensity profile of the laser
beam all contribute to the LIFT process being very unstable and the results highly unpredictable. In contrast, the blisters
resulting from the confined ablation in tmSLADT act as mechanical actuators, allowing for a much better control of die
placement and, as a result, more reliable and precise die transfers. This capability, unmatched by the other LIFT-based
methods, allowed us to report in 2011 the world’s first successful application of lasers for the fabrication of a functional
device (an RFID tag) based on a COTS 65-µm thick, 670-µm square bare die65. Here, we report precision placement of
18-μm thick, 350-μm square dice using our LEAP technique. To the best of our knowledge, there is no other electronics
technology, conventional or nonconventional, capable of high-rate packaging of such ultra-small, ultrathin dice.
3. CHIP-IN-PAPER APPLICATION
The problems with processing/handling ultrathin wafers, discussed extensively in the literature7,31 and also observed in
our practice, can be minimized if some of the operations are consolidated to reduce the times the ultrathin wafer is
transferred from one carrier to another before the die placement step. This minimalistic approach is in the core of our
tmSLADT process sequence, illustrated in Figure 2.
The experimental work reported in this section demonstrates the viability of LEAP for the packaging of ultrathin (< 30
µm) and ultra-small (< 500 µm/side) bare dice using as a technology demonstrator an RFID die attached to an antenna in
a chip-in-paper configuration. The reasons for selecting this particular application were: (1) the challenge of creating a
functional electronic device by embedding a semiconductor die and an antenna in a thin lightweight paper substrate with
a total thickness of ≤ 120 µm, typical for the paper used for banknotes, security documents, smart forms, etc., and (2) the
practical importance of this application and the expected significant benefits to society3,66.
Proc. of SPIE Vol. 8608 86080L-5
Mechanically ground to 50 pm wafer
Patterned etch mask
Etch mask structured
on the front side
Wafer thinned to 20 pm by RIE
on the back side
Ultrathin wafer mounted
on the UV- transparrent carrier
with a spun -on DRL
=17="
Dynamic release layer
UV- transparent carrier
,
Wafer and DRL diced by RIE,
mask stripped
UV laser pulse
Die laser-transferred to
the ceiving substr ate
using tmSLADT
Figure 2. Process sequence in the tmSLADT method illustrated for transferring 20-µm thick dice. In this example, the wafer
thickness is reduced from 50 µm to 20 µm before dicing the wafer. Wafer dicing and thinning are carried out using Reactive
Ion Etching (RIE).
fIls
Figure 3 illustrates the chip-in-paper packaging concept and the use of LEAP for its realization. The process sequence
starts with printing the antenna traces and die pads on the paper substrate. Next, the die pads are covered with a needledispensed anisotropic conductive paste (ACP), and, finally, the die is placed using the tmSLADT process (Figure 1a).
UV laser pulse i
UV- transparent carrier
/
1_1
Anisotropic Conductive Paste (ACP)
Die laser transferred to
the receiving substrate
using tmSLADT
20pm -thick diced wafer
Paper substrate with printed antenna
Pressure and heat applied to connect
the chip to the antenna pads
111111111111111111
Printed antenna /traces
20pm -thick RFID die
Anisotropic conductive adhesive
50pm -thick paper sheets
Figure 3. Chip-in-paper concept and process sequence.
The substrate is then laminated with a second sheet of paper leaving the chip and antenna embedded in the paper. The
final product is referred in this text to as an RFID-enabled financial and security paper, or, with regard to the particular
example presented here, an RFID “banknote” (Figure 8).
The experimental work was divided into two stages. Initially, a background work was performed to evaluate the die
attach using ACP and the conductor traces screen-printed on paper. The results of these experiments are presented in
Section 3.1. The discrete components used at this stage were blank silicon tiles sputtered with a thin conductive film.
Two different sizes were used, ultrathin, ultra-small 350 µm/side, 18 to 20 μm thick tiles, and 670 μm/side, 20-μm thick
tiles with area dimensions identical to those of the RFID die used in the subsequent experiments.
Proc. of SPIE Vol. 8608 86080L-6
In the second series of experiments, a number of RFID tags (antennas and functional RFID dice) were assembled on a
natural cotton-based paper substrate using the LEAP technology. Section 3.2 provides details about these experiments.
3.1 Preliminary experiments: Flip-chip assembly of thin dice on paper using ACP
Wafer carrier with DRL: The laser transparent wafer carrier used in these experiments was a 3”×1/16” fused silica disk
(CGQ-0600-10, Chemglass Life Sciences). The DRL consists of a blister layer of spin-on polyimide (PI-2525, HD
Microsystems), followed by an adhesive layer of low molecular weight polyester, formulated in house and designated as
PE755. The DRL materials were spin-coated on a SUSS RC-8 spin coater as explained elswhere55.
Wafer thinning: A COTS (100) p-type Si wafer, mechanically ground to a 50 µm thickness, was used in these
experiments. The wafer preparation started with sputtering a 0.5-µm thick Au layer on the front of the wafer, preceded
by a 30 nm thick layer of Cr for improved adhesion of the gold layer. The latter was patterned using standard
lithographic techniques into squares with 350 µm or 670 µm sides to define dice with the corresponding dimensions. The
Au and Cr layers in the streets were then etched away to expose the Si wafer in the streets.
To minimize the possibility for structural damage in the chips, additional wafer thinning from 50 µm down to 20 µm was
performed using reactive ion etching (RIE). After removal of the metal layers, the wafers were rinsed and dried and then
placed Au-side down in a Trion Phantom II RIE Plasma Etcher. The parameters used for both wafer thinning and
opening the streets in the next step are shown in Table 1.
Table 1. Dry Etch (RIE) thinning and dicing parameters for Si.
Process
Pressure, mTorr
Power, W
Base Pressure, mTorr
SF6, sccm
Thinning
300
100
100
26
Dicing
100
300
100
26
The measured etch rate resulting from these parameters was 0.85 µm/min for thinning and 1.25 µm/min for dicing. The
wafer thickness was measured using KLA Tencor P-11 contact profilometer on a separate control piece of Si wafer
placed in the etcher adjacent to the processed wafer.
After the wafer was thinned to 20 µm it was manually attached, sputtered side up, to the DRL spin-coated on the wafer
carrier. The as-prepared stack was run through an Optec DPL-24 Laminator to ensure reproducible and evenly
distributed bonding pressure between the DRL and the wafer. Lamination was carried out as follows: 1) dwelling in
vacuum for 7 min, 2) pressurizing the chamber and 3) dwelling for additional 3 min. The pressure of the laminator used
is set at 207 KPa and is non-adjustable.
Wafer dicing: After the wafer was bonded to the DRL, it was singulated into individual dice. This was accomplished
utilizing RIE with parameters shown in Table 1. After singulation was completed, the sample was inspected using a
backlit optical microscope to ensure that the streets were completely opened.
When the method described here is used for assembly of functional devices, sputtering and patterning metal films onto
the front side of the wafer will not be permissible. In this case, the street pattern can be defined by structuring a
photoresist layer with a photolithographic process and then using the structured layer as an etching mask, as shown in
Figure 2.
Substrate preparation: As mentioned before, paper was selected for this work because, compared to other flexible
substrate materials, it is less expensive, readily available, and fully recyclable. Its major disadvantages include water
absorption and sensitivity to temperature. These problems were addressed by avoiding wet processing and by using lowtemperature materials whenever possible. The US currency bills are printed on 109 µm thick, 100 g/m2, 25% linen and
75% cotton paper. A COTS material close to these specifications is the Strathmore 500 Series Marker, 50 g/m2 (approx.
56 µm thick), 100% cotton paper. Two plies of this paper laminated together provide the desired thickness of the
finished device. For some of the electrical continuity experiments, the test pads were printed on polyimide.
Test pads were created by standard screen printing technique using a stainless steel (230-0.0014) screen with 0.005
emulsion thickness and Acheson Electrodag PF-050 Ag ink. Process parameters were optimized based on silver ink
manufacturer’s recommendations. The sputtered tiles were attached using epoxy based Creative Materials EXP 2608-48
Proc. of SPIE Vol. 8608 86080L-7
anisotropic conductive paste with average particle size of 2 to 3 μm. The ACP was applied over the receiving pads using
a manual dispenser with a needle size of 125 μm. At this point, the substrates were ready for tmSLADT assembly.
Laser transfer: A schematic of the tmSLADT experimental set-up is shown in Figure 4. The laser transfer is carried out
using the third harmonic (355 nm) of a HIPPO Nd:YVO4 laser (Spectra Physics). The laser beam is directed towards the
sample holder, mounted on XYZ motion control stages, using HurryScan II laser scanhead (Scanlab). Further details
about the experimental setup are provided elsewhere56.
waveplate in
rotation stage
power meter
refractive beam shaper
Nd:YVO4
dicnroic
polarizer
beam expander
relay optics
sample holder
XYZ motion
control stages
Figure 4. tmSLADT experimental setup.
The fused silica carrier, which was prepared as outlined in the preceding paragraphs, is mounted in a specially designed
fixture on top of the receiving substrate with the DRL and singulated wafer facing down. Shims of 160 µm thickness are
used between the sample carrier and receiving substrate to provide the transfer gap. Once the substrates are mounted, the
fixture is positioned under the scanhead of the HIPPO laser for transfer. The laser transfers are accomplished by
scanning the DRL attached to the die to be transferred with a circular laser scanning pattern with parameters selected
based on results from previous experiments56,65. The laser parameters used for activating the DRL are critical to optimize
the transfer rate, and minimize the lateral or rotational displacement of the die during transfer. Operating with pulse
energies just below the rupture threshold ensures maximum blister height while still containing the hot gas generated by
the vaporized blistering layer material. The laser operating parameters were 15 kHz repetition rate and a scan speed of
300 mm/s, appropriate to create a continuous blister. For this study, a series of three concentric circles was used with
diameters of 200, 400, and 600 µm for 670×670 μm tiles. The pattern starts with the smallest circle first, and works its
way outward with a line connecting each circle. This pattern is shown in Figure 1b. The smallest die, 350×350 µm were
transferred with a single circle with a 200 µm diameter. An average power of 200 mW was used for transfer. The
transfer gap was about 180 µm.
Continuity experiments. Test patterns were produced on a 75 μm thick polyimide substrate as well as on a 56-μm thick
paper substrate and ACP was dispensed onto the die site. Each die was then transferred over uncured ACP using the
tmSLADT process, and the ACP was B-stage cured at 125o C for 3 min on a Thermolyne Mirak HP72625 hot plate. In
the next step of the assembly process, a weight of 140 g was placed over the sample and final cure of the ACP was
performed at 185 oC for 5 min. After the ACP cure step, the test sites were checked for continuity using a digital multimeter. A picture of a completed die site is shown in Figure 5.
(a)
(b)
Figure 5. An overview (a) and close-up (b) of a 670 × 670 µm conductive dummy die assembled on a test pattern. The lines
on the topside of the die indicate that part of the DRL transferred with the die, and are not ablation marks on the die itself.
The continuity checks showed resistance measurements of 2-3 Ω for accurately placed die, which is acceptable for this
application. Cross-sections of the assembled die supported the low resistance measurements and showed the application
Proc. of SPIE Vol. 8608 86080L-8
of pressure in the curing process provided a very good area of contact between the metalized portion of the die and the
silver ink of the traces. A scanning electron microscope (SEM) image of an assembled die is shown in Figure 6.
15kV
X180
100pm
Figure 6. A SEM image of a cross-sectioned 670×670 µm die assembled on a polyimide substrate.
The LEAP process was also tested and proven for ultrathin die using dummy die as thin as 18 to 20 μm and as small as
350×350 µm, assembled on paper. A total of 10 die with the aforementioned dimensions were transferred. Alignment of
these very small dice proved challenging as there is no back-light capability on the experimental set-up that is in use
currently. Nonetheless, resistance measurements showed values between 2.1 and 2.9 Ω with an average of 2.33 Ω for
well-placed die.
These initial experiments provided valuable experience and confidence in our success in producing working RFIDenabled financial & security paper.
3.2 Chip-in-paper: RFID-enabled financial & security paper
Most of the methods and materials used in the second series of experiments are identical to those described in Section
3.1. The differences are briefly described in this section.
RFID wafer: The chips used in the assembly of the functional RFID device were 670 μm/side Alien® Technology
Higgs™ 3 chips. This particular RFID chip conforms to the EPC Class 1 and Gen 2 standard. The wafer was
mechanically thinned to approximately 65 µm for this demonstration. No further thinning was attempted in order to
minimize the wafer handling and the possibility of damaging the functional chips.
Wafer dicing: After the RFID wafer was bonded to the DRL, it was singulated into individual dice using laser ablation.
The Spectra Physics HIPPO Nd:YVO4 laser third harmonic at 355 nm was used for this purpose. The laser was set to a
50 kHz repetition rate, and used at an average power of 3 W, with pulse energy of approximately 60 µJ. Utilizing a scan
speed of 400 mm/s, 20 scans were required to singulate the 65 µm thick wafer.
After singulation was completed, the sample was inspected utilizing a backlit optical microscope to ensure complete
street opening was achieved. In some cases, nearly complete dicing occurred while small tabs of Si remained intact
across the diced streets, which inhibited the transfer process. The desire for full separation must be balanced with the
harmful effects of over-scanning during dicing, as laser scanning much beyond that necessary to singulate the wafer
affects the properties of the DRL and must be monitored.
After singulating the wafer, individual dice were tested to find known-good-die (KGD) for the RFID assembly using a
Micromanipulator 8840 microprober with an Alien® Technology 9650 RFID Reader with attenuators inline. These KGD
were mapped for the tmSLADT process.
Laser transfer: After substrate and wafer preparation, the RFID die were transferred using the Spectra Physics HIPPO
Nd:YVO4 and the tmSLADT process. A custom manual-alignment fixture was used in these experiments to align the die
over the die site using a backlit microscope, since automatic alignment machine-vision equipment is not currently part of
the experimental set-up. After substrate alignment, the fixture was placed on a 3-axis stage for final alignment with the
laser. To facilitate transfer, the laser was set-up using a 15 kHz repetition rate and 500 mW of average power. The laser
scan head directed the beam in a scan pattern consisting of three concentric circles at a rate of 300 mm/s, which resulted
in a sufficient transfer rate for these experiments.
The power setting was much higher than reported in previous work56,65 to ensure transfer. Also, the transfer gap from the
active side of the die to the surface of the ACP is estimated at only 95 µm, which reduces the amount of translation
during transfer.
Proc. of SPIE Vol. 8608 86080L-9
ACP curing:: After transfer, the fixture was
w carefully removed withhout disturbingg the die. The whole paper ssubstrate
assembly (which was stretcched over a gllass substrate and
a attached onn the edges w
with Kapton® taape) was placeed on the
hot plate set to 125 °C forr approximatelly 3 min to B--stage cure thee ACP. The finnal cure was pperformed on tthe same
hotplate set to
t 185 °C with
h a 140 g weigh
ht placed on th
he assembly foor approximateely 5 min. The B-stage cure sserved to
effectively ho
old the die in place
p
for subseequent handling
g and placemennt of the weighht on top of thee assembly for the final
cure. An asseembled RFID inlay
i
on paper is shown in Figure 7.
Figure 7. An assembled RFID
R
die on a paaper substrate wiith a screen-prinnted antenna. The antenna designn follows the
he darker area suurrounding the diie) was dispenseed over a larger aarea
recommeendations suggessted by Rao et al.67. The ACP (th
to accoun
nt for the lack off precision alignm
ment features in the experimentaal setup.
Before final assembly, the RFID
R
tags werre tested for fun
nctionality andd read range. T
The details of thhe testing are liisted
later in this section.
s
Chip embedd
ding: In order to protect the chip and anteenna, the as-prrepared and tested assembly was laminated with a
second sheett of the same paper used to
o print the anttenna. Both pllies of paper w
were attached using a 3M S
Super 77
Multipurposee Adhesive. Th
he 3M adhesiv
ve was sprayed
d over the assem
mbly and the ssecond sheet oof paper was placed on
top of it; any
y trapped air was
w pushed out using a rubberr squeegee. Affter the adhesivve dried, the R
RFID “banknotees” were
cut to a size of
o 67 × 146 mm
m. Finally, artw
work was printted on both siddes using a stanndard color inkk-jet printer (Figure 8).
Functionalityy testing: The read range of each RFID baanknote was deetermined usinng an Alien® T
Technology AL
LR-9650
single antenn
na RFID readeer. Alien Tech
hnology’s Gateeway Demonsttration applicaation was usedd to determinee when a
RFID bankno
ote was readin
ng properly. Th
he attenuation was set to 0 ddB, which resuulted in an apprroximately 1 W output
power with a 6 dBi antenn
na gain. The baanknotes were placed in the radiation fieldd directly in linne with the anttenna by
hand, and heeld in several orientations
o
to determine thee maximum re ad range. The distance from
m the face of thhe RFID
reader to thee “banknote” was
w measured. Each tag was tested before aand after appliication of the ffinal paper covverlay to
determine if the assembly step
s
damaged the
t RFID IC or
o decreased thhe tag performaance. Nine out of 10 sampless worked
after initial assembly
a
with read
r
ranges varrying from 7-30”, with the m
majority of the ttags in the 15-225” range. Onee tag was
damaged durring assembly of
o the cover lay
yer and did nott read afterwarrd.
The remaind
der of the tags did not show any
a noticeable reduction in pperformance affter assembly oof the cover laayer. It is
important to note that the read
r
range testting was not highly controlleed in these prooof-of-concept experiments. A
Also, no
attempt was made at this time
t
to optimize the antennaa design and m
match it to thee resonant freqquency (915 M
MHz) and
input impedaance of the RF
FID die. The goal
g
of our exp
periment was demonstrate thhe assembly aand applicabilitty of the
LEAP processs for chip-in-p
paper applicatiions. Now thatt the concept hhas been proveen, tag perform
mance can be opptimized
and tested in
n an anechoic chamber to maximize
m
the read
r
range, if needed. It maay be advantaggeous in high--security
applications to read the tags at lesser distaances, though this
t can be conntrolled by the rreader attenuattion in most caases.
To assess thee reliability off the RFID pap
per when subjected to mechannical stresses, bend testing w
was performedd on each
tag that wass assembled. The
T banknotes were manuallly bent arounnd a 50 mm ddiameter manddrel 100 times in each
direction. Affter bending, each banknote was
w tested to determine
d
if thhe read range hhad been affeccted, and no nooticeable
change was observed.
o
After the arttwork printing on the facesto
ock, the RFID paper was rettested for rangge and functionnality again. N
No range
difference orr loss of functio
onality were ob
bserved.
Proc. of SPIE Vol. 8608 86080L-10
DEC2012
X
Figure 8. RFID-enabled financial & security paper concept realized in the form of an RFID “banknote”. The image at the
bottom is a backlit photo clearly showing the embedded RFID antenna and chip.
4. PROCESS ANALYSIS OF LEAP TECHNOLOGY
4.1 Cost modeling
One of the major drivers for developing LEAP is the need to reduce the cost and increase the throughput of the
packaging operations, especially, in the case of small-size bare dice. LEAP provides an unmatched combination of high
packaging rates with cost of packaging unattainable by the conventional pick-and-place automation equipment.
The Cost of Ownership (COO) model developed by SEMATECH in 1990 is the de facto gold standard for cost modeling
analysis in the semiconductor industry. The cost prediction for LEAP has both similarities and differences compared to
cost modeling for IC fabrication, where the focus of the COO model is on the life-cycle cost of owning and operating a
semiconductor equipment while the impact of the cost of materials is typically not emphasized68. LEAP technology
excels in the assembly of ultra-low cost devices for which the cost is driven mostly by materials and less by the
equipment and labor costs. The model presented here computes the product cost from the ground up, based on the
process flow analysis in which the LEAP process is regarded as a series of operation steps, each with a specific cost and
yield. The operation cost of flip-chip assembling of a bare die using conductive adhesives (a typical example would be
an RFID inlay) is given by:
C pr =(C pd + Cadh + Csubs + Cant )/Y ,
(1)
where Cpr is the product unit cost, defined as the total cost invested per assembly of one die divided by the yield, Y, at the
end of the process; Cpd is the cost of packaged die; Cadh is the cost of adhesives used to interconnect the die, Csubs is the
cost of substrate material; and Cant is the cost of antenna.
Proc. of SPIE Vol. 8608 86080L-11
The yield Y in equation (1) is the composite yield calculated as a product of the assembly yield and die yield,
Y = Ya × Yw . The assembly yield, Ya, accounts for the fact that not all dice will be transferred from the wafer and not all
dice will be successfully interconnected. For square dice, the die yield, Yw, is given by the Seeds model69
Yw = e
- d e Do
(2)
,
where de is the die edge length and Do is the wafer defect density. Yw is included in equation (1) because all dice from the
wafer are packaged and the assembly cost of defective components must be written off on the good components. The
typical industry practice is to test dice on the wafer prior to assembly and to package only the good dice. However, in the
case of ultralow-cost single chip products such as RFID tags in which the chip accounts for more than a half of the
product cost, a more efficient approach would be to test the die post-assembly. This will reduce the cost of pre-assembly
operations, simplify the assembly equipment, and increase the rate of packaging. It is presumed that the benefits will
effectively offset the losses of having to dispose a certain percentage of assembled but non-functional products.
The term Cpd in equation (1) is a sum of the cost of semiconductor die, Cdie, and the cost of packaging operation, Cp. Cp
accounts for the fixed costs (equipment depreciation, overhead, and general and administrative costs) and the variable
manufacturing cost that includes all costs directly allocated to production, less cost of die: labor, maintenance, energy
and other resources. Cdie is the cost of a die from a wafer attached to the transparent wafer carrier and ready for laser
transfer, calculated as
⎛ π w2
π wr ⎞
Cdie = ( Cwafer + Cwaf .att . ) / ⎜ 2r - 2
⎟,
de ⎠
⎝ de
(3)
where wr is the wafer radius; Cwafer is the cost of the non-diced wafer; and Cwaf.att. is the fixed and variable cost for
preparing the wafer for transfer. The term in the denominator in equation (3) is the total number of dice in the wafer.
Figures 9 and 11 show the relationship between the die size and the various cost components of the LEAP operation
computed using the model in (1). By way of comparison, Figure 9 shows also the cost-die size relationships in case of
flip-chip assembly using conventional pick-and-place equipment13. Several important observations can be made from
these relationships. The cost benefits of using LEAP are clearly seen, especially for dice with sizes of less than 500 µm.
In this size range, the cost of the conventional flip-chip technology increases with the die size until the technology
reaches its lower size limit at about 400 µm. The reason is that there is a trade-off between alignment accuracy and
throughput when using pick-and-place equipment. The smaller the die the longer it takes to achieve the desired
alignment accuracy. All other conditions remaining the same, lower throughput means higher production cost. In
contrast, the LEAP technology is not only capable of transferring dice with much smaller sizes, but, even more
importantly, the cost of packaging operation is independent of die size.
12.0
LEAP
pick- and -place
i
Cost of packaged die
Cost of die
10.0
8.0
LI)
6.0
U
,-.f
a.)
ó
4.0
2.0
Cost of packaging operation
1.10
0.90
0.70
Die size, mm
C)
0.50
0.0
0.30
Figure 9. Cost as a function of die size for flip-chip packaging using LEAP (solid line) and a pick-and-place equipment
(dashed line). The former is computed using the cost model in equation (1) assuming Cwafer = $1000; the latter is adapted
from Ref. 13.
Proc. of SPIE Vol. 8608 86080L-12
The die cost vs. die size in Figure 9 follows equation (3) but it is different for both operations. The lower die cost in case
of LEAP results from the fact that LEAP starts with a non-diced, non-bumped wafer as opposed to the pick-and-place
machines that require a bumped and diced wafer stretched on a releasable carrier tape. These additional back-end
operations increase the cost per chip about 2-3 times compared to the “base” die cost calculated simply as wafer cost
divided by total number of dice. The wafer in LEAP is also diced but dicing is done after the wafer is attached to the
glass carrier. The simplified pre-assembly process sequence in LEAP adds only about 18-20% to the “base” cost of die,
much less than the additional cost accrued due to wafer bumping, dicing, and mounting on tape in the pick-and-place
routine. It is important to point out again that in LEAP the wafer is not tested after dicing, which additionally reduces the
cost per die and the cost of assembly.
4.2 Packaging rate of LEAP
One of the major advantages of LEAP technology is the high rate of packaging. The throughput of the operation is
determined not by the capabilities of the die placing components of the system. Rather, as shown in the example later in
this section, for a given inlay design the rate depends almost exclusively on the travel speed of the webstock. Even more
importantly, the packaging rates are independent of chip size, a unique characteristic of LEAP compared to the other
packaging technologies.
Roll-to-roll (R2R) manufacturing is the industry standard for cost-effective mass production of flexible electronic
products70. R2R mass production requires high placement rates. Placement accuracy and rate for the pick-and-place
machines are inversely correlated. According to Gilleo71, multiple nozzle placement machines are capable of up to
100,000 components per hour (cph) but with 4σ placement accuracy of ±100 μm, insufficient for the ultra-small dice.
Typical single nozzle die bonder systems process thick dice at a rate of 3000 cph72, but this rate is lower for precision
assembly of ultrathin dice. The most advanced (and expensive) single nozzle machines are capable of placement of
thicker dice at a rate of 5000 cph with 3σ placement accuracies of ±10 μm. There are pick-and-place machines that can
package up to 10,000 dice per hour (this number is smaller for smaller die sizes), but they can achieve these high rates
only by adding a second head, which also adds a substantial cost to the total cost of the equipment. Though these
machines may have the precision to place extremely fine pitch components, they are unable to place ultrathin dice34 at a
rate sufficient for high throughput assembly (>30,000 cph). In contrast, the throughput in LEAP can be increased by
multiples of 2, 3, 4 … simply by packaging 2, 3, 4 … dice at any given position of the webstock as shown in Figure 10.
laser beam
x -y laser scanner
die to be
transferred next
<
>
vw
////
Y1///////////
/// ' \
I=mo
wafer attached to
a glass carrier
/
MM/
web stepP
transferred dies
roll of flexible circuits
Figure 10. An example of LEAP assembly with three dice at each position of the webstock.
Proc. of SPIE Vol. 8608 86080L-13
This capability is another truly unique LEAP characteristic, because the increase in throughput does not require
equipment modifications. This is possible because the laser beam moves to the next die on the wafer using a
galvanometer x-y scanner capable of precision scanning with a speed ws that is orders of magnitude higher than the rollto-roll feed vr and the wafer positioning speed ww. Consequently, the positioning time of the laser beam for transferring
the next die is negligible compared to the time needed to move the substrate to the next position. This time is also
negligible compared to the time needed to adjust the wafer position so that the die to be transferred is positioned straight
above the intended location on the substrate. Since the increase in throughput is achieved without an increase in the cost
of equipment, the relationship cost of packaged die/throughput can be modeled as C p ∝ 1/ (nT ), n = 1, 2, 3... , where
n is the number of dice packaged at each web step, and T is the throughput for n = 1. This relationship is seen in Figure
11, which illustrates the effect of throughput on cost for various die sizes and values of n.
8.0
,N
7.0
.
1 die per position
2 dies per position
3 dies per position
Cost of packaged die
6.0
5.0
4.0
°
3.0
Cost of die
2.0
Cost of packaging operation
1.0
1.10
1.00
0.90
0.80
0 70
0.60
0.50
Die size, mm
0.40
0.30
0.20
0.0
0.10
Figure 11. Modeled cost as a function of die size for flip-chip packaging using LEAP for n = 1, 2, and 3.
The decrease in the cost of packaging operation is due to the decreased cycle time, i.e., the time required to package one
die at one position on the webstock. Less cycle time means less cost of labor per die. Also, the increase in the number of
transferred dice per unit time leads to a proportional decrease in the fixed (equipment depreciation, overhead, etc.) cost
per die. The throughput has a similar effect on the die cost. Equation (3) indicates that the cost per die includes the wafer
cost and the cost associated with preparing the wafer for die transfer. The latter includes the cost of materials and labor
for wafer preparation as well as the cost related to the depreciation of the equipment used for wafer preparation.
An illustrative example: LEAP assembly of an RFID inlay
The cost simulation model was used to compute the cost of an RFID inlay under several different scenarios.
Scenarios 1.1 & 1.2 assume a 200-mm RFID wafer with 600 µm square RFID die and 50 µm kerf width. The
total number of chips from this wafer calculated using equation (3) would be 105,206. Assuming a defect
density of 0.3 cm-2, the number of good dice is estimated as equal to 102,532.
The real potential of LEAP will be achieved when the size of the RFID chip is reduced below what is possible
today with the conventional pick-and-place equipment. Scenarios 2.1 & 2.2 assume a 200-mm RFID wafer with
300 µm square RFID die and 15 µm kerf width, which is possible, because, as mentioned before, in the LEAP
process the wafer is diced using RIE. The number of good dice from this wafer would be 279,626.
Proc. of SPIE Vol. 8608 86080L-14
Table 2. Parameters in the cost simulation model.
Parameter
Value
Cost of adhesives for die attach, ¢/inlay
0.05
Cost of antenna, ¢/inlay
1.5
Cost of substrate material per inlay, ¢/inlay
0.5
Cost of materials for wafer attach, $/wafer
10
Coefficient accounting for material waste
1.10
Cost of utilities and facilities, $/wafer
10
Web speed, m/min
10
Time for actual laser transfer, s
0.01
Time for wafer positioning, s
0.2
Time to replace wafer in the LEAP station, s
10
Time for wafer preparation, h
1.5
Equipment cost*, $
$991,000
Depreciation period, yrs.
6
Depreciation type
straight-line
Equipment utilization, %
80
Coefficient accounting for cost of maintenance
1.10
Annual operating time**, s
1.44×107
Operator’s wage, $/h
30.00
Indirect cost rate, % of Modified Total Direct Costs
30
* includes the cost of LEAP station as well as the cost of the wafer preparation equipment
** 52 weeks less 2 weeks for maintenance, 2 shifts, 5-day work week
In Scenarios 1.1 and 2.1 only one die is transferred per web step. The most efficient layout of the inlays on the
webstock in this case would be if the inlays were laid out with their long side perpendicular to the direction of
web travel. Assuming an overall size of the RFID inlay of 100 mm × 10 mm, the web step in this case would be
equal to 10 mm. Scenarios 1.2 & 2.2 involve the transfer of 4 dice per web step. In this case, the most efficient
way to lay the inlays out would be to place 4 inlays in a row, long side to long side, for each position of the
webstock. In this case, the web step would be 100 mm.
Table 3. Results from the cost simulation.
Scenario
Parameter
1.1
1.2
2.1
2.2
Die size, µm/side
600
600
300
300
Dice per web step
1
4
1
4
Cost, ¢/inlay
5.8
5.6
4.0
3.8
Transfer rate, cph
13,329
17,700
13,331
17,774
Proc. of SPIE Vol. 8608 86080L-15
The yield of the LEAP operation is assumed = 95%. This value is lower than the typical yield from a top-of-theline die bonder because of the fact that LEAP is still a developing technology. It is envisioned that the yield
from LEAP will be improved significantly when the technology matures. It was also assumed that the wafers in
Scenario I and II were purchased at $1,000 per wafer. The rest of the parameters in the cost model are listed in
Table 2.
The cost of the RFID inlay for the four different simulation scenarios is shown in Table 3. Note that the transfer
rate in Table 3 is not proportional to the number of dice per web step as reasoned before. This can be explained
with the difference in the web steps, determined by the rectangular shape of the tag - 10 mm vs. 100 mm for 1
die and 4 dice, respectively. If, for example, the tag had a square shape with an inlay size of 25 mm × 25 mm,
the transfer rates for Scenarios 2.1 and 2.2 would be 9,998 cph and 39,980 cph, respectively. This example
shows how sensitive the transfer rate is to the inlay design. Another critical parameter is the web speed.
Doubling the web speed to 20 m/min will decrease the cost of the 25 mm × 25 mm inlay in Scenario 2.2 to 3.4
¢/inlay and will increase the transfer rates to 50,495 cph, a truly staggering number, indeed.
5. CONCLUSIONS
The main obstacle to the widespread use of ultrathin, ultra-small embedded chips in non-reusable electronic devices
today is the absence of a viable high-throughput, low-cost packaging technique. The disruptive laser-enabled advanced
packaging (LEAP) technology presented here is exceptional in its ability to support the high-volume assembly of
ultrathin, ultra-small semiconductor dice essential for the new class of ultra-low-cost disposable and green electronic
products packaged on flexible, biodegradable substrates and augmented with RFID technology. An enormous market
potential exists for such products including RFID-enabled smart tickets, smart forms, smart labels, financial and security
paper and many more.
We demonstrated the viability of the LEAP process to the packaging of ultrathin and ultra-small semiconductor dice,
including 18-20 µm thick, 350 × 350 µm dice, embedded in a paper substrate. Sample EPC Global Gen2 UHF RFIDenabled “banknotes” were produced using LEAP to exemplify the application of this technology. These chip-in-paper
“banknotes” were verified as working with read ranges up to 30” with a non-optimized antenna design. Initial reliability
tests showed no reduction in tag performance after repeated bending stresses. The process model presented verifies
LEAP as a low-cost approach for packaging ultra-small, ultrathin dice. It is shown that the packaging rate in LEAP is
independent of the chip size, a unique characteristic of LEAP compared to the conventional pick-and-place packaging
technologies. Both packaging rate and cost in LEAP are dependent mostly on the R2R web speed and configuration. A
manifold increase in throughput is achieved by simply redesigning the webstock without the need for complicated and
costly equipment modifications. The possible cost reduction and throughput delivered by LEAP are unmatched by any
other technologies designed for packaging of ultrathin and ultra-small chips.
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