NMI TR18
Shift Registers with
Feedback Configured
as Counter-dividers
Greig W Small
© Commonwealth of Australia 2014
First edition — June 2014
Second edition — July 2016
National Measurement Institute
Bradfield Road, Lindfield, NSW 2070
PO Box 264, Lindfield, NSW 2070
T
F
W
(61 2) 8467 3600
(61 2) 8467 3610
www.measurement.gov.au
CONTENTS
1
Introduction ...................................................................................................................................... 4
2
Shift Registers with Feedback to the Input ...................................................................................... 4
3
4
5
2.1
Some Definitions ................................................................................................................... 6
2.2
Some Observations ............................................................................................................... 6
2.3
Corollary ................................................................................................................................ 6
Shift Registers of the Twisted-ring Configuration ............................................................................ 6
3.1
Propositions .......................................................................................................................... 7
3.2
Examples of Loop Structures ................................................................................................ 8
3.3
Systematic Generation of Loop Sequences .......................................................................... 9
Derived Counting Sequences........................................................................................................ 11
4.1
Combining Loops ................................................................................................................ 11
4.2
Merging of Loops ................................................................................................................ 11
4.3
Associated Sequences ........................................................................................................ 13
4.4
Attachment of One Loop to Another ................................................................................... 14
4.5
Modifying Maximum-length Sequences .............................................................................. 14
4.6
Automated Design of Shift Register Counter-dividers ........................................................ 15
Some Examples of Counter Design .............................................................................................. 16
5.1
Modulo-158 Counter with Symmetrical Output ................................................................... 16
5.2
Non-integer Divider Modulo 101/27 ...................................................................................... 18
6
Conclusion ..................................................................................................................................... 19
7
References .................................................................................................................................... 19
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ABSTRACT
Binary counters are conventionally adopted as counters and dividers. Where the natural binary
sequence of counting states is the required output, such counters are obviously the most appropriate.
In other applications, however, such as frequency scaling and shift register based waveform
synthesis, counters based on shift registers with feedback may offer advantages of simplicity of
programming and of modulating the count modulus. The implementation of shift registers with
feedback to their input is particularly effective in programmable gate arrays, in which the coding of the
feedback states is interpreted as a look-up table.
Keywords: shift registers, linear feedback shift registers, programmable dividers, modulated dividers,
phase-locked loops.
1 Introduction
Conventional binary counters are the obvious choice for event counting, for sequential addressing of
look-up tables in waveform synthesis and in many other applications. In frequency synthesis,
however, where either fixed or programmable division ratios are required, binary counters are clumsy.
Modifying the counting base of a binary counter usually implies resetting on carry overflow to the
ones-complement of the required base. Either every bit must be reset or, if the counting base is fixed,
the pattern of bits to be reset is specific to the base and requires a custom design. In either case the
advantages of sequential binary counting are compromised by the loss of a number of counts starting
from zero.
An alternative configuration that retains some semblance of the natural binary sequence is the ratefeedback binary counter [1], in which the output signals from several stages are combined with
interlacing and caused to advance the count, and so to modify the count modulus.
The more effective tool in programmable frequency synthesis is the accumulator rate multiplier, better
known by the term direct digital synthesis (DDS). Again, the natural binary sequence, or binary-coded
decimal sequence, is to some extent retained.
In cases of fixed-frequency synthesis where the natural binary sequence is irrelevant, continuedfraction dividers offer accurate approximations to irrational ratios [2].
Another type of counter comprises a shift register with feedback to the input from one or more taps
combined in the exclusive-OR (XOR) function. Known as linear feedback shift registers (LFSRs),
these are able to generate long (2N – 1) pseudo-random sequences of output bits with a modest
number (N) of shift-register stages. Usually the zero state is a persistent state and must be excluded,
requiring additional logic or at least a power-up reset to a non-zero state.
If the feedback is inverting and from the output stage only, the counter is called a twisted-ring counter.
An adaptation of this is the Johnson counter, where the shift register fills progressively with ones and,
when full, progressively with zeros. Usually the output bits from the N stages are gated to generate
2N separate signals, changing in sequence to 1 (or 0) whilst all others are 0 (or 1). A 5-stage Johnson
counter was popularly used with numerical displays based on glow discharge (Nixie) tubes, where
each of the ten output signals of the counter enabled the selection of one of the ten cathodes. In the
Johnson counter there is the possibility of entering an unintended loop on start-up or from some
transient interference. This is counteracted with additional logic to count out of the unwanted loop or
loops.
Although specific designs of shift-register counters may be found by searching the Internet, there
appears to be no comprehensive theory of design in the literature. Here the theory and systematic
design of shift registers as counter-dividers, with feedback exclusively to the input stage, is developed
and their versatility and economy of design is demonstrated.
2 Shift Registers with Feedback to the Input
The configuration of an N-stage shift register counter with count control by feedback to the input stage
is shown in Figure 1. The data-in signal is an explicit Boolean function of the N output signals of the
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shift register. A logic gate generates the carry-out signal from a designated terminal state of the shift
register.
This configuration is particularly suited to implementation in a programmable gate array (PGA), which
is comprised of a number of identical programmable combination logic blocks and a versatile
programmable interconnection network between logic blocks and from logic blocks to input and output
blocks. An example of a combination logic block, simplified as is appropriate and relevant to a shiftregister counter, is shown in Figure 2.
Figure 1: Shift-register counter with control at the input stage
Figure 2: Simplified example of a PGA combination logic block
In Figure 2, L represents the combination logic and M is a programmable multiplexer. The logic is
implemented as a look-up table and as such is capable of representing every possible one-bit
Boolean function of the several input bits. In practice the combination logic block is usually presented
as a schematic diagram of gates and D flip-flops. In compilation the look-up table is generated by
evaluating the output of this gate array for all possible values of the several inputs. Consequently, the
designer has the freedom to represent the logic in any form that generates the desired result, without
regard to the complexity of that representation. For example, Figure 3 shows four different
representations of the exclusive-or (XOR) function.
Figure 3: Different representations of the exclusive-or function
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The upper diagrams are the conventional symbol and a construction from two-input NAND gates; the
lower diagrams are the arithmetic functions of selective complement and addition of two bits. The
designer is free to choose a representation that clarifies his intention.
2.1 Some Definitions
The number of stages in a shift register is denoted by N. The total number of possible states is then
2N.
The state of a shift register is denoted by S. In particular, S may be assigned a numerical value by
regarding the pattern of bits of the shift register as a binary number. It is convenient to assign to the
output of the final stage the most significant bit (msb) and accordingly to the output of the input stage
the least significant bit (lsb). The 2N possible states then correspond to the numerical values 0, 1 … 2 N
– 1.
The ones-complement (cp) of S is denoted by S; cp(S) = S = (2N – 1) – S.
Both bits and states may be concatenated. Concatenation is denoted by { … }.
The rump R of S is a subset of S. Examples are S = {msb, R} and S = {R, lsb}.
The data-in bit is denoted by d.
One shift of the contents of the shift register is denoted by sh( ); sh(S) = {R, d}. Multiple shifts are
defined by shn + 1(S) = sh(shn(S)).
Numerically, sh(S) = (2S + d) modulo 2N. That is, if S is of the form {0, R} then
sh(S) = 2S + d, and if S is of the form {1, R} then sh(S) = 2S + d – 2N.
2.2 Some Observations
Note that the result of a shift may be the same for either of a pair of precursor states. If the data-in bit
is the same, the two states {0, R} and {1, R} both result in {R, d}. Such pairs of states shall be termed
congruent pairs, since they are congruent modulo 2N – 1.
Note that sh(S) may result in either of two possible successor states, {R, 0} or {R, 1}, according to
whether d is 0 or 1. Such pairs of states shall be termed sibling pairs.
Note that each of a sibling pair may have a precursor, or one may have two precursors in which case
the other has none.
Note that exactly two states in a given shift register may be their own precursor/successor. These
states are either when all N bits are 0 (S = 0) or when all are 1 (S = 2N – 1). No other state has this
property.
2.3 Corollary
The only possible state sequences are loops, in which each state has exactly one precursor, or
strings that begin with a state that has no precursor and must lead eventually to a loop, possibly
entering into another string on the way. Since every state must have a successor, there can be no
isolated string, although a string that leads to a state that is its own precursor/successor may appear
to be an isolated string.
The bit values of a shift register constitute a record of the most recent N values of d. A succession of
states may be identified either as a sequence of state values, or as a sequence of data-in bits. The
two representations are equivalent.
3 Shift Registers of the Twisted-ring Configuration
As noted above, a shift register with inverting feedback from the output stage to the input stage is
termed a twisted-ring shift register. Without additional logic, there will in general be multiple
sequences of states, each of which accounts for a distinct subset of all possible states. Normally, in a
Johnson ring counter all but one of these possible subsets are excluded by additional logic.
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3.1 Propositions
Proposition 1: For every N there is at least one loop of length 2N
Proof
Let the initial state S1 be zero, corresponding to all bi = 0. At each shift the most significant zero is
shifted out and its complement is shifted in as the least significant bit. Hence N shifts are required to
replace S1 by its complement S1 (all bi = 1) and a further N shifts to restore the original state S1.
Proposition 2: For every odd N there is exactly one loop of length 2
Proof
Let the initial state be S1. For there to be a loop of length 2, it is necessary that:
sh(S1) = S1
so that sh(sh(S1)) = sh(S1) = S1
That is, in one shift each bit of S1 is replaced by its complement. Hence bi = bi+1 for all i, and so the bit
pattern is an alternating sequence of ones and zeros. Further, since in one shift the msb is replaced
by its complement as the lsb, the msb must be the same as the lsb. This can be true only for odd
values of N.
The numerical value of S1 may be determined by evaluating the binary interpretation of the alternating
sequence of zeros and ones. Alternatively it may be calculated directly.
Let S1 belong to the lower half (msb = 0) of the field of all possible state values. Then:
S1 = sh(S1) = 2S1 + 1
and
S1 = (2N – 1) – S1 (ones complement of S1)
from which
3S1 = 2N – 2
Now the residues of 2N modulo 3 are 2, 1, 2, 1, 2 … for N = 1, 2, 3, 4, 5 … respectively. Hence for odd
values only of N:
S1 = (2N – 2)/3
The solution is unique – there is only one such loop for each value of N.
Proposition 3: For every shift register of length (2n + 1)N there will be a loop of length 2N
corresponding to each loop of length 2N in a shift register of length N
Proof
Let S(1) be a state of any loop of length 2N in an N-stage shift register. Generate the state S(2n + 1)
by concatenating S(1), S(1), S(1) … for a total of 2n + 1 times. Then {S(1), S(1), S(1) …} is a state in
a (2n + 1)N-stage shift register.
Since
shN(S(1))
it follows that
= S(1)
shN(S(2n + 1)) = shN{S (1), S(1), S(1) …}
= {S(1), S(1), S(1) …}
and
sh2N(S(2n + 1)) = shN{S(1), S(1), S(1) …}
= {S(1), S(1), S(1) …}
Therefore the concatenated state is a state in a shift register of length (2n + 1)N that is periodic in 2N
shifts; that is, it is a state of a loop of length 2N.
Corollary
The only loops of length 2N in a shift register of length (2n + 1)N are those corresponding to the loops
of length 2N in a shift register of length N.
Consider an indefinitely long shift register with feedback from the output of the Nth stage, with an
initial state {U, S(1)} where U signifies ‘undefined’ and S(1) is a state of a loop of length 2N in an Nstage shift register.
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After N shifts the state of the shift register will be {U, S(1), S(1)} and after a further N shifts it will be
{U, S(1), S(1), S(1)}. From this point onwards the pattern in the first 3N bits will repeat in 2N shifts and
will be identical whether the feedback is taken from the output of the Nth stage or of the 3Nth stage.
Clearly, this cannot be true for any pattern not of this form.
The argument is readily extended to feedback taken from the output of the (2n + 1)Nth stage.
Proposition 4: If N is an odd prime P, its loop structure must consist of one loop of length 2
and loops of length 2P to account for the (2p – 2) remaining states
Proof
Since P is prime, it is not an odd multiple of any number except itself and 1. It is comprised therefore
of exactly one loop of length 2, and (2P – 2)/(2P) loops of length 2P.
Comment
The result given above suggests that (2P – 2) must be divisible by 2P, or equivalently that
(2P-1 – 1) is divisible by P. In fact, this is a particular case of a more general theorem from the theory
of congruences [3]:
xP-1 ≡ 1 (modulo P) for all x ≡/ 0 (modulo P)
where the equivalence symbol is read ‘is congruent with’.
Proposition 5: For a shift register of length N = 2n stages each and every loop must be of
length 2N
Proof
Since 2n cannot be an odd multiple of any number, including 1, there cannot be any loop of length
less than 2N.
Comment
Note that every even number is either of the form 2n or is an odd multiple of exactly one number of the
form 2n.
This follows from the unique factorisation theorem of arithmetic, which requires that the set of prime
factors of an integer is unique. Hence there is only one way to form the (odd) product of the odd
primes and the product of the n factors of 2.
By contrast, an odd number of the form P1P2 for example, where P1 and P2 are odd primes, is an odd
multiple of both P1 and P2.
3.2 Examples of Loop Structures
From the propositions above the loop structure of any given length of shift register may be
determined. Table 1 lists the loop structures of shift registers for a few values of N.
As is evident in the tables, the total number of loops becomes unmanageably large with N greater
than about 8 unless the look-up table can be constructed automatically and the hardware is able to
accommodate its implementation as an N-bit address by one-bit data memory.
Table 1(a): Loop structures for a selection of odd values of N
Stages
N
Factors
Number of
loops
Loops of
length
Number of
states
Total number
of states
1
1
1
2
2
2
1
1
2
2
3
1
6
6
1
1
2
2
5
3
10
30
3
5
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32
8
7
9
15
1
1
2
2
7
9
14
126
1
1
2
2
3
1
6
6
9
28
18
504
1
1
2
2
3
1
6
6
5
3
10
30
15
1 091
30
32 730
128
512
32 768
Table 1(b): Loop structures for a selection of even values of N
Stages
N
Factors
(odd x 2n)
Number of
loops
Loops of
length
Number of
states
Total number
of states
2
2
1
4
4
4
4
4
2
8
16
16
2
1
4
4
6
5
12
60
64
8
16
16
256
256
2
1
4
4
10
51
20
1 020
4
2
8
16
12
170
24
4 080
2
1
4
4
6
5
12
60
18
7 280
36
262 080
8
16
16
256
24
349 520
48
16 776 960
6
8
10
12
18
24
1 024
4 096
262 144
16 777 216
3.3 Systematic Generation of Loop Sequences
A loop may be identified conveniently and unambiguously by its state of least numerical value. Let this
state be denoted by L(a:1), where the digit in bold type designates the loop’s position in order of
ranking by initial states. Let L(a:n + 1) be the successor to state L(a:n) in loop L(a).
Since for all N there must be a loop starting with 0, it follows that L(1:1) = 0. In this loop the sequence
of states will be →0→1→3→… This will account for 2N states, as shown in Proposition 1 (clause 0).
If there are more than one loop, the first state that is not accounted for will be the identifying state of
the second loop – L(2:1) = 2, and the sequence will be →2→5→… This will account for a further set
of states.
Continuing in this manner, always choosing as the identifying state of the next loop the first state that
has not already been included in a loop, all possible loops will systematically be generated. For
example, with N = 5:
L(1:1) = 0, sequence is →0→1→3→7→15→31→30→28→24→16
L(2:1) = 2, sequence is →2→5→11→23→14→29→26→20→8→17
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L(3:1) = 4, sequence is →4→9→19→6→13→27→22→12→25→18
L(4:1) = 10, sequence is →10→21
3.3.1 An alternative representation of a state and its location by loop
To identify the loop to which any particular state belongs, the list of states by loop may be searched
for that state. Alternatively, the state may be notionally shifted until one of the loop identifiers is
encountered. Both of these methods are rather mechanical.
A somewhat more direct method, yet equivalent to the second of the alternatives above, results from
a different representation of the state, in which contiguous bits of the same polarity are replaced by
the numerical count of those bits. For example, in loop L(3:1) above, state 13, or 01101 in binary
notation, is represented by (1,2,1,1). Equally, the complementary state is also represented, since the
assignation of polarity has not been specified.
Note that in this case the number of counts is even. Since consecutive counts represent bits of
alternating polarity, the leading and trailing counts represents bits of opposite polarity. A notional b
shifts of the binary representation, where b is the value of the trailing count, will replace the set of
trailing bits with b leading bits of their complement, which is to say, of the same polarity as the original
a leading bits with which they are now contiguous. These two leading counts shall therefore be
replaced by their sum a + b.
In the example, (1,2,1,1) →(2,2,1) and the compacted form may now be cyclically permuted to
generated new state representations within the same loop. Since a loop is labelled by its state of least
value, its follows that the loop may be identified by cyclic permutation of the given state to satisfy the
condition that the sequence of counts is of the form (max1, min1, max2, …) and then substituting bit
values beginning with zeros. In the example, the desired permutation is (2,1,2) and the corresponding
bit pattern is 00100 = 4.
3.3.2
An alternative procedure for the generation of loop sequences
The bit-count representation of states may be used to effect in generating the set of loops. The
constraints are that the number of counts must be odd, and the representation must be of the form
(max1, min1, max2, … ). As an example, consider the case N = 6. All possible representations are
(6)
loop 0;
(4,1,1)
loop 2;
(3,1,2)
loop 4;
(3,2,1)
loop 6. Note that (3,2,1) is not a cyclic permutation of (3,1,2);
(2,1,1,1,1)
loop 10;
(2,2,2) loop 12. Note that four shifts will result in the same state, so this is a loop of length 4. This
completes the list of possibilities and results in five loops of length 12 and one of length 4, as is
required.
3.3.3
Occurrences of sibling pairs in loops
Relatively few sibling pairs occur in loops. Where they do so, their complementary sibling pairs also
occur. It may be useful when combining loops (see below) to know where these are.
Suppose that a sibling pair occurs in a loop, separated by n shifts. Then we may construct one of the
siblings as follows:
Represent the sibling as an N-bit number, and assign either 0 or 1 to the least significant bit (lsb) b0;
the choice will determine which of the complementary pairs of the siblings will be generated.
Since the sibling’s pair must be identical except for b0, then b0 must be copied into bn, and in turn bn,
or its complement if the shift is end-around, must be copied into b2n (mod N).
The procedure is continued until either each bit has been assigned a value and the next shift would
complement the lsb, or the lsb would not be complemented, or the loop is closed without having
assigned a value to every bit. The second possibility will always result if n is even, for then there must
have been a multiple of 2N shifts which always returns the initial value of the lsb. The third possibility
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will always result if n and N are not mutually prime, for then the sequence closes in a proper subset of
N. Even if the closure complements the lsb, applying the procedure to any remaining subset will also
result in its initial bit being complemented.
The defining requirements for n are therefore that it must be odd and mutually prime with respect to
N. For n = 1, however, there will always be two pairs of siblings and these will be in loop 0.
For example, let N be equal to 7, for which n may take values of 1, 3 and 5.
For n = 3, construct the sibling state as follows:
S = xxxxxx0→xxx0xx0→0xx0xx0→0xx01x0→01x01x0→01x0100→0100100(→0100101). Hence 36
and 37 are a sibling pair separated by 3 shifts.
Similarly, for n = 5, proceed as follows:
S = xxxxxx0→x0xxxx0→x0x1xx0→x0x1x00→00x1x00→0011x00→0011000(→0011001). Hence 24
and 25 are a sibling pair separated by 5 shifts.
4 Derived Counting Sequences
4.1 Combining Loops
As shown in Table 1, shift registers of the twisted-ring configuration of more than two stages (N > 2)
possess multiple loops, resulting in indeterminacy (assumed to be undesirable) of state sequence on
start-up. This may be reliably avoided by combining loops into a single sequence of all possible
states.
Loops may be combined by merging, in which the entire sequence of one loop is inserted into
another, or by attachment, in which a loop sequence is broken and one end is attached to another
loop. In attachment any state of the broken loop leads eventually into the loop to which it is attached.
If all possible loops are combined by merging or attachment, then all possible states are accounted
for in one composite sequence and no ambiguity can exist.
4.2 Merging of Loops
Two loops may be merged by choosing a pair of sibling states, one from each loop, and inverting the
data-in coding generated by their precursors. The precursor in loop 1 then leads to the sibling state in
loop 2 and vice versa. The whole sequence of states of loop 2, from the sibling state to its precursor,
is patched into loop 1 between the precursor state and its successor.
Note that in this operation the data-in codes generated by states in the upper half of states (msb = 1)
remain the complements of those of the corresponding states in the lower half
(msb = 0). It is sufficient, therefore, to consider modifications to the data-in codes of the lower half of
states only, with the condition of complementarity imposed on those of the upper half.
By combining all loops in this manner, a maximum-length sequence is obtained. Generally, there will
be a plurality of ways in which the loops may be combined.
In the case of N = 3, the two loops of the twisted-ring configuration are →0→1→3→7→6→4 and
→2→5. The possible choices of sibling pairs are 2, 3 and 4, 5, and their respective precursors are 5,
1 and 6, 2. Inverting the coding for the first pair gives the part-sequences 5→3 and 1→2, and
combined sequence is →0→1→2→5→3→7→6→4. Alternatively, inverting the coding for the second
pair gives the part-sequences 6→5 and 2→4, and the combined sequence is
→0→1→3→7→6→5→2→4. There are no other possible sequences in this case.
Table 2: Sequential data-in codes for maximum-length sequences
Sequence
Sequential data-in code
01253764
1
0
1
1
1
0
0
0
01376524
1
1
1
0
1
0
0
0
Table 2 shows the sequential data-in codes for the two maximum-length sequences. These codes
describe the successive states that may be observed at the output of any stage of the shift register.
The following relationships may be noted.
With the appropriate relative shifts:
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
each sequence is the same as the other, in reverse order;

each sequence is the same as the complement of the other; and

each sequence is the same as the complement of itself, in reverse order.
State sequences that possess such relationships shall be termed associated sequences.
In the case of N = 4, the two loops are →0→1→3→7→15→14→12→8 and
→2→5→11→6→13→10→4→9. The possible choices of sibling pairs for merging these loops are 2,
3; 6, 7; 8, 9 and 12, 13. The corresponding sequences are given in Tables 3(a) to (c).
Table 3(a): State sequences for each choice of sibling pairs
Sibling pair
State sequence
2, 3
0
1
2
5
11
6
13
10
4
9
3
7
15
14
12
8
6, 7
0
1
3
6
13
10
4
9
2
5
11
7
15
14
12
8
8, 9
0
1
3
7
15
14
12
9
2
5
11
6
13
10
4
8
12, 13
0
1
3
7
15
14
13
10
4
9
2
5
11
6
12
8
Table 3(b): Sequential data-in codes for each choice of sibling pairs
Sibling pair
Sequential data-in code
2, 3
1
0
1
1
0
1
0
0
1
1
1
1
0
0
0
0
6, 7
1
1
0
1
0
0
1
0
1
1
1
1
0
0
0
0
8, 9
1
1
1
1
0
0
1
0
1
1
0
1
0
0
0
0
12, 13
1
1
1
1
0
1
0
0
1
0
1
1
0
0
0
0
Table 3(c): Data-in codes listed in order of state value
Sibling pair
Data-in code ordered by state value
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
2, 3
1
0
1
1
1
1
1
1
0
1
0
0
0
0
0
0
6, 7
1
1
1
0
1
1
1
1
0
0
0
1
0
0
0
0
8, 9
1
1
1
1
0
1
1
1
0
0
0
0
1
0
0
0
12, 13
1
1
1
1
1
1
0
1
0
0
0
0
0
0
1
0
Table 3(a) and Table 3(b) list the state sequences and the sequential data-in codes as in the previous
example. Relationships between the data-in code sequences as noted above will be investigated
later.
Table 3(c) shows the data-in codes listed in ascending order of state value, and suggests a more
compact way of identifying sequences. As noted above, the codes of the second half of the state
values are the complements, respectively, of those of the first half. A sequence may therefore be
identified by the state (or states) of the first half for which a code value of 1 has been replaced by a 0.
The four sequences are then identified as sequences 1, 3, 4 and 6.
These four sequences are not exhaustive. In each of these four, the second of the original two loops
was merged into the first in its entirety. It is also possible to combine the two loops by switching
between the first into the second multiple times. With four points at which to implement this pattern,
there are four combinations from which to choose. Expressed in terms of those states in which a datain code of 1 is replaced with a 0, they are 1 3 4, 1 3 6, 1 4 6 and 3 4 6. The resulting sequences are
given in Table 4, in which the states belonging to the second loop are in bold type. In every case the
part-sequences are of one, three and four states.
Table 4: State sequences resulting from multiple switching between original loops
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Sequence
State sequence
134
0
1
2
5
11
7
15
14
12
9
3
6
13
10
4
8
136
0
1
2
5
11
7
15
14
13
10
4
9
3
6
12
8
146
0
1
2
5
11
6
12
9
3
7
15
14
13
10
4
8
346
0
1
3
6
12
9
2
5
11
7
15
14
13
10
4
8
The totality of possible sequence still has not been exhausted. So far, only those precursor pairs
mutual to both of the original loops have been considered. Other precursor pairs, specific to the
second of those loops, exist, namely 2, 10 and 5, 13. Setting the data-in code for each pair to 0, 1 in
turn gives:
→2→5→11→6→13→10→4→9
Original loop 2:
Invert code bit for 2, 10: →2→4→9 and →5→11→6→13→10
Invert code bit for 5, 13: →2→5→10→4→9 and →6→13→11
Invert code bit for both: →2→4→9 and →5→10 and 6→13→11
Inverting the code bit for both pairs of precursors is unacceptable, as there is no possibility of
escaping the →5→10 loop. In both other cases the first component loop may be merged with the
original loop 1 by choosing either precursor pair 1, 9 or 4, 12, and the second component loop by
choosing 3, 11 or 6, 14. Altogether this represents another eight sequences as listed in Table 5, again
with the components of the second loop in bold type.
The 16 state sequences listed in tables 3, 4 and 5 comprise all possible sequences for N = 4. For N =
5 the number of possible loops is 64; for higher values of N the number of possible loops increases
rapidly and becomes unmanageable.
Table 5: State sequences resulting from modifying the original loop 2
Sequence
State sequence
213
0
1
2
4
9
3
6
13
10
5
11
7
15
14
12
8
216
0
1
2
4
9
3
7
15
14
13
10
5
11
6
12
8
243
0
1
3
6
13
10
5
11
7
15
14
12
9
2
4
8
246
0
1
3
7
15
14
13
10
5
11
6
12
9
2
4
8
513
0
1
2
5
10
4
9
3
6
13
11
7
15
14
12
8
516
0
1
2
5
10
4
9
3
7
15
14
13
11
6
12
8
543
0
1
3
6
13
11
7
15
14
12
9
2
5
10
4
8
546
0
1
3
7
15
14
13
11
6
12
9
2
5
10
4
8
4.3 Associated Sequences
Table 3(b) lists the sequential data-in code bit for the first four sequences of a four-stage shift register.
Because this bit is shifted through the shift register, one stage at a time with each shift, the list of
sequential code bits is also a history of the sequential states of the shift register. These states may be
read from the list, four adjacent bits at a time, advancing to the right with the msb on the left. (It may
be convenient to extend the sequence by one cycle or two to avoid reading end-around.)
It is equally valid to read the list in the reverse order, advancing to the left with the msb on the right.
This will generate one of the associated sequences. Two more associated sequences result from
substituting for each bit its complement and reading forward and reverse. Relative to the initial
sequence, these associated sequences are designated the reverse, the complement and the reverse
complement sequences.
Thus, in general, associated sequences always appear in sets of four, except for values of N less
than 4 in which case some or all of the sequences are self-referential.
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Identifying the sequences associated with a given sequence is straightforward. In a given sequence,
let S = {0, R} be a state for which the data-in bit is d = 0. Then two patterns of (N + 1) bits, {0, R, 0}
and {1, R, 1} relating to S and its congruent partner, will occur in the given sequence.
In the reverse sequence, these will appear as {0, R', 0} and {1, R', 1} respectively, where R' is the
value that results from reading the (N – 1) bits of R in the reverse order.
In the complemented sequence, these will appear as {1, R, 1} and {0, R, 0} respectively, where R is
the value of the ones-complement of the (N – 1) bits of R.
Hence the states associated with S = {0, R} in the given sequence are {0, R'}, {0, R} and {0, R'} in the
reverse, complement and reverse complement sequences respectively.
The four sets of associated sequences for N = 4 are given in Table 6.
Table 6: All four sets of associated sequences for a four-stage shift register
Given
Reverse
Complement
Reverse complement
1
4
6
3
134
146
346
136
213
246
546
513
216
243
516
543
The table shows the relationship to the given sequence of its associated sequences. For the
relationships to an entry in another column, form the logical products of the respective column
headings. For example, the complement of an entry under the heading Reverse is found in the
column under the heading Reverse complement.
The point of generating and listing all these loops will become apparent below, where modified
counting is considered.
4.4 Attachment of One Loop to Another
As with the merging of loops, a pair of sibling states, one from each loop, is identified. In the loop to
be attached, the data-in code of the precursor state is inverted so that its successor becomes the
sibling state in the other loop. The sibling state in the loop to be attached now has no precursor and
has become the start of a string that leads into the other loop.
If desired, other states in the string that have sibling pairs in a loop may also be made points of
attachment. The number of shifts required to count out of any string is thereby reduced.
4.5 Modifying Maximum-length Sequences
Counter-dividers generally are required to divide by factors other than 2N. Since a maximum-length
counter cannot divide by a factor greater than 2N without external intervention, only those divisors less
than 2N are accessible.
Shortening a maximum-length sequence is somewhat similar to attaching a string. A sibling pair within
the sequence is identified, and the precursor to one of these is caused to invert its data-in code, so
that its successor becomes the second of the sibling pair. The sequence of states from the first of the
pair to the second becomes an attached string, and the count modulus is reduced by the length of this
string. Additional implementations of sequence shortening may be made, subject to the limitation that
the additional precursors to be invoked must remain in the loop after the preceding shortenings.
For the same N, different maximum-length sequences offer different choices in the lengths of these
strings. All sequences of an associated set, however, have the one set of string lengths in common.
Let S(a) = {R, 0} and S(b) = {R, 1} be a sibling pair of states in a given sequence, a distance s apart;
that is, S(b) = shs(S(a)). Then in the complement sequence these will be replaced by their
complements, S(a) and S(b), also a sibling pair distance s apart.
In the reverse sequence, S(a) will be read as {0, R'} and S(b) as {1, R'}, a congruent pair distance s
apart. The successors to these will be the sibling pair {R', 1} and {R', 0} or, perhaps, {R', 0} and {R', 1},
also distance s apart.
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Hence the sequences of an associated set have in common the same combination of distances
between sibling pairs and the same set of shortening string lengths.
For N = 4, Table 7 lists all combinations of count-shortening precursor, length of string and length of
loop for one representative sequence of each of the four associated sets.
Table 7: Precursor, string length and loop length of four associated sets (N = 4)
Sequence
1
134
213
216
String length and loop length for each count-shortening precursor
Precursor
7
8
5
2
4
11
1
6
9
14
3
12
10
13
0
15
String
1
1
3
5
6
6
8
8
8
8
10
10
11
13
15
15
Loop
15
15
13
11
10
10
8
8
8
8
6
6
5
3
1
1
Precursor
7
8
14
10
12
11
13
0
9
5
3
4
2
6
0
15
String
1
1
4
5
6
6
7
8
8
9
10
10
11
12
15
15
Loop
15
15
12
11
10
10
9
8
8
7
6
6
5
4
1
1
Precursor
7
8
13
1
12
3
2
6
14
10
4
11
9
5
0
15
String
1
1
2
3
5
5
6
7
9
10
11
11
13
14
15
15
Loop
15
15
14
13
11
11
10
9
7
6
5
5
3
2
1
1
Precursor
7
8
13
1
12
14
3
2
10
11
4
6
9
5
0
15
String
1
1
2
3
5
5
7
8
8
5
11
11
13
14
15
15
Loop
15
15
14
13
11
11
9
8
8
7
5
5
3
2
1
1
It may be seen that sequence 213 offers all relevant loop lengths, except 12, with only one modifying
precursor (or none). Loop lengths of less than 9 do not require a shift register of four stages.
A cascade of two or more counters may be simpler than a single long counter. The versatility of
cascaded counters is not limited to the product of factors. By modulating the count of the first stage
with the carry-out signals from later stages, division by factors of the form n1n2±a may be achieved.
Non-integer frequency division may be approximated by the established technique of periodic
modulation of an integer divider by ±1 count (-1 count only, for a maximum-length divider). The
approximation is optimal in that timing errors are bounded by one clock period.
The configuration is similar to that of a cascade of two or more dividers, but with the output signal
being taken from the first stage.
4.6 Automated Design of Shift Register Counter-dividers
The analysis and systematic design of shift register counter-dividers as presented above lends itself
to interpretation as a software package that generates the look-up table necessary to realise dividers
of any specified modulus based on shift registers of any reasonable length. In that case, the
architecture may be simplified further as shown in Figure 4. This configuration is suitable for
implementation in discrete hardware, if desired.
Figure 4: Shift-register counter configuration suited to large numbers of stages
The look-up table is a 2N by 2-bit programmable read-only memory (PROM). The output signal,
designated carry, could be any configuration of output signal, such as an optimal approximation to a
square wave of the number of cycles required per counting cycle. Other options, such as waveform
synthesis, are possible if the PROM is arranged with a larger number of data bits.
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5 Some Examples of Counter Design
5.1 Modulo-158 Counter with Symmetrical Output
A particular design of phase-locked loop frequency synthesizer [4] requires a counter, modulo-158,
with symmetrical output.
For a symmetrical output the counter must end with a divide-by-two stage, which therefore must be
preceded by a modulo-79 counter. Noting that 79 = (5 × 16) – 1 suggests that the modulo-79 counter
might be configured as a modulo-5 counter followed by a modulo-16 counter, with count modulation of
the modulo-5 counter once for every carry out from the combination, as shown in Figure 5.
Figure 5: Modulo-79 counter
This is bound to be a simpler design than one based on a seven-stage shift register, in which six
component loops of 14 states would need to be combined, the resulting loop sequence of 84 states to
be modified so as to cycle through 79 states, and the remaining four component loops to be attached
to the main loop.
Modulo-5 (4) Counter
A shift register of three stages is required. The twisted-ring configuration results in two loops, one of 6
states and one of 2 states. The state sequences are →0→1→3→7→6→4 and →2→5 respectively.
The loop of 6 states may be modified to count through 5 states by inverting the data-in bit for either
S(3) or S(4); choose S(3). The loop of 2 states may be attached to the main loop by inverting the
data-in bit for S(2), S(5) or both; choose S(2). The loop count may be modulated to divide by 4 by
inverting the data-in bit at S(4), which must be the state that provides the carry-forward to the modulo16 counter and to its output carry. With this arrangement the state sequence is:
Two alternative approaches to the design of the input gating logic may be considered.
The first implements the shift register state sequence above, and is shown in Figure 6(a). Note that
both S(2) and S(3) may be identified by the binary code 01x 1. The loop is closed with feedback from
the output of the shift register to one input of an exclusive-NOR (XNOR) gate which, in the absence of
other signals, generates the inverted data-in bit. The other inputs to the XNOR gate serve to further
invert the data-in bit for the selected states S(2) and S(3) and for the carry at S(4) from the modulo-16
counter.
Figure 6(a): Input gating logic implementing the shift register state sequence
1
x = don’t care; the bit represented by x need not be recognised
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The second approach is to compose the data-in truth table and interpret it in the simplest
configuration of gates. This is shown in Figure 6(b).
For a symmetrical output the counter must end with a divide-by-two stage, which therefore must be
preceded by a modulo-79 counter. Noting that 79 = (5 × 16) – 1 suggests that the modulo-79 counter
might be configured as a modulo-5 counter followed by a modulo-16 counter, with count modulation of
the modulo-5 counter once for every carry out from the combination, as shown in Figure 5.
Figure 5: Modulo-79 counter
This is bound to be a simpler design than one based on a seven-stage shift register, in which six
component loops of 14 states would need to be combined, the resulting loop sequence of 84 states to
be modified so as to cycle through 79 states, and the remaining four component loops to be attached
to the main loop.
Modulo-5 (4) Counter
A shift register of three stages is required. The twisted-ring configuration results in two loops, one of 6
states and one of 2 states. The state sequences are →0→1→3→7→6→4 and →2→5 respectively.
The loop of 6 states may be modified to count through 5 states by inverting the data-in bit for either
S(3) or S(4); choose S(3). The loop of 2 states may be attached to the main loop by inverting the
data-in bit for S(2), S(5) or both; choose S(2). The loop count may be modulated to divide by 4 by
inverting the data-in bit at S(4), which must be the state that provides the carry-forward to the modulo16 counter and to its output carry. With this arrangement the state sequence is:
Two alternative approaches to the design of the input gating logic may be considered.
The first implements the shift register state sequence above, and is shown in Figure 6(a). Note that
both S(2) and S(3) may be identified by the binary code 01x 2. The loop is closed with feedback from
the output of the shift register to one input of an exclusive-NOR (XNOR) gate which, in the absence of
other signals, generates the inverted data-in bit. The other inputs to the XNOR gate serve to further
invert the data-in bit for the selected states S(2) and S(3) and for the carry at S(4) from the modulo-16
counter.
2
x = don’t care; the bit represented by x need not be recognised
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Figure 6(a): Input gating logic implementing the shift register state sequence
The second approach is to compose the data-in truth table and interpret it in the simplest
configuration of gates. This is shown in Figure 6(b).
Figure 6(b): Input gating logic implementing the data-in truth table
The implementation in a combination logic block (CLB) is identical for both. The first has the appeal of
a methodical approach to the design of the input gating logic and is therefore easier to interpret, while
in this particular example the second is marginally simpler.
Modulo-16 Counter
The merging of the two loops of a twisted-ring four-stage shift register has been comprehensively
dealt with above. Any one of the merged loops is acceptable. The clocking of this counter is enabled
by the carry-forward from the modulo-5 counter.
Any state may be selected as the terminal count, which must be combined with the carry-forward of
the modulo-5 counter to generate the output carry. The complete divider is shown in Figure 7. In the
annotations to the figure, ‘+’ signifies a logical OR and ‘.’ a logical AND.
Figure 7: Divider modulo-158 with symmetrical output signal
5.2 Non-integer Divider Modulo 101/27
A frequency synthesizer, designed to generate a signal of frequency 10/2π kHz from a 5 MHz clock,
requires a divider modulo 101/27 followed by one of modulo 313 [5]. The relative error in frequency is
19 × 10-9 Hz/Hz.
The modulo-101/27 divider may be configured as a four-stage shift register, modified to count by 11,
with carry-out enabling a five-stage shift register modulo 27, the terminal state, or carry, of which
modulates the first stage at S(8) (or at S(7)) to count by 10 in the absence of the carry and by 11
otherwise. This is an example of periodically modifying the count by +1.
Taking the first example from Table 7, the merged loop is formed with precursor pair (1, 9) and
shortened by five counts with precursor 2. The counting sequence is:
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where nc indicates no carry from the modulo-27 divider.
The modulo-27 divider is configured as a five-stage shift register. The sequences to be combined are
listed in clause 0 and, from 3.3.3 above, there must be complementary sibling pairs with n = 3 in loop
4, namely (18,19) and (13,12). The three loops of 10 states may be merged with the precursor pairs
(1, 17) and (2, 18). The resulting sequence of 30 states is:
→0→1→2→4→9→19→6→13→27→22→12→25→18→5→11→23→14→29→26→20→8→17→3→
7→15→31→30→28→24→16
which may be shortened by 3 counts with precursor 6. The remaining loop of two counts may be
attached with precursor 10. As usual, any state that is not in an attached string may be chosen as the
terminal count. In this case, a carry forward is not required and it is more convenient to combine the
terminal state with S(8) at the input to the first stage. For the same reason, any state within the
counting sequence of the first stage may be chosen as its carry out and second-stage count enable –
it is not necessary to choose state S(8). Indeed, choosing a state other than S(8) relaxes the timing
constraint on the signal path from the second stage.
The schematic diagram of the complete counter is shown in Figure 8.
Figure 8: Schematic diagram of modulo-101/27 divider
At the input to the modulo-10/11 shift register there are just five signals, so the input logic and the first
two stages may be accommodated in one combination logic block (CLB). The next two stages also
require one CLB and the output gate one more, although use might be made elsewhere of one of its
shift registers.
At the input to the modulo-27 shift register there are also five signals, so the input logic and the first
two stages may again be accommodated in one CLB. The next two stages require another and the
output stage and gating logic also one more.
6 Conclusion
Shift-register counter-dividers have been shown to be versatile, simple in architecture and economical
to implement in programmable logic arrays. In addition, they are fully synchronous and the
accumulation of delays through cascaded gates is minimal.
7 References
[1]
Small G W 1973 Rate-feedback binary counters in musical scale generation
J. Audio Eng. Soc. 21 702–5
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[2]
Small G W 1973 Synthesis of the musical scale using non-integer frequency division
J. Audio Eng. Soc. 21 262–6
[3]
Davenport H 1968 The Higher Arithmetic (London: Hutchinson)
[4]
Small G W 2006 A generator-detector system for ac bridge applications
Conf. Precision Electromagnetic Meas. Digest (Torino) 472–3
[5]
Small G W 1973 A frequency synthesizer for 10/2π kHz
IEEE Trans. Instrum. Meas. IM-22 34–7
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