UNIVERSITA’ DEGLI STUDI DI VERONA
DOCTORAL PROGRAM IN
Nanotechnologies and Nanostructured Materials for
Biomedical Applications
WITH THE FINANCIAL CONTRIBUTION OF
EU funded FP7 ALPINE Project, n. 229231
2013
Study of structure and electronic
properties of high performance
CdTe solar cells by electrical
investigation.
Presented by
Ivan Rimmaudo
Accepted on the recommendation of
Dott. Alessandro Romeo
Table of Contents
1 Introduction ............................................................................................ 1
1.1
Photovoltaic Technologies and CdTe ............................................ 1
1.2
Solar cells and CdS/CdTe junction................................................. 4
1.3
CdTe cell fabrication...................................................................... 8
1.3.1 Front Contact ................................................................................ 9
1.3.2 CdS Window Layer ...................................................................... 10
1.3.3 CdTe Absorber Layer ................................................................... 10
1.3.4 Activation Treatment .................................................................. 11
1.3.5 Etching and Back Contact ............................................................ 12
1.4
Thesis Contents ........................................................................... 13
1.5
References................................................................................... 14
2 Electrical characterization .................................................................... 17
2.1
Introduction ................................................................................ 17
i
2.2
Current Voltage (J/V) ................................................................... 18
2.3
Admittance Techniques............................................................... 21
2.4
Capacitance Voltage (C/V)........................................................... 23
2.5
Drive Level Capacitance Profiling (DLCP) .................................... 26
2.6
Admittance Spectroscopy (AS) .................................................... 27
2.7
Temperature and Frequency in Admittance techniques. ........... 30
2.8
References ................................................................................... 32
3 Freon® activation treatment in low temperature process ................... 34
3.1
Introduction................................................................................. 34
3.2
Experimental ............................................................................... 35
3.3
Current Voltage (J/V) ................................................................... 36
3.3.1 Transport properties. .................................................................. 37
3.4
Space charge profiles. ................................................................. 38
3.5
Space charge spectroscopy ......................................................... 40
3.6
Hysteresis effect. ......................................................................... 42
ii
3.7
Discussion.................................................................................... 44
3.8
Conclusions ................................................................................. 47
3.9
References................................................................................... 48
4 Effects of activation treatment on the electrical properties of low
temperature grown CdTe devices ........................................................ 51
4.1
Introduction ................................................................................ 51
4.2
Experimental ............................................................................... 52
4.3
Current-Voltage (J/V) .................................................................. 53
4.3.1 Transport Properties ................................................................... 54
4.4
Space charge profiling ................................................................. 56
4.5
Admittance spectroscopy: defects identification ....................... 60
4.6
Conclusions ................................................................................. 63
4.7
References................................................................................... 64
5 Thin CdTe: Physical and electrical properties. ..................................... 69
5.1
Introduction ................................................................................ 69
5.2
Experimental Details ................................................................... 70
iii
5.3
Current-Voltage (J/V) .................................................................. 70
5.4
Atomic Force Microscopy (AFM) ................................................. 73
5.5
X-Ray Diffraction (XRD)................................................................ 73
5.6
Space Charge Profiling ................................................................. 76
5.7
Space charge spectroscopy ......................................................... 78
5.8
Conclusions.................................................................................. 81
5.9
References ................................................................................... 84
6 Ageing of CdTe devices by copper diffusion ........................................ 87
6.1
Introduction................................................................................. 87
6.2
Experimental ............................................................................... 88
6.3
Current-Voltage (J/V). ................................................................. 89
6.4
Space Charge Profiling ................................................................. 91
6.5
Space Charge Spectroscopy ........................................................ 96
6.6
Conclusions.................................................................................. 98
6.7
References ................................................................................. 100
iv
7 Final Conclusions ................................................................................ 101
7.1
Freon® vs. CdCl2 for low temperature deposition process. ....... 101
7.2
CdCl2 activation treatment effects ............................................ 102
7.3
Properties of devices based on thin CdTe layers ...................... 102
7.4
Cu diffusion in ageing process................................................... 103
v
vi
List of Figures
Figure 1-1. Thin Film in PV market. .............................................................. 3
Figure 1-2. a) Electron-hole (e--h+) pair generation. b) Direct
recombination. c) Trap assisted recombination......................... 5
Figure 1-3. Solar cell equivalent circuit. ....................................................... 7
Figure 1-4. CdS/CdTe solar cell structure ..................................................... 9
Figure 2-1. CdS/CdTe base-line J/V curves and parameters. ..................... 18
Figure 2-2. a) Ea extraction from dark J/V for our CdS/CdTe base-line. b)
Ideality Factor temperature dependency for CdS/CdTe baseline. ........................................................................................... 20
Figure 2-3. CdS/CdTe band diagram showing the main recombination
mechanisms: a)Interface Ea>Eg, b) SCR Ea=Eg and c) Bulk CdTe
Ea=Eg. ......................................................................................... 21
Figure 2-4. a) Parallel circuit for admittance measurements. b) Admittance
phasor diagram. ........................................................................ 22
vii
Figure 2-5. Charge Density profile for CdS/CdTe base-line. In the inset the
relative Mott-Schottky plot. ..................................................... 24
Figure 2-6. Deep defect contribution due to Vac. ....................................... 25
Figure 2-7. CdS/CdTe base-line C/V and DLCP profiles comparison........... 27
Figure 2-8. CdS/CdTe base-line a) AS curves and b) t peaks at different
temperatures. ........................................................................... 29
Figure 2-9. Extraction of Et and sigma for a deep defect in CdS/CdTe baseline ............................................................................................ 30
Figure 3-1. Typical J/V curves of the three sets of samples. ...................... 36
Figure 3-2. Arrhenius plots of J0 comparing different combination of
deposition and treatments. ...................................................... 38
Figure 3-3. C/V (open) and DL (full) space charge profiles. The estimation
of free hole concentrations indicated in the figure. The
difference between C/V and DLCP concentration indicates a
lower bound for deep defect concentrations........................... 39
Figure 3-4. Arrhenius plot of AS and DLTS data for VE-Freon® sample...... 40
Figure 3-5. Influence of the freeze-out of free holes in VE-Freon® sample
associated with defect A. .......................................................... 42
viii
Figure 3-6. Influence of the direction of the DC bias scan direction on the
space charge width measured for sample CSS-Freon® (circles)
and VE-Freon® (triangles) at 350 K and the AC frequency 104
Hz. ............................................................................................. 43
Figure 3-7. Influence of the direction of the DC bias scan direction on dark
J-V measured for sample CSS-Freon® (circles), VE-Freon®
(squares) and VE-CdCl2 (triangles). ........................................... 45
Figure 4-1. Typical J/V curves of the three sets of samples. ...................... 53
Figure 4-2. Arrhenius plot for 720µl, 1800µl and Over-treated samples. In
the inset: Ideality factors dependency from temperature....... 54
Figure 4-3. C/V (full dots) and DLCP (open dots) of the 180 l, 720 l, 1800
l and over-treated samples made at 200 K and 50 kHz. In the
inset comparison of 50 kHz and 1 MHz for 1800 µl sample at
the same temperature. ............................................................ 58
Figure 4-4. C/V (full dots) and DLCP (open dots) of the 180 l, 720 l, 1800
l and over-treated samples made at 300 K and 50 kHz. In the
inset comparison of 50 kHz and 1 MHz for 1800 µl sample at
the same temperature. ............................................................ 59
ix
Figure 4-5. Arrhenious plots of the different samples identifying the
different defects. ...................................................................... 62
Figure 5-1. J/V characteristics of different devices with CdTe thickness
ranging between 0,7 and 6 µm. ................................................ 71
Figure 5-2. Roll-over reduction in thin CdTe devices ................................. 72
Figure 5-3. Band diagram for thick (top) and thin (bottom) CdTe, showing
the back contact barrier (ϕb) reduction.................................... 72
Figure 5-4. Grains morphology of 1 m (top), 1.8 m (center) and 6 m
(bottom) thick CdTe after CdCl2 treatment. ............................... 74
Figure 5-5. XRD spectra of CdCl2 treated (top) and as-deposited CdTe
(bottom), 6 m (red) and 0.7 m (black). ................................. 75
Figure 5-6. Comparison between the 0.7 m (black symbols) and 6 m
(gray symbols) samples............................................................. 76
Figure 5-7. Typical 6 µm C/V (open symbols) and DLCP (full symbols)
profiles measured at different temperatures and at constant
frequency of 1 MHz. In the inset, for the same sample, profiles
measured at different frequencies and at constant temperature
of 300 K are compared. ............................................................ 77
x
Figure 5-8. Depletion width extension over temperature and frequency for
6 µm and 1 µm (inset) samples (DC bias 0 V). .......................... 79
Figure 5-9. Different quasi-Fermi-levels splitting in Thin CdTe .................. 80
Figure 5-10. Defect identification by linear correction of AS Arrhenius plot
for 6 µm (full dots) and 1 µm (open dots). ............................... 81
Figure 6-1. Down right. Normalized efficiency evolution for the different
kinds of stress. η0 represents the efficiency at t=0 h (hour).
Others. Typical J/Vs of DNB, LTNB and LTB at different ageing
time........................................................................................... 90
Figure 6-2. Comparisons between DLCP (full symbols) and C-V (open
symbols) profiles of LTNB sample at 300 K and 10 kHz. In the
inset a similar comparison repeated at 1 MHz......................... 92
Figure 6-3. Comparisons between DLCP (full symbols) and C-V (open
symbols) profiles of LTB sample at 300 K and 10 kHz. In the
inset a similar comparison repeated at 1 MHz......................... 93
Figure 6-4. Comparisons between DLCP (full symbols) and C-V (open
symbols) profiles of DNB sample at 300 K and 10 kHz. In the
inset a similar comparison repeated at 1 MHz......................... 95
xi
Figure 6-5. Comparisons between DLCP (full symbols) and C-V (open
symbols) profiles of LTB sample at 10 kHz and in a range of
temperature between 180 K to 300 K. ..................................... 96
xii
List of Tables
Table 3-1. Typical performances of the three kinds of samples. ............... 36
Table 4-1. Current-Voltage parameters of four typical solar cells with
different treatment. ................................................................. 52
Table 4-2. Bandgap and ideality factor for the four differently treated
devices. ..................................................................................... 55
Table 4-3. Measured defects concentration in the differently treated CdTe
devices. ..................................................................................... 57
Table 4-4. Extracted defects by AS. ............................................................ 62
Table 5-1. Depletion region width over absorber thickness for different DC
bias at 300 K and 50 kHz. .......................................................... 79
Table 5-2. Extracted defects of 6 m and 0.7 m CdTe absorbers. ........... 82
Table 6-1. Activation energy and cross capture section ............................ 97
xiii
xiv
Summary
Electrical characterization is a powerful investigation method for
semiconductor devices. Compared to other types of characterization, its
main advantage consists in the possibility to analyze the finished devices.
For many kinds of technologies this issue is mandatory to understand
deeply the device structure, its operation mechanism and how the
materials can change during the fabrication process. Therefore, electrical
characterization techniques represent probably the most important
feedback in the device development.
In this thesis a possible methodology to investigate thin films solar cells by
means of some electrical characterization techniques will be described.
Moreover I will show how these methodologies have been used to extract
important information for CdS/CdTe solar cells fabricated in our
laboratories. This information has been very useful to develop and optimize
a low temperature (< 450 °C) production process so to be able to achieve
CdTe solar cells with efficiency exceeding 14 % (best cases over 15 %).
In general, the investigations which constitute the chapters of this thesis,
have been approached changing in reasonable manner important process
parameters and, then, analyzing the resulting effects on the electronic and
structural properties of the materials and consequently on the devices.
xv
It is known that CdTe needs a special “activation treatment” to perform
high efficiency devices. This treatment has been studied to further assess
the “magic” benefits on the CdTe semiconductor properties.
Two different activation treatments have been optimized in our labs. The
first is based on a mixture of gases Ar and difluorochlorometane (Freon®),
already used by other researchers, who demonstrated its effectiveness on
CdTe cells fabricated at high temperature. The second is based on the
deposition of a liquid solution of CdCl2 in methanol and a subsequent
annealing in air.
Solar cells with CdTe treated in these two different ways were fabricated
and analyzed also by means of electrical characterization. Results were
compared also with cells fabricated at high temperature kindly provided by
Parma University. CdCl2 treatment was able to recrystallize the low
temperature deposited CdTe also by improving the electrical properties,
while the gaseous treatment was demonstrated to be weak in increasing
the carriers concentration but, at the same time, too invasive in affecting
the intermixed layer at the CdS/CdTe interface, with an excess of sulfur
diffusion.
The treatment based on liquid CdCl2 has been further investigated
modulating its effectiveness. Under-treated, sub-optimum, optimum and
over-treated samples were prepared and analyzed, in order to address the
changes involved by the activation treatment on the films composing the
devices. It has been demonstrated that a strong connection between the
treatment effectiveness and the defect concentration in CdTe polycrystals is
present. The CdTe carrier concentration increases as treatment increases
but at the same time recombination is also enhanced by the deep defects
close to the junction, the optimum treatment represent the best tradeoff
between this two phenomena.
Another important issue in thin film devices is the absorber thickness,
which is desired to be as small as possible. Unfortunately the scaling is
usually challenging. By preparing several numbers of cells with different
CdTe thickness, it has been demonstrated that the problems connected
xvi
with thickness are not only light absorption and films homogeneity, but
most important they are mainly generated by different materials
composition and different transport mechanism. Within this study solar
cells with 1.5 µm of CdTe and efficiency exceeding 10 % have been
fabricated.
Finally, the performance degradation of CdTe solar cells with Cu/Au back
contact has also been investigated by electrical characterization. Identical
samples were stressed for long time in different condition of light,
temperature and electrical bias. Different Cu migration has been observed
for the different kinds of stresses, excluding the hypothesis that at different
stresses it corresponds just only a different diffusion speed. Moreover we
conclude that probably Cu in our samples does not migrate as positively
ionized like it has been proposed by other authors, but in negative or
neutral configuration generating middle band defects, which enhance
recombination.
xvii
xviii
Chapter 1
Introduction
1.1 Photovoltaic Technologies and CdTe
Since 1954, when the first 6 % Silicon solar cell was presented by Chapin
[1], photovoltaic (PV) technology has been developed in many different
manners, basing on different materials. Each technology presents different
characteristics (e.g. maximum efficiency, cost, scalability, application, etc.),
hence to compare them is not straightforward. In this paragraph I will try to
report a brief overview of the most widespread and promising photovoltaic
technologies.
Silicon is the oldest technology and up to now it is the most diffused in PV
modules market (exceeding 80 % in 2011 [2]). Silicon is a semiconductor
with indirect bandgap that makes it not the best material for photonic
application. Nevertheless its success was determined by the high
knowledge developed in the last century, especially in microelectronic
industry. Indeed silicon cell efficiency record is 25.0 % [3][4] approaching
the calculated theoretical limit of 30 % [5]. The main drawback is the low
scalability, which results in modules with much lower efficiency or very high
cost.
1
2
Photovoltaic Technologies and CdTe
The single junction record efficiency is hold by GaAs, 28.8 % [3][4],
nevertheless it is mainly used for space application due to the high
production cost.
Combining stacks of p-n junctions is possible to increase dramatically the
efficiency of the solar cells that are called multi-junction or tandem cells.
Furthermore concentrating the solar light by means of special mirrors it is
possible to achieve 44 % efficiency [4]. Multi-junction structures are
extremely complex and expensive, moreover mirrors occupy large areas
and necessary water-cooling increases the system cost. All these aspects
make this technology suitable mainly for massive energy production.
Dye-sensitized solar cells [6] record is 11,4 % [4], but they don’t need
direct light exposure, then suitable in countries with low yearly solar
radiation or for indoor application. Furthermore they can also be produced
with different colors and used to make PV-artworks or decorations (i.e.
skyscrapers windows).
Thin films solar cells technologies point to reduce the cost often at the
expense of modules efficiency. Since 2007 they occupy over 10% of the
whole PV market, exceeding 17% in 2009 (see Figure 1-1) [2]. There are
many different thin films technologies, however to present all of them is
beyond the goal of this work: here I will mention only the most relevant in
the PV market.
Copper Indium Gallium (di)Selenide (CIGS) is one of the most promising
thin film technologies due to its high efficiency and relatively low
production cost. CIGS holds the thin film efficiency record and it is also
suitable for flexible modules production. Recently the world record was set
to 20.4 % on flexible substrates by EMPA labs. [4]. The main drawback is the
indium scarcity. Alternative cells are being developed where selenium is
replaced with sulfur (CIGS2) [7].
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Introduction
Figure 1-1. Thin Film in PV market.
The most widespread thin film technology is based on CdTe, in 2009 it
achieved almost 14 % of the PV modules market giving a real alternative to
silicon. The current cell efficiency record is 18.7 % [3][4] whereas for
modules is 15.3 % [3], this values state the high scalability of the production
process. On the other hand, the cost per watt-peak is the lowest in PV
market (0,67 $/Wp) [8] and this is the actual driving force of CdTe. However
this technology presents different drawbacks:
 Te scarcity,
 Cd toxicity,
 Back-contact stability.
Tellurium is a rare metalloid, which principal source is anode sludge
produced during the electrolytic refining of copper. Cadmium is toxic if
breathed in fine dust or fumes. Therefore the CdTe perception is usually a
critical factor for the market, and it is often a comfortable way for
competitors to contrast this technology. Moreover CdTe is very stable
compound, which is not soluble in water and with a high melting
temperature (1092 °C), and once encapsulated it is definitely harmless [9].
Nevertheless many efforts were made by researchers to reduce the
Electrical characterization of high performance CdTe solar cells.
3
4
Solar cells and CdS/CdTe junction
thickness of CdTe in the modules: nowadays modules are produced usually
with a thickness of around 4 µm that means 28 g/m2 of CdTe (13,2 Cd and
14,8 Te). It has been calculated that scaling the CdTe thickness down to 1
µm would solve the problem of Te abundance up to a yearly production of
100 GW [10] and, at the same time, the Cd amount should be dramatically
reduced down to 2.7 g/m2, almost ten times smaller than C-size Ni-Cd
rechargeable batteries [11].
Another important issue is the choice of an appropriate back-contact that is
crucial to limit performance losses when solar cells are connected to form a
module. Furthermore PV modules are usually to be granted for a period of
20-25 years, in which performance cannot decrease down to 80 % of the
initial value, for CdTe modules this is often strongly connected to the backcontact stability.
1.2 Solar cells and CdS/CdTe junction
A solar cell is a device able to generate power, converting light energy in
electric energy. It is based on the photovoltaic effects discovered by
Bacquerel in 1839 and fully explained by Einstein’s photoelectric effect in
1905. When light is incident on a semiconductor, photons interact with
electrons transferring their energy, in accord with their wavelength and the
energy bandgap of the semiconductor (Eg), hence electrons (e-) lying in the
valence band (VB) are promoted to the conduction band (CB), thus they are
now free and they can move freely in the lattice. The absence of the
electron in the valence band is called hole (h+) and it is also able to move
freely in the lattice. This process is usually called electron-hole pair
generation (or just generation). If any electric field is applied to the
semiconductor, electrons lose the received energy and fall again in the
valence band annihilating a hole and emitting a photon of the same energy
of the bandgap this process is called direct radiative recombination.
Actually, many different recombination mechanisms are usually present in
semiconductors, however I will mention only recombination assisted by
traps alias Shockley-Read-Hall (SHR). In a semiconductor lattice many kinds
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Introduction
of defects can be present (e.g. dangling bonds, vacancy, substitutional or
interstitial atoms, etc.), which represent possible electronic states. If defect
electronic state energy lies within the band-gap they represent a so-called
recombination center or a trap. The difference between these two is small,
the first capture a carrier until it is annihilated by an opposite charge, the
latter, captures the carrier for a certain time after which the carrier is
released back to the band where it came from. In both cases the energy
that electron have to lose to recombine with a hole is smaller than the
energy bandgap, and this makes the recombination process statistically
more probable (see Figure 1-2).
Figure 1-2. a) Electron-hole (e--h+) pair generation. b) Direct recombination. c)
Trap assisted recombination
If an electric field is applied to a semiconductor under light, electrons and
holes are separated and a current flows through the device. To perform this
separation without any external power source a p-n junction is needed.
A p-n junction is formed joining an n-type and a p-type semiconductor. If
the two semiconductors have the same Eg we call the p-n junction
homojunction otherwise we have a heterojunction. The p-type
semiconductors differ by n-type for the kind of majority carriers: in the first
case holes, in the latter electrons. At the interface of the two materials
carriers recombine and, at thermal equilibrium, the free carriers density is
almost zero. On the other hand fixed charged ions remain at the interface,
Electrical characterization of high performance CdTe solar cells.
5
6
Solar cells and CdS/CdTe junction
positive in the n-type side and negative in the p-type, for this reason we call
it Space Charge Region (SCR) or in alternative Depletion Region. Away from
the interface, thus from the SCR, carriers density concentration is high and
the resistivity of this regions are order of magnitude lower than SCR’s one,
so we call these neutral regions. The fixed charge forming the SCR generate
the electric field needed to separate the electron-hole pairs generated by
the light. Transport mechanisms in a p-n junction either in dark or light
operation can be addressed by Poisson’s equation and continuity
equations.
𝑞
−∇2 𝜓 = 𝜖 (𝑁𝐷+ − 𝑁𝐴− + 𝑝 − 𝑛)
1-1
Where  is the electrostatic potential  the permittivity of the
semiconductor, q is the elementary charge ND and NA ionized donor and
acceptor density respectively, p and n free holes and electrons density.
𝛿𝑝
(𝑥, 𝑡)
𝛿𝑥
= −𝑞
1 𝛿𝐽ℎ
𝛿𝑥
+ 𝐺ℎ − 𝑅ℎ
1-2
𝛿𝑛
(𝑥, 𝑡)
𝛿𝑥
= −𝑞
1 𝛿𝐽𝑛
𝛿𝑥
+ 𝐺𝑛 − 𝑅𝑛
1-3
These are mono-dimensional versions of the continuity equations where x
is the direction, t is the time, Jh and Jn holes and electrons current density
respectively, G is the generation ratio due to optical or thermal energy and,
finally, R is the recombination ratio including radiative and non-radiative
mechanisms (with photon or phonon emission respectively).
The p-n junction was not invented for solar purpose. Diode was the first pn junction based electronic device used to rectify electric signals, its
simplified characteristic equations is:
𝑞𝑉
𝐽𝐷 = 𝐽0 [𝑒𝑥𝑝 (𝐴𝑘𝑇) − 1]
1-4
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Here, JD is the current flowing through the diode, J0 is the saturation current
of the diode, A is the ideality factor, V the internal voltage, q the
elementary charge and k Boltzmann’s constant (see paragraph 2.2).
Therefore, it is possible to describe a solar cell as a current generator in
parallel to a diode.
Unfortunately it is not enough for a satisfactory description of a real solar
cell. To better outline the actual devices, the model must be integrated at
least with two additional resistances: one in series to the diode (Rs) and one
in parallel (Rp). The resulting equivalent circuit is shown in Figure 1-3.
Figure 1-3. Solar cell equivalent circuit.
The relation between current and voltage for this circuit is:
𝑞(𝑉−𝑅𝑠𝐽 𝐽)
(𝑉−𝑅𝑠 𝐽)
𝐴𝑘𝑇
𝑅𝑝
𝐽 = 𝐽0 [𝑒𝑥𝑝 (
) − 1] − 𝐽𝐿 +
1-5
During light operation, when the external contacts are shunted, JL flows
and it is usually called Short Circuit current (Jsc), on the other hand when no
load is connected to the contacts, a voltage is present called Open Circuit
voltage (Voc), that can be calculated by:
𝑉𝑜𝑐 =
𝑘𝑇
𝐽
𝑙𝑛 ( 𝐿
𝑞
𝐽0
− 1)
1-6
Electrical characterization of high performance CdTe solar cells.
7
8
CdTe cell fabrication
When a passive load is connected to the circuit, current flows and
consequently electric power is supplied. Load has to be optimized in order
to set the working condition as close as possible to the maximum power
point (Pm), that is the combination of current (Jm) and voltage (Vm), supplied
by the solar cell, which maximize the output power (Pm) (see Figure 2-1).
It is useful to define another parameter called Fill Factor (FF) as follow:
𝐹𝐹 = 𝑉
𝑃𝑚
𝑜𝑐 𝐽𝑠𝑐
𝑉 𝐽
= 𝑉𝑚 𝐽𝑚
𝑜𝑐 𝑠𝑐
1-7
In the absence of Rs and Rp,
𝑉𝑚 = 𝑉𝑜𝑐 𝑎𝑛𝑑 𝐽𝑚 = 𝐽𝑠𝑐 → 𝐹𝐹 = 1
1-8
Finally it is possible to define a parameter called Efficiency (η) that
represent the capability of the solar cell to transform luminous power in
electric power.
𝑃
𝜂 = 𝑃 𝑒𝑙 = 𝐹𝐹
𝑜𝑝𝑡
𝑉𝑜𝑐 𝐽𝑠𝑐
𝑃𝑜𝑝𝑡
1-9
To create modules many solar cells must be connected together in series
and/or in parallel in order to increase the maximum output voltage and
current, according to the load. This operation is usually challenging.
1.3 CdTe cell fabrication
Cadmium telluride thin film technology is one of the most successful in PV
market, as I already mentioned in the first paragraph. However it is worth
to note that a unique way to make CdTe solar cells does not exist. In
general it is possible to say that CdTe devices are thin films stacks deposited
on a substrate, where CdTe plays the role of absorber layer. Films
composing the cell can be different, deposited with different techniques
and in different conditions. In this paragraph I will explain the production
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Introduction
process that has been developed at Verona University’s laboratories which
is summarized in Figure 1-4. This process has been started at the begin of
my Ph.D. and developed in the last three years. Performance of the
produced solar cells rose up to 14% with best cases exciding 15%.
Figure 1-4. CdS/CdTe solar cell structure
1.3.1 Front Contact
A solar device transforms photons in electrons and holes, however these
carriers must be extracted out of the device before they recombine.
Therefore the contacts quality plays an important role on the device
performance. Moreover when solar cells are connected together to form a
module the resistance of contacts and connections determines most of the
energy loss.
At our laboratories a fabrication process has been developed for solar
cells in superstrate configuration. This means that the device is deposited
on a transparent substrate and the front contact is the first layer deposited
on it (see Figure 1-4).
Electrical characterization of high performance CdTe solar cells.
9
10
CdTe cell fabrication
Indium tin oxide (SnO2:In2O3 alias ITO) as front contact is usually higly
conductive, minimizing both vertical and horizontal resistance, it is also very
transparent. Unfortunately indium is a rare and expensive material that also
tends to diffuse in the other layers. In all the samples I will mention in thr
next chapters, ITO was deposited by direct current magnetron sputtering
and covered by a ZnO buffer layer to avoid indium diffusion, likewise
impurities from the substrate. Being ZnO an insulator it increases the
vertical resistance of whole device, so it must be as thin as possible. On the
other hand, it has beneficial effects on the Rsh (see Figure 1-3). Thicknesses
of the ITO and ZnO films are 400 nm and 100 nm respectively. On this bilayer front contact other 4 layers are deposited to complete the device. To
access the front contact a small area is masked during the CdS and CdTe
deposition, here Cu and Au are deposited during the back-contact
deposition.
1.3.2 CdS Window Layer
CdS is a yellowish natural n-type semiconductor with an energy band-gap
around 2,4 eV, hence absorbed photons are in the visible range. CdS
absorption is undesired, because it reduces the photons that can reach the
absorber and generate electron-hole pairs. CdS is needed only to form the
p-n junction with CdTe. I will refer to it as window layer, even though many
authors call it buffer layer.
In superstrate configuration many problems are connected to the window
layer deposition: its transparency, thickness, uniformity and crystalline
structure have a critical impact on the device performance.
At our laboratories CdS is deposited by Vacuum Evaporation (VE) at 100 °C
and at pressures lower than 10-5 mbar. After deposition the film is annealed
at 450 °C for 30 min in order to ensure better crystalline quality, which
allows to grow a higher quality CdTe. The thickness usually deposited on
our samples ranges from 300 nm to 500 nm.
1.3.3 CdTe Absorber Layer
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Introduction
CdTe is the p-type semiconductor of the junction where most of the light
is absorbed, and so, it is called absorber layer. CdTe is a direct bandgap
semiconductor; it means that the conduction band minimum and the
valence band maximum are aligned, so to generate an electron-hole pair
only a photon is needed. Reported bandgap energy ranges from 1,4 to 1,56
eV [12]. These factors result in a very high absorption coefficient: it has
been calculated that only 1 µm of CdTe is sufficient to convert 92% of the
useful sunlight, whereas crystalline silicon has to exceed 200 µm to reach
the same value [12], this makes CdTe very well suited for solar applications.
At our laboratories CdTe is deposited by VE in the same vacuum chamber
where CdS is deposited, at pressures of 10-6 mbar and at a substrate
temperature of 340 °C. Our baseline nominal CdTe thickness is 9 µm, but
etching (see paragraph 1.3.5) can reduce it sensibly. The final film thickness
has been measured by a profilometer into a range between 7 to 7.5 µm.
Moreover to study the effects of ultra-thin layer (see Chapter 5), CdTe was
scaled down to 700 nm.
1.3.4 Activation Treatment
After deposition CdTe must be activated by a special treatment based on
a chemical reaction between CdTe and Cl. This treatment has been
performed and studied in many different ways by researchers since the late
eighties, but it is still under discussion.
It is believed that this performs s doping of CdTe and recombination centers
like grain boundaries seem to be passivated [13]. A recrystallization of the
grains, an enlargement of the grain size, a change in the preferred
orientation, the intermixing of the CdS and CdTe layers with reduction of
the lattice mismatch [14][15] are considered a consequence of the
following reaction:
𝐶𝑑𝐶𝑙2 (𝑠) + 𝑂2 (𝑔) + 𝐶𝑑𝑇𝑒(𝑠) ⟺ 𝑇𝑒𝐶𝑙2 (𝑔) + 2𝐶𝑑𝑂(𝑠)
1-10
Electrical characterization of high performance CdTe solar cells.
11
12
CdTe cell fabrication
In general efficiencies increase from 6-7 % up to 18.7 %, which is the
current world record.
Our process include two different activation treatments:
 CdCl2 methanol saturated solution bath,
 Freon®.
The first is performed by dissolution of precise amounts of CdCl2 in
methanol in order to have a known saturation level. This solution is
deposited on the CdTe surface just after deposition, it is dried in air and
afterwards heated at 410 °C for 30 min (see Chapter 4).
The latter is a gaseous treatment based on Freon® and Ar gases whose
possible advantages and backwards are discussed with major details in
Chapter Chapter 3.
In this dissertation I will refer to samples which have not received the
activation treatment as as-deposited.
1.3.5 Etching and Back Contact
As already written in paragraph 1.3.1, contacts quality is very important to
extract carriers from the device. Back contact is needed to extract carriers
from the CdTe (p-type). Unfortunately CdTe has a high electron affinity,
therefore there are not so many metals with sufficiently high work function
suitable to form an ohmic contact [16].
Many back contacts have been developed and used (e.g. Sb2Te3, As2Te3,
etc.) [15], however the best results have been obtained with the addition of
Cu, which main drawback is a high diffusion tendency, that affects the
contact quality and the device performance as time goes (see Chapter
Chapter 6).
To form the back contact on our samples a thin Cu layer is deposited by
VE, its thickness ranges from 5 Å to 80 Å depending on other parameters
(e.g. CdTe thickness, treatment…). For our baseline Cu is deposited in 20 Å
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Introduction
thickness. To protect Cu from oxidation 500 Å of Au are deposited on it.
Finally the sample is annealed at 190 °C for 20 min.
When our samples are treated performing CdCl2 saturated solution
deposition, the surface must be cleaned and prepared before the back
contact deposition. This is done dunking the sample in a Bromine-Methanol
(B-M) solution bath for few seconds. This is usually addressed as surface
etching (or just etching).
1.4 Thesis Contents
In the next chapters I will discuss some of the main open issues of CdTe
technology addressing them by means of deep electrical characterization.
In the next chapter the electrical techniques used to characterize the
sample will be explained from a theoretical and practical point of view. In
chapters 3 and 4, I will show how these techniques have been used to bring
out important information on the activation treatment: comparing our two
different activation treatments (Freon® and CdCl2 saturated solution), and,
afterwards, comparing samples differently treated by a novel treatment
modulation.
Similar approach has been used to address CdTe thickness scaling (Chapter
5) and Cu/Au back contact degradation (Chapter 6). Discussion and
conclusions will follow.
From the third chapter to sixth have been published as papers or
proceeding as shown in the list of publications.
Electrical characterization of high performance CdTe solar cells.
13
14
References
1.5 References
[1] D.M. Chapin, C.S. Fuller, and G.L. Pearson. Journal of Applied Physics,
(1954).
[2] Photovoltaics Report. Fraunhofer Institute For Solar Energy Systems Ise,
Freiburg, (December 11-2012).
[3] Martin A. Green, Keith Emery, Yoshihiro Hishikawa, Wilhelm Warta and
Ewan D. Dunlop. Progress In Photovoltaics: Research And Applications,
2013.
[4] www.nrel.gov/ncpv/
[5] Parag S. Vasekar, Anant H. Jahagirdar, Neelkanth G. Dhere, Thin Solid
Films, 518 7, 1788–1790. (2010)
[6] R.H. Bube. Photovoltaic Materials. Imperial College Press. London 1998.
[7] B. O'Regan, M. Grätzel, Nature 353, 737 - 740 (24 October 1991).
[8] www.solarbuzz.com/facts-and-figures/retail-priceenvironment/module-prices.
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Introduction
[9] Zayed J, Philippe S., Int J Toxicol. 2009 Jul-Aug;28(4):259-65.
[10] V.M. Fthenakis. Renewable and Sustainable Energy Reviews, 13 (2009)
2746–2750.
[11] V. M. Fthenakis. Renewable and Sustainable Energy Reviews, 8 (2004)
303–334.
[12] J. Poortmand, V. Arkhipov. Thin Films Solar Cells, Wiley (2006).
[13] B.E. McCandless, Proc. of Mat. Res. Symp., 668, 2001, p. H1.6.1.
[14] S. Pookpanratana, X.Liu , N. R. Paudel, L. Weinhardt, M. Bar, Y.
Zhang, A. Ranasinghe, F. Khan, M. Blum, W. Yang, A. D.
Compaan, C. Heske, Applied Physics Letters, 97,17, 172109-1 – 171093
[15] A. Romeo, M. Terheggen, D. Abou-Ras, D. L. Batzner, F.-J. Haug, M.
Kalin, D. Rudmann and A. N. Tiwari, Prog. Photovolt: Res. Appl. 12
(2004) 93-111.
[16] S.H. Demtsu. Impact Of Back–Contact Materials On Performance And
Stability Of Cds/Cdte Solar Cells. Dissertation, 2006.
Electrical characterization of high performance CdTe solar cells.
15
16
References
Chapter 2
Electrical characterization
2.1 Introduction
Solar cells characterization is a fundamental step for the process
development, it is an unavoidable feed-back for processes improvements.
Empirical approach is surely faster and easier, and probably, the most
suitable to start a process setup, however to improve, in order to have
good results in devices fabrication, deep investigation and interpretation is
needed.
In material science many investigation techniques have been developed in
order to analyze the morphology, the composition, the optical and the
electrical properties, etc. Electrical characterization techniques occupy a
relevant position in the PV materials investigation, mainly due to the
possibility to analyze the finished device. Unfortunately, measured
parameters are affected by many different factors, thus data interpretation
is critical.
In this chapter I will introduce the basic theory of the techniques I used to
characterize our samples, , whereas measurement protocols and details will
be presented in Appendix A.
17
18
Current Voltage (J/V)
2.2 Current Voltage (J/V)
In paragraph 1.2 the equivalent circuit of a solar cell and its equation have
been already described. By applying a voltage ramp to the external contacts
and measuring the current flow it is possible to trace the Current-Voltage
curve (J/V).
In Figure 2-1 the typical J/V for our CdS/CdTe base-line is shown:
14
40
2
20
10
Pm
8
6
4
10
Vm
2
0
0
-10
Voc
Jm
Jsc
-2
2
Current Density [mA/cm ]
30
12
845
-22,3
690
-19,6
71,9
13,5
Power [mW/cm ]
Parameters
Voc [mV]
Jsc [mA/cm2]
Vm [mV]
Jm [mA/cm2]
FF [%]
Eta [%]
-4
-6
-20
-8
-30
-10
-0,4
-0,2
0,0
0,2
0,4
0,6
0,8
1,0
Voltage [V]
Figure 2-1. CdS/CdTe base-line J/V curves and parameters.
J/V analysis is considered the basic characterization for PV devices since
many electrical parameters can be extracted, giving information about the
device structure and material properties. Referring to the parameters
definition and formulas in paragraph 1.2, Voc and Jsc can be directly obtained
from a J/V curve. Moreover from measured values of J and V it is possible
to calculate:
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𝑃 =𝐽∗𝑉
2-1
𝑑𝑃
𝑑𝑉
2-2
=0
Solving for V, Vm is the result of eq. 2-2 and Jm is the related current value
calculated by eq. 1-5.
Thus, using equation 1-6 1-7 FF and η can be calculated. Furthermore, other
information can be estimated such as Rs, Rsh , A and J0.
Rsh is a lumped resistance connected to many physical factors as pin-holes,
shunting paths, inhomegeneity of the films, etc. It is calculated as follow [1]:
𝑑𝐽 −1
𝑅𝑠ℎ = (𝑑𝑉) |
2-3
𝐽𝑠𝑐
Rs is connected to materials and contacts resistance, it can be extracted by
the comparison of J/Vs in dark and light condition, measuring the voltage
difference for each current value Rs is determined as function of J [2].
Unfortunately these extractions are often very challenging, because
simplified models work only when the parameters are independent by light
intensity and/or voltage. Therefore usually J/V numerical fittings are
preferred to graphical extractions.
Another interesting approach is to perform J/Vs at different temperature
in dark condition. In this thesis I will address this measurement as J/V-T.
Taking into account the expression for J0 [3]:
𝐸
𝑎
𝐽0 = 𝐽00 𝑒𝑥𝑝 [𝐴𝑘𝑇
]
2-4
Electrical characterization of high performance CdTe solar cells.
19
20
Current Voltage (J/V)
Where J00 is a weak function of temperature and Ea is the activation energy.
Passing to logarithms we obtain:
𝐸
𝑎
𝑙𝑛(𝐽0 ) = 𝑙𝑛(𝐽00 ) + 𝐴𝑘𝑇
2-5
By dark-J/Vs numerical equation fitting, it is possible to extract A(T) and
J0(T) at different temperature and plot eq. 2-5 over 1/T in a semilogarithmic scale, where Ea is the slope of the linear correction [2-4] (see
Figure 2-2).
Value
Aln(J0) [mAcm-2]
-30
Ea [eV]
-35
Slope
Standard Error
1,439
0,041
-16,740
0,47752
1,8
1,7
Adj. R-Square 0,99433
-40
-50
-55
-60
A [-]
-45
a)
1,6
1,5
1,4
3,2
3,4
3,6
3,8
4,0
1000/T [K-1]
4,2
4,4
b)
220
240
260
280
T [K]
300
320
Figure 2-2. a) Ea extraction from dark J/V for our CdS/CdTe base-line. b) Ideality
Factor temperature dependency for CdS/CdTe base-line.
If the extracted Ea coincides with the absorber bandgap it is possible to
conclude that recombination takes place mainly in the SCR and/or in the
bulk CdTe (Figure 2-3b and c), if it is sensibly bigger it takes place mainly at
the CdS/CdTe interface (Figure 2-3a) [2, 4].
Furthermore, from the ideality factor temperature dependency (see
Figure 2-2b), it is possible to conclude whether recombination process is
purely SRH or if it is enhanced by tunneling via traps as described by Rau et
al. [4].
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Electrical characterization
Figure 2-3. CdS/CdTe band diagram showing the main recombination
mechanisms: a)Interface Ea>Eg, b) SCR Ea=Eg and c) Bulk CdTe Ea=Eg.
2.3 Admittance Techniques
Admittance measurements are performed applying to the sample a
superposition of two signals: direct current voltage (Vdc) and alternate
current voltage (Vac), and then measuring the current response (J) (see
Figure 2-4a). Dividing the output current phasor by the input voltage phasor
admittance can be calculated [2].
𝑌=
𝐽
𝑉𝑑𝑐 +𝑉𝑎𝑐
𝐶=
𝐵
𝜔𝑎𝑐
= 𝐺 + 𝑗𝐵
2-6
2-7
Where Y is the admittance, G is the conductance and B is the susceptance;
C is the capacitance and ac the angular velocity (ac=2fac, where fac is Vac
frequency). G and B can be easily separated because they are in
quadrature.
Electrical characterization of high performance CdTe solar cells.
21
22
Admittance Techniques
A solar cells is generally modeled as follow:
Figure 2-4. a) Parallel circuit for admittance measurements. b) Admittance phasor
diagram.
Where Rsc and Rpc are the series and parallel resistance respectively, for the
whole circuit. To have a reliable extraction of C it is important to ensure a
high quality factor (Q) or low dissipation factor (D).
𝑄 = 𝐷 −1 =
|𝐵|
𝐺
𝜋
= 𝑡𝑎𝑛 ( 2 − 𝜑)
2-8
Usually it is enough to ensure Rsc<<Rpc. Refer to Appendix A for more
details.
To investigate the solar cells by admittance techniques the depletion
approximation must be assumed, which consists of the following
assumptions:



SCR is fully depleted of free carriers,
SCR ends abruptly,
SCR is precisely defined.
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For thin film devices this approximation is usually to strict, nevertheless
admittance measurements are considered an important point to start
analysis and discussion on devices properties [2].
2.4 Capacitance Voltage (C/V)
Capacitance voltage technique is a type of admittance measurements,
usually performed in diode-based devices, to investigate semiconductors
structure and properties. Considering a solar cell depletion region as an
insulator and the neutral regions as conductors, it is possible to see it as a
planar capacitor which capacitance is given by [5]:
𝑄
𝐶=𝑉 =
𝜀𝑟 𝜀0 𝐴
𝑊
2-9
Where:
 Q is the SCR electrical charge,
 V the electrostatic potential,
 A the area,
 W the depletion region width,
 0 free space permittivity,
 r the material relative dielectric constant.
Similarly it is possible to formulate capacitance in differential way [5]:
𝑑𝑄
𝐶 = 𝑑𝑉
2-10
In CdS/CdTe thin film solar cell it is possible to consider the depletion region
extending mostly in the CdTe (p-side of the device) due to the large doping
difference compared with CdS (n-side). Now considering a single acceptor
state density (NA) close to the valence band [5]:
Electrical characterization of high performance CdTe solar cells.
23
24
Capacitance Voltage (C/V)
2𝜀𝑟 𝜀0 (𝑉𝑏𝑖 −𝑉𝑑𝑐 )
𝑞𝑁𝐴
𝑊=√
2-11
And so from eq. 2-9 and 2-11 [2]:
1
𝐶 −2
2
= 𝐴2 𝑞𝑁
𝐴 𝜀𝑟 𝜀0
(𝑉𝑏𝑖 − 𝑉𝑑𝑐 )
2-12
Eq. 2-12 is usually reported on Mott-Schottky plot as in Figure 2-5 (inset).
1
2
𝑁𝐴 = 𝐶 −2 = − 𝐴2 𝑞𝜀
𝑟 𝜀0
[
𝑑(𝐶 −2 )
𝑑𝑉𝑑𝑐
]
2-13
Hence, sweeping Vdc and measuring the capacitance variation, NA and W
can be calculated using eq. 2-11 and 2-13. Finally, plotting NA over W, the
doping profile is obtained as shown in Figure 2-5.
1E9
1E8
2
1E17
4
2
A /C [m /F ]
-3
1E16
1E15
Mott-Schottky
2
Charge Density [cm ]
1E18
1E7
-2,0
-1,5
-1,0
-0,5
0,0
0,5
Voltage [V]
1E14
0,5
1,0
1,5
2,0
2,5
3,0
Distance from the junction [m]
Figure 2-5. Charge Density profile for CdS/CdTe base-line. In the inset the relative
Mott-Schottky plot.
Despite only Vdc appears in these equations, Vac is still needed. At a given
temperature, ac should be low enough to allow carriers to move rapidly in
and out the depletion region edge, and generate the alternate current
detectable by the instrument.
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Nevertheless the junction capacitance variation with Vdc is determined only
by the charges at the edge of the depletion region, giving the possibility to
profile the SCR charge density. If a dominant ionized shallow defect is
supposed to be present C/V profiling brings out the free carriers density [6].
This holds true only if any density of states is present deep in the
bandgap. In this case, there is an additional contribution to the measured
capacitance due to the change of the occupancy state where the electronic
level of the defect crosses the quasi-Fermi level (xc).
Figure 2-6. Deep defect contribution due to Vac.
In such conditions the free carrier density will be overestimated by this
technique, while W will be underestimated [6][2]. However, in the next
paragraph, I will show how comparing C/V profiles to DLCP profiles is a
suitable way to estimate the deep defects concentration within the
depletion region.
Electrical characterization of high performance CdTe solar cells.
25
26
Drive Level Capacitance Profiling
(DLCP)
2.5 Drive Level Capacitance Profiling (DLCP)
Drive level capacitance profiling has been developed to overcome the
intrinsic limitation of C/V technique. DLCP is a purely dynamic technique
stimulating defects response only by Vac.
𝐶(𝜕𝑉) = 𝐶0 + 𝐶1 𝜕𝑉 + 𝐶2 (𝜕𝑉)2 + ⋯
2-14
Therefore sweeping Vac amplitudes and measuring the device capacitance,
the coefficients C0, C1… in eq. 2-14 can be extracted by polynomial
interpolation. Taking into account only the first two terms a linear
correction can be applied, which intercept (C0) brings out the constant
capacitance determined by Vdc (that correspond to the capacitance
measured by C/V techniques in the ideal case). The slope of the linear
correction is C1 and it is possible to demonstrate that [6]:
𝐶0 = (𝜀
𝐴|𝜌𝑒 |𝜀𝑟 𝜀0
𝑟 𝜀0 𝐹𝑒 +|𝜌𝑒 |𝑥𝑒 )
𝐶1 = −
𝐴𝜌𝑒2 (𝜀𝑟 𝜀0 )2
2(𝜀𝑟 𝜀0 𝐹𝑒 +|𝜌𝑒 |𝑥𝑒 )3
2-15
Whit e the charge density and Fe the electric field evaluated at x=xe.
And finally
𝑁𝐷𝐿 = − 2𝑞𝜀
𝑊=
𝜀𝑟 𝜀0 𝐴
𝐶0
𝐶03
2
𝑟 𝜀0 𝐴 𝐶1
=
|𝜌𝑒 |
𝑞
2-16
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In this thesis DLCP and C/V profiles are usually presented together, because
by comparison deep defects density can be estimated as shown in Figure
2-7.
+0,65 V
-3
Charge Density [cm ]
1E16
0V
DLCP
C/V
1E15
-2 V
Deep defects
contribution
1E14
0,0
0,5
1,0
1,5
2,0
2,5
Distance from the junction [m]
Figure 2-7. CdS/CdTe base-line C/V and DLCP profiles comparison.
2.6 Admittance Spectroscopy (AS)
In our typical analysis, AS represent a very important step for the
complete electrical characterization. So far I have explained how C/V and
DLCP can be used to extract information about either deep or shallow
defects density, by AS technique it is possible to identify the dominant
defects.
Considering the case of a single dominating acceptor with energy Et deep
in the gap and with characteristic frequency expressed by the following
equation [7]:
1
𝜔𝑡 = 𝜏 = 𝑒𝑝 + 𝑐𝑝
𝑡
2-17
Electrical characterization of high performance CdTe solar cells.
27
28
Admittance Spectroscopy (AS)
𝑒𝑝 = 𝑁𝑣 (𝑇)〈v𝑡ℎ 〉𝜎𝑝 𝑒𝑥𝑝 [−
𝐸𝑡 −𝐸𝑉
]
𝑘𝑇
𝑐𝑝 = 𝑁𝑣 (𝑇)〈v𝑡ℎ 〉𝜎𝑝 𝑒𝑥𝑝 [−
𝐸𝐹 −𝐸𝑉
]
𝑘𝑇
2-18
Where cp and ep are the hole capture and emission rate respectively, 0 is a
constant pre-factor, <vth> is the average value of holes thermal velocity and
p is the trap capture cross section. It is worth to underline that t is
determined only by p and Et, considered to be temperature independent.
Referring to Figure 2-6, at the crossing point (xc) EF=Et, hence ep=cp, it means
that the same amount of carriers (holes) are captured and emitted by the
trap. As long as x<xc Et<EF then cp<ep traps are mainly unoccupied (i.e.
ionized charges) whereas for x>xc results Et>EF and cp<ep, traps are mainly
occupied (neutral charge).
In order to experimentally determines t, AS measurements are
performed sweeping the frequency (ac) of a small amplitude Vac signal at
fixed temperature and Vdc bias. The last one determines the band bending
and then xc. In this way as long as ac<t carriers can be captured and
emitted, however when ac>t carriers will be not enough quick and
capacitance will be determined only by Vdc.
In the presence of a dominant deep acceptor responding to Vac, the AS is a
step-like curve as Figure 2-8a.
abs(facdC/dfac) [nF]
C [nF]
1,5
1,0
0,5
2
10
3
10
4
10
fac [Hz]
5
10
223 K
0,8
Temperature
2,0
6
10
280 K
0,6
0,4
0,2
0,0
2
10
3
10
4
10
fac [Hz]
5
10
6
10
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Figure 2-8. CdS/CdTe base-line a) AS curves and b) t peaks at different
temperatures.
By differentiation, –facdC/dfac can be plotted vs. frequency (fac, where
ac=2fac) and the peak reveals the t of the defect [2][7].
So at the crossing point xc we can write:
𝜔𝑡 = 2𝜈 𝑒𝑥𝑝 [−
𝐸𝑡 −𝐸𝑉
]
𝑘𝑇
2-19
dividing by T2 and solving
𝜔
2𝜈
𝑙𝑛 (𝑇 2𝑡 ) = 𝑙𝑛 (𝑇 2 ) −
𝐸𝑡 −𝐸𝑉
𝑘𝑇
2-20
Changing the temperature the characteristic peak changes, then tracing its
evolution (as in Figure 2-8b) it is possible to build the Arrhenius plot in
Figure 2-9. From the linear correction of this curve it is possible to calculate
p from the intercept and Et from the slope [7].
1

Ln(1/ )
2
0
Value
Intercept
-1
-2
Slope
Standard Error
23,6
0,51
-6116
135
Ea [meV]
527
12
Sa [cm2]
7,3E-12
6,9E-22
Adj. R-Square
3,4
0,998
3,6
3,8
4,0
4,2
1000/T
Electrical characterization of high performance CdTe solar cells.
29
30
Temperature and Frequency in
Admittance techniques.
Figure 2-9. Extraction of Et and sigma for a deep defect in CdS/CdTe base-line
2.7 Temperature and Frequency in Admittance
techniques.
It is important to mention the effect of frequency and temperatures on
the profiling either C/V and DLCP. In the next chapters profiles will be
presented in a wide range of temperature and at different frequencies to
add more information.
Consider the following equation [6]:
2𝜋𝜈
𝐸𝑒 = 𝑘𝑇 𝑙𝑛 (𝜔 )
2-21
𝑎𝑐
Where
𝜈 = 𝜈0 𝑇 2 = 𝑁𝑣 (𝑇)〈v𝑡ℎ 〉𝜎𝑝
2-22
Ee is called the limiting energy of the electronic state. It represents the
energy upper limit for carriers to occupy a state. So for a given
temperature, a trap state Et with p can capture and emit free carriers,
quick enough to follow Vac, only if Et-EV < Ee.
Also
1
𝜏𝑎𝑐 = 𝜔
𝑎𝑐
1
𝐸
= 2𝜋𝜈 𝑒𝑥𝑝 (𝑘𝑇𝑒 )
2-23
This issue can be addressed from another point of view: for a given
combination of temperature and frequency, if carriers relaxation time is
smaller than ac the occupation of the defect contributes to the final
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Electrical characterization
capacitance. Hence, changing T and ac, Ee changes and consequently the
occupancy of the defects.
For C/V, increasing the frequency (or reducing the temperature) just
enough to have Et>Ee should avoid deep defects contribution to final
capacitance. This is called defect freeze-out.
For DLCP the following equation is valid [6]:
𝑁𝐷𝐿 =
|𝜌𝑒 |
𝑞
𝐸 +𝐸𝑒
= 𝑝 + ∫𝐸 0𝑉
𝐹
𝑔(𝐸, 𝑥𝑒 )𝑑𝐸
2-24
Where p is the free carriers density, EF0 is the Fermi level in the bulk and
g(E,xe) is the density of states at a distance xe from the junction. When ac is
sufficiently high (or T sufficiently low) the contribution of the integral to the
estimated charge is negligible, however dramatically reducing the
frequency Ee increases extending the integral range and adding to the
estimated charge NDL contribution by defects over EF0. Hence, at very low
frequency (or high temperature) DLCP and C/V profiles should coincide.
Finally in the case of AS, to sweep the frequency can be interpreted as a
progressive reduction of Ee, thus as long as ac<t Ee>Et and deep state
contribute to the measured capacitance, however when ac>t Ee=Et the
defect freeze-out occurs and capacitance is determined only by Vdc,.
Electrical characterization of high performance CdTe solar cells.
31
32
References
2.8 References
[1] S. S. Hegedus, W. N. Shafarman, Prog. Photovolt, Res.Appl. 2004,
12,155-176.
[2] J. Heath, P. Zabierowski, Capacitance spectroscopy of thin film solar
cells, in Advanced Characterization Techniques for Thin-Film Solar Cells
(Eds. U. Rau, T. Kirchartz and D. Abou-Ras), WILEY-VCH, (2011).
[3] U. Malm, J. Malmstrom, C. Platzer-Bjorkman, L. Stolt, Thin Solid Films
480–481 (2005) 208–212.
[4] U. Rau, A. Jasenek, H.W. Schock, F. Engelhardt, Th. Meyer, Thin Solid
Films 361-362 (2000) 298-302
[5] D. L. Pulfrey, N. G. Tarr, Introduction to microelectronic devices,
Prentice-Hall International, Inc. (1989).
[6] J. T. Heat, J. D. Cohen, W. N. Shafarman, J. Appl. Phys., 95(3) (2004)
1000.
[7] F. H. Seymour, V. Kaydanov, T. R. Ohno, , J. Appl. Phys., 100 (2006),
033710.
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Electrical characterization
Electrical characterization of high performance CdTe solar cells.
33
Chapter 3
Freon ® activation treatment for low
temperature fabrication process
3.1 Introduction
The best CdS/CdTe device performances are usually obtained by high
temperature deposition processes. This seems to be connected with the
higher recrystallization of CdTe layers. On the other hand, making solar cells
in superstrate configuration at lower temperature, allows the application of
different substrate materials to be used in place of glass. Furthermore for
industrial production low temperature processes are usually preferred.
Moreover, a possible way to make more attractive processes for industries
is to avoid wet steps and toxic materials.
It has been proved that a possible alternative to the common activation
treatments is a gaseous treatment based on a mixture of Ar and Freon®,
which are non-toxic gasses. This treatment has been developed at Parma
University laboratories on devices deposited by Close Space Sublimation
(CSS) performed at temperatures up to 550 °C [1]. At our laboratory Freon®
34
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Freon® activation treatment
treatment has been optimized for our low temperature devices. It is
performed by fluxing a mixture of Ar and HCF2Cl (Freon® R-22) in a closed
chamber at temperatures ranging between 390 °C and 450 °C [1]. The
relative pressure of Freon® ranges between 2 % and 6 %. Samples are held
at this condition for 25 minutes. At around 400°C Freon® dissociates,
freeing chlorine, which is then reacting with CdTe (as in eq. 3-1) forming
CdCl2 which recrystallizes the layer and passivates the grain boundaries [2].
𝐶𝑑𝑇𝑒 (𝑠) + 2 𝐶𝑙2 (𝑔) ⟺ 𝐶𝑑𝐶𝑙2 (𝑔) + 𝑇𝑒𝐶𝑙2 (𝑔)
3-1
Back contacts are made with a stack of Cu and Au and subsequent
annealing in air as described in paragraph 1.3.5. The amount of Cu has been
optimized according to the different CdTe activation treatments applied.
Unfortunately resulting performance are sensibly much lower than for CSS
devices. In this chapter I will analyze different samples made either by VE or
CSS and treated either by Freon® or our usual CdCl2 bath. Results will be
compared in order to explain why Freon® treatment is not suitable to
activate devices deposited at low temperature.
3.2 Experimental
Within this study three kinds of samples were compared:
 VE-CdCl2: CdS and CdTe deposited by VE and treated by usual CdCl2methanol saturated solution bath (see paragraph 1.3.4),
 VE-Freon® : CdS and CdTe deposited by VE and Freon® treatment,
 CSS-Freon® : CdTe deposited by CSS on a sputtered CdS film and
afterwards Freon® treatment.
Performances are summarized in Table 3-1.
Electrical characterization of high performance CdTe solar cells.
35
36
Current Voltage (J/V)
Table 3-1. Typical performances of the three kinds of samples.
Absorber
Voc
[mV]
Jsc
[mA/cm2]
FF
[%]
η
[%]
VE-Freon®
VE-CdCl2
CSS-Freon®
655
704
768
20.1
25.6
21.7
50
58
64
6.6
10.4
10.7
The first two sets of samples are identical a part of the treatment and the
back contact while the third has been kindly provided by Parma University.
3.3 Current Voltage (J/V)
2
Current Density [mA/cm ]
In Figure 3-1 the typical J/V curves of the three kinds of samples.
40
Sample
VE-CdCl2
Efficiency[%]:
6,6
58
50
64
Voc[mV]:
704
655
768
Jsc[mA/cm2]:
25,6
20,1
21,7
FF[%]:
20
0
VE-Freon CSS-Freon
10,4
10,7
VE-CdCl2
VE-Freon
CSS-Freon
-20
0,0
0,5
Voltage [V]
Figure 3-1. Typical J/V curves of the three sets of samples.
1,0
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Freon® activation treatment
Comparing Voc of the two VE samples we can see that Freon® one is
definitely lower, although is very low in both cases, suggesting low junction
quality or poor doping. The highest Jsc is for the VE-CdCl2 sustaining the first
hypothesis. CSS-Freon® shows the highest FF yielding general better device
quality.
3.3.1 Transport properties.
Dark J/V–T characteristics for all cells were measured in the range 300 K –
360 K and the sample was either placed in a LN2-cryostat or on a Peltier–
controlled substrate holder. Where possible, the saturation current J0 and
the diode ideality factor A were extracted by fitting the single diode
equation with series (RS) and shunting (rsh) resistances (see eq. 1-5).
It should be noted that the dark J/V curves for all cells above 300 K
exhibited instability due to a hysteresis, i.e. the value of the current for a
given voltage depended on the bias scan direction and the measurement
time duration. Hence, our fitting results are subject to some systematic
error, indicated where necessary. The fitting parameters are given as the
rough approximation. For this reason we restrict ourselves in the discussion
to a qualitative analysis only.
In order to extract the activation energy (Ea) and to define the transport
mechanism [3][4], it has been checked the ideality factors, ranging between
1.5 and 1.6, were not depending on the temperature. This procedure,
according to [5], allowed us to construct the modified Arrhenius plots, as
shown in Figure 3-2.
In both VE cells the barrier height was nearly the same, Ea ~ 1.35 eV ( 0.1
eV systematic error). We note that the saturation current J0 for the VEFreon® sample (circles) is smaller in the whole temperature range as
compared to the VE-CdCl2 cell (squares). Apparently, the Arrhenius plot for
Electrical characterization of high performance CdTe solar cells.
37
38
Space charge profiles.
the CSS-Freon® sample is not linear (triangles). This prevents us from
calculating the barrier height in this case. Nevertheless, we note that this
device exhibited the lowest J0 values among all the three samples.
Figure 3-2. Arrhenius plots of J0 comparing different combination of deposition
and treatments.
The deviation from linearity was due to the instability in shunting-like
resistance caused by a severe hysteresis effect (see the discussion below).
3.4 Space charge profiles.
The capacitance measurements were performed with an Agilent E4980A
LCR meter controlled by LabView via PC at Warsaw University of
Technology.
With regards to space charge distributions in Figure 3-3, open symbols are
C/V profiles and full symbols are DLCP profiles, both measured at room
temperature (RT) and 10 kHz. Doping concentrations in the SCR of CSSFreon® , VE-CdCl2 and VE-Freon® samples were estimated to be 2x1014 cm-3,
6x1013 cm-3, 3x1013 cm-3, respectively, as indicated in the figure by the
lowest values of the DLCP curves [6]. Deep defects contributing to
capacitance-voltage profiles were also detected. The difference between
the C/V and DLCP profile, indicating the lower bound for the concentration
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Freon® activation treatment
Charge density [cm-3]
of deep defects [7], is the highest for the CSS-Freon® sample (circles) and
amounts to 4x1014 cm-3. For the VE-Freon® device (triangles) the defect
1E15
VE-CdCl2
VE-Freon
CSS-Freon
1E14
1
2
3
Distance from junction [m]
Figure 3-3. C/V (open) and DL (full) space charge profiles. The estimation of free
hole concentrations indicated in the figure. The difference between C/V and DLCP
concentration indicates a lower bound for deep defect concentrations.
Electrical characterization of high performance CdTe solar cells.
39
40
Space charge spectroscopy
concentration varies from 1x1013 cm-3 at 2 µm up to 2.3x1014 cm-3 at
distances larger than 2.5 µm. In the VE-CdCl2 sample (squares) we detected
no large differences between the C/V and DLCP profiles around RT.
3.5 Space charge spectroscopy
In order to estimate deep defect parameters detected by SCR profiling
space charge spectroscopy was performed [7]. Admittance spectra (AS)
were measured by use of the HP4284A LCR meter. Capacitance transients
for deep level transient spectroscopy (DLTS) analysis (steady state bias UR= 1 V, amplitude ΔU = 1 V, 50 ms pulse width) were recorded by the 12 bit AD
converter (Advantech, PCL818HD) connected to the Boonton 72B
capacitance bridge operating at 1 MHz .
log(eT/T-2 )[s-1K-2]
10
0
10
-1
10
-2
10
-3
10
-4
10
-5
EA~ 600 meV
AS
DLTS
EB ~700 meV
2,9
3,0
3,1
1000/T [1/K]
3,2
Figure 3-4. Arrhenius plot of AS and DLTS data for VE-Freon® sample.
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Freon® activation treatment
In the available temperature range only the VE-Freon® sample exhibited a
step-like AS response measured at 0 V DC bias (defect A) as well as DLTS
peaks (defect B). The activation energies extracted from the corresponding
Arrhenius plots (Figure 3-4) are EA = 620 meV for AS and EB = 700 meV for
DLTS data (the sign of the DLTS peaks indicates that defect B is a hole trap).
The following remarks we estimate the systematic error of the activation
energies to be ~ 100 meV:
(i) The A defect: the peak after differentiation of the AS signal was quite
broad and for higher temperatures additionally overlapped by some deeper
response. Thus the assignment of the maxima was not precise. Moreover,
since this defect is responsible for the freeze-out (see below), the time
constants (see paragraph 2.7) are influenced by the occupation factor. This
becomes significant if the trap concentration is in the same range of the
free holes concentration [7], as in this case.
(ii) The B defect: it was possible to indicate the maxima for only 3 rate
windows in the available temperature range; additionally the DLTS peaks
were overlapped by some other higher temperature signal.
Shallow defects freeze-out is usually observable at very low temperature,
in this condition the occupation of defects close to the valence band is very
small whereas deep defects occupation is dramatically reduced. Moreover,
Ee (see eq. 2-21) is very small and further reduction due to high ac can
cause Ee<Et-EV, hence the freeze-out of the shallow defects.
However in VE-Freon® samples, carriers freeze-out has been noticed even
at temperatures around 300 K, suggesting that a deep defect controls the
free-holes concentration. With regards to the evolution of the admittance
peaks with temperature, we can assume that the defect A is the dopant for
this kind of sample.
In Figure 3-5 two DLCP profiles are shown, for low (squares, fLO = 104 Hz,
the defect follows Vac) and high frequency (circles, fHI = 106 Hz; the defect
Electrical characterization of high performance CdTe solar cells.
41
42
Hysteresis effect.
Charge density [cm-3]
does not follow Vac). The latter indicates a fully depleted absorber layer due
to the depletion region extension, reaching the geometrical limit of the
device.
10
16
10
15
10
14
VE-Freon 10 kHz
VE-Freon 1 MHz
CdTe Thickness
10
13
1
2
3
Distance from junction [m]
Figure 3-5. Influence of the freeze-out of free holes in VE-Freon® sample
associated with defect A.
3.6 Hysteresis effect.
We have observed that above RT the results of electrical measurements
start to depend strongly on the direction of the bias scan.
Space charge width [m]
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Freon® activation treatment
VE-Freon
1,5
1,0
CSS-Freon
0,5
,
,
-0,8
: +0.6 V -> - 0.7 V
: -0.7 V -> +0.6 V
-0,4
0,0
Voltage [V]
0,4
Figure 3-6. Influence of the direction of the DC bias scan direction on the space
charge width measured for sample CSS-Freon® (circles) and VE-Freon®
(triangles) at 350 K and the AC frequency 104 Hz.
In all three samples the application of a reverse bias increases quasipermanently a negative charge in the space charge region, which shrinks
the SCR width (increased capacitance) when scanned from negative to
positive biases.
In a subsequent measurement (i.e. from forward to reverse bias) the
positive charge is accumulated and the SCR width becomes wider (the
capacitance is lower) for the whole DC voltage range, as compared to the
previous scan in the opposite direction. This is illustrated in Figure 3-6 for
the samples CSS-Freon® (circles) and VE-Freon® (triangles).
Concerning the dark J/V characteristics, the CSS-Freon® sample was most
strongly affected (Figure 3-7 circles): the shunting-like current (voltage
range from 0 V to 0.5 V) has increased by more than one order of
magnitude while switching from the reverse-forward (full symbols) to the
forward-reverse (open symbols) bias scan direction. For both VE samples
the differences were of a different kind and a much smaller magnitude: in
the CdCl2-treated cell only the series-like resistance for biases between
Electrical characterization of high performance CdTe solar cells.
43
44
Discussion
0.6 V and 1.4 V is slightly modified (inset of Figure 3-7 squares), whereas for
the Freon® activated device additionally the whole reverse-forward curve is
shifted downwards as compared to the forward-reverse branch (the main
diode current is reduced by a factor of ~1.5, triangles in Figure 3-7). It
should be noted that the time constant of the hysteresis effects is in the
order of several seconds even at 360 K.
3.7 Discussion
Among all the differences detected among the samples with CSS- and VECdTe absorbers the most striking one is the much lower doping of VE
devices (see Figure 3-3). Now, comparing the defect parameters detected in
our samples with the literature data [8][9], we note that the A level (defect
signatures from AS) agrees pretty well with the H3- and the B level (DLTS)
with the H5-defect. This allows us to interpret the extremely low doping in
10
3
10
1
-2
Current Density [mAcm ]
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10
10
1
10
0
Voltage [V]
1,0
1,5
-1
-2
Current [mAcm ]
10
10
0,5
-3
10
rev to fwd VE-Freon
fwd to rev VE-Freon
rev to fwd CSS-Freon
fwd to rev CSS-Freon
-1
rev to fwd VE-CdCl2
fwd to rev VE-CdCl2
-5
0,5
1,0
Voltage [V]
1,5
Figure 3-7. Influence of the direction of the DC bias scan direction on dark J-V
measured for sample CSS-Freon® (circles), VE-Freon® (squares) and VE-CdCl2
(triangles).
VE samples as a lack of the H1 defects (adopting the nomenclature of [8,9]),
which are most probably VCd and/or its complexes with ClTe [10]. As a
consequence the VE-Freon® samples exhibit the freeze-out already at RT.
The lack of the H1 defect, or rather its too low concentration, seems to
have severe consequences for the performance of the VE-Freon® samples.
This is because for such a low doping (hole concentration ~1013 cm-3) the
nominal space charge width greatly exceeds the thickness of the VEElectrical characterization of high performance CdTe solar cells.
45
46
Discussion
absorber (<4 µm) and the front and back contact barriers interfere. This
leads to an inverse band-bending in the region where the electron-hole
pairs are generated, which is responsible, at least partially, for the observed
Jsc and FF deterioration in VE-Freon® devices.
According to [8] the presence of level H5 could be easily attributed to an
excess of sulfur diffusion into CdTe, that has been effectively measured by
spectral response (provided by EMPA,CH) where no CdS light absorption
was detected despite more than 0.3 micron window layer was deposited.
This would mean that on one hand the activation treatment is not sufficient
to dope the VE-CdTe and on the other hand it generates a very strong
intermixing of CdS and CdTe at the interface, reducing the Voc (by a
reduction of the band gap) and the fill factor.
At the first sight, the transport in all investigated devices seems to be
controlled by the Shockley-Read-Hall Recombination (SRH) in the SCR:
barrier heights correspond almost to the CdTe bandgap and the ideality
factors do not depend on the temperature in the range values between 1.5
and 1.6 [3-5]. Then, the most straightforward interpretation would link the
Voc to the space charge width and hence to the free holes concentrations. In
this simple picture the poor Voc of VE samples would be due to a very low
doping level.
Apparently, this model seems to be supported also by the J/V hysteresis
behavior, since the dark current is reduced for the reverse-forward scans,
when the SCR width is shrunken. However, it should be noted that despite
the strong resemblance of the hysteresis in C/V characteristics it differs very
much for the J/V curves (Figure 3-7): for the CSS-Freon® sample (circles) the
forward-reverse curve (open symbols) has a shunting-like current one order
of magnitude higher than the reverse-forward one (full symbols) but the
main diode current does seem not to change a lot (the difference vanishes
around 0.7 V), whereas for the VE-Freon® sample (triangles) there is no
shunting current in both directions at all. The only effect here is that the
forward-reverse curve (open symbols) is slightly above the reverse-forward
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Freon® activation treatment
(full symbols), which can be interpreted as a decrease of the saturation
current after application of the reverse bias. Finally, the only current that
changes during the hysteresis cycle in the sample VE-CdCl2 (inset of Figure
3-7) is the current dominated by the series resistance and/or the back
diode. So, the hysteresis effect in C/V is similar but in J/V it is totally
different. The plausible explanation of this discrepancy would rely on the
assumption that the main diode current in VE samples is limited by the back
contact recombination. This supposition could be justified by the fact that
in VE samples the whole absorber is depleted and the back contact is in the
space charge region. However, these issues, although very interesting, and
promising for the future investigations of the transport mechanisms, are
beyond the scope of this work.
3.8 Conclusions
Freon® treatment has demonstrated to be very effective for the activation
of CdTe layers deposited by CSS [1] and it is a very good way to simplify the
fabrication of CdTe solar cells. However if applied to CdTe deposited by
vacuum evaporation (low substrate temperature), the efficiencies of
finished devices are poor [11].
Within this study three kinds of samples were compared separately: one
made by CSS and treated with Freon® and one made by VE and treated by
CdCl2. Both samples show better performances than the VE-Freon® one.
Both comparisons bring out that all the three different samples present a
high concentration of deep defects. On the other hand VE-Freon® devices
show a smaller concentration of shallow defects resulting in lower free
carriers concentration. This is supported also by the freeze-out effect of the
charge carriers at room temperature and high frequencies that indicates
that the transport mechanism is dominated by defects not near to the
valence band. From space charge spectroscopy two different defects for VEFreon® samples have been detected. The first one has an activation energy
Electrical characterization of high performance CdTe solar cells.
47
48
References
of about 600 meV perhaps responsible of the charge transport and,
according to Seymour’s nomenclature [8][9], it could be indicated as H3.
The second one, placed even deeper in the band (700 meV) could be
associated to H5 defect. In vacuum evaporated samples, irrespective of the
post deposition treatment, no shallower defects have been detected.
Unfortunately, due to a pronounced hysteresis effect, no defect evaluation
was possible for CSS devices. CSS deposited CdTe is generally more
conductive and has higher crystalline quality. However CdCl2 treatment is in
general able to change the crystal quality of the VE-CdTe increasing the
electrical properties, even in our case where a slightly higher carrier
concentration, compared to the VE-Freon®, is measured. This is a
remarkable difference if we consider that, for the Freon treated samples,
the back contact was made with a double amount of Cu. This means that in
order to increase the doping level the VE-samples need a stronger
activation treatment, which Freon® is not able to deliver.
3.9 References
[1] N. Romeo, A. Bosio, A. Romeo, S. Mazzamuto and V. Canevari,
Proceedings from 21st Photovoltaic Solar Energy Conference, 4-8
September 2006, 1857-1860.
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Freon® activation treatment
[2] L. Zhang, J. L. F. Da Silva, J. Li, Y. Yan, T. A. Gessert, and S-H. Wei Effect of
Copassivation of Cl and Cu on CdTe Grain Boundaries, Physical Review
Letters 101, 155501-15504 (2008).
[3] U. Rau, A. Jasenek, H.-W. Schock, F. Engelhardt, and T. Meyer, Thin Solid
Films, 361-362 (2000) 298.
[4] V. Nadenau, U. Rau, A. Jasenek, and H.-W. Schock, J. Appl. Phys., 87(1)
(2000) 584.
[5] U. Malm, J. Malmström, C. Platzer-Björkman, and L. Stolt, Thin Solid
Films, 480-481 (2005).
[6] J. T. Heath, J. D. Cohen, W. N. Shafarman, J. Appl. Phys., 95,2004, pp.
1000-1010.
[7] J. Heath, P. Zabierowski, Capacitance spectroscopy of thin film solar
cells, in Advanced Characterization Techniques for Thin-Film Solar Cells
(Eds. U. Rau, T. Kirchartz and D. Abou-Ras), WILEY-VCH, (2011).
[8] F. H. Seymour, V. Kaydanov, T. R. Ohno, Proceedings from 2006 IEEE
World Conference on Photovoltaics Energy Conversion, Waikoloa,
Hawaii, May, 2006.
[9] F. H. Seymour, V. Kaydanov, T. R. Ohno, D. Albin, Appl. Phys. Lett., Vol
87, 153507, October, 2005 .
[10] Hofmann, D. M., Omling, P., Grimmeiss, H. G., Meyer, B. K., Benz, K. W.,
Sinerius, D., Phys. Rev. B 45 11, pp 6247-6250, 1992.
Electrical characterization of high performance CdTe solar cells.
49
50
References
[11] A. Salavei, I. Rimmaudo, V. Allodi, A. Romeo, A. Bosio, N. Romeo, S.
Mazzamuto, D. Menossi. Proceedings of 26th European Photovoltaic
Solar Energy Conference, 5-9 September 2011, Hamburg, Germany, pp
3030-3034.
Chapter 4
Effects of activation treatment on the
electrical properties of low
temperature grown CdTe devices
4.1 Introduction
I already described in Chapter 1 the effects of the activation treatment,
among them: re-crystallization and enlargement of the grains, preferred
orientation, reduction of the grain boundaries [1], generation of CdS and
CdTe intermixing layers with a reduction of the lattice mismatch [2][3].
Most important is the macroscopic effect on the performance of the solar
cell, which improves from efficiencies in the range of 6% up to the current
record efficiency of 18.7% [4].
CdCl2 activation treatment is generally optimized by following an empirical
process: adjusting the amount of CdCl2, the temperature and time of the
post-deposition annealing and then by testing the finished solar cell.
Generally there is a threshold of necessary amount of CdCl2 for having a
complete “transformation” of the absorber and a threshold above which
the treatment delivers an over-treated device.
51
52
Experimental
This study focuses on the effect of CdCl2 treatment on the device
parameters, not only in terms of solar energy conversion but also in terms
of electrical properties of the absorber. As a matter of fact the activation
treatment changes various electrical parameters among them carrier
concentration, conductivity, carriers mobility [5].
4.2 Experimental
At our labs, vacuum evaporated CdTe is typically treated by a saturated
solution of CdCl2 in methanol. Four kind of devices have been prepared
depositing different amounts of this solution on CdTe layers, dried in air
and annealed at 410 °C for 30 min, in order to modulate the effectiveness
of the treatment. The amount of solution has been measured in microliters. The whole TCO/CdS/CdTe/back contact and the Bromine-Methanol
etching were identical for all the samples. Final conversion efficiencies are
ranging, between 6 and 13% depending only by the differences in
treatment.
In typical solar cells made with the four different amount of CdCl2 taken in
consideration and their respective device parameters are shown. The overtreated sample has been made by depositing the saturated solution in the
range of tenth of ml.
Table 4-1. Current-Voltage parameters of four typical solar cells with different
treatment.
Treatment
Voc
[mV]
Jsc
FF
2
[mA/cm ] [%]
η
[%]
180 l
655
20.5
44.8
6.0
720 l
704
22.8
55.0
9.3
1800 l
768
23.3
64.7
11.9
Over-treated
840
20.7
50.2
8.7
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4.3 Current-Voltage (J/V)
In Figure 4-1 the typical J/V measurements for the four different sets of
samples are presented.
180 ul
Efficiency[%]
2
Current Density [mA/cm ]
Sample
10
0
-10
FF[%]
720 ul 1800 ul Over-treated
6
9,3
11,9
8,7
44,8
55
64,7
50,2
Voc[mV]
655
704
768
840
Jsc[mA/cm2]
20,5
22,8
23,3
20,7
180 l
720 l
1800 l
Over-Treated
-20
0,0
0,5
Voltage [V]
1,0
Figure 4-1. Typical J/V curves of the three sets of samples.
Performances rise as long as the amount of CdCl2 solution increases up to
the optimum value 1800 µl (open circles). The over-treated samples
performance (gray squares) is smaller, indicating that the upper limit for a
working treatment has been passed. It is worth to note that for the overtreated samples Voc is overestimated, since the J/V curve is crossing the xaxis not in a one-diode regime mode due to the strong roll-over.
Electrical characterization of high performance CdTe solar cells.
53
54
Current-Voltage (J/V)
Moreover the current densities for the low-treated (black squares) and the
over-treated samples are similarly lower than the other ones, a possible
explanation of this aspect will be discussed in the next paragraphs.
4.3.1 Transport Properties
-2
Aln(J0) [mAcm ]
Current-voltage measurements of several devices in the dark have been
made at different temperatures. The more significant ones are the graphs
made at temperatures between 200 K and 300 K. Currents have been
plotted in the logarithmic scale versus voltage and then numerically fitted in
order to extract, assuming a single diode model, the saturation current (J0)
and the ideality factor (A) (see paragraph 1.2, 2.2 [6] and [7]). These
parameters allow to graph the Arrhenius plot in Figure 4-2.
1800 l
720 l
Over-treated
-50
-75
210
T [K]
240
270
300
2,5
-100
A [-]
2,0
1,5
3,0
3,5
4,0
-1
1000/T [K ]
4,5
Figure 4-2. Arrhenius plot for 720µl, 1800µl and Over-treated samples. In the
inset: Ideality factors dependency from temperature.
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Effects of the activation treatment
Figure 4-2 shows the Arrhenius plots for the 720 µl, 1800 µl and overtreated samples, in the inset the related evolution of A with temperature is
shown. Unfortunately, samples treated with 180 µl, at low temperature
show in the measurement a too noisy current, preventing good parameters
extraction. The activation energy for each sample has been calculated by
the slope of the linear correction of the Arrhenius plots as explained in
paragraph 2.2.
Table 4-2 summarizes the collected data.
Table 4-2. Bandgap and ideality factor for the four differently treated devices.
Treatment
Adj. Rsquares
0.986
A [-]
180 l
T Range
[K]
320-290
1.44-1.53
Ea
[eV]
1.37
720 l
320-250
0.998
1.50-1.72
1.46
1800 l
320-225
0.994
1.40-1.70
1.44
Over-treated
320-280
270-211
0.998
0.994
1.97-2.15
2.58-2.81
2.2
1.72
At the same time the dependence of the ideality factor with temperature
has been taken into account (inset of Figure 4-2) in order to define the
transport mechanism: if the ideality factor remains constant a ShockleyRead-Hall (SRH) recombination away from the interface and the back
contact can be considered as the main transport mechanism (see paragraph
2.2 and [8]).
In the under-treated sample (180 l) the ideality factor is constant only at
high temperatures bringing out an activation energy of 1.37 eV, smaller
than the CdTe band gap, usually considered around 1.45 eV. It should be
noted that the linear correction for this kind of samples is possible only at
high temperature and then for few points. The best fittings and extractions
Electrical characterization of high performance CdTe solar cells.
55
56
Space charge profiling
are possible for the 720 l (triangles) and 1800 l (squares) samples that
have the higher efficiencies. The activation energies are very similar and
close to the CdTe bandgap. However, 1800 l case shows a slightly higher
dependence from the temperature, which suggests a more complex
transport mechanism, probably due to more extended CdS/CdTe
intermixing layer. This will be consistent with the doping profiles that I will
discuss in the next paragraphs.
In the over-treated case (circles), there is a much larger temperature range
in which the parameter extraction is possible. This suggests a higher doping
which allows high currents even at low temperatures. For these samples
two different SRH regimes are present, resulting in two different activation
energies, both higher than the typical CdTe bandgap. This can be explained
if we consider the recombination at the interface (see paragraph 2.2) as the
main transport mechanism, hence an even more extended intermixing
layer.
4.4 Space charge profiling
C/V and DLCP profiles have been measured in a wide temperature range
(between 150 K and 320 K), but for space reason only measurements at 200
K and 300 K are shown. Measurements have been repeated changing the
Vac frequency (ac=2fac see paragraph 2.3), in particular 50 kHz, 100 kHz
and 1 MHz, to analyze the defects response.
In Figure 4-3 typical DLCP and C/V profiles at 200 K and 50 kHz of the
differently treated devices are shown. In the inset profiles at 50 kHz and 1
MHz for 1800 µl case are compared.
At 200 K the low-treated samples (180 µl) (squares in Figure 4-3) show a
completely depleted absorber approaching the geometrical limit. This
reveals a very low doping concentration, confirmed by measurements at
300 K (squares in Figure 4-4) where due to the higher temperature it is
possible to extract the doping profile resulting to be very low.
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Effects of the activation treatment
A different situation is registered for the case of 720 l and 1800 l, which
present a higher doping concentration both at 200 K and 300 K
(respectively circles and triangles in Figure 4-3 and Figure 4-4). Moreover
both curves converge together close to 1 µm stating a real effective
increase in the defects concentration. On the other hand profiles differ
deep in the bulk: as a matter of fact in the 720 l sample the shallow
defects concentration remains constant in the absorber, while for the 1800
l sample it gradually increases as the junction approaches. Similar
behavior is observed also for the over-treated samples (stars) but with a
much higher doping level in all the range of temperatures (Table 4-3). With
regards to deep defects, it is possible to see that they contribute more and
more as the treatment increases, suggesting their concentration increases
at the CdS/CdTe interface, a similar effect is also reported by Burgelman et
Al. [9].
Table 4-3 summarizes rough estimations of the deep and shallow defects
concentration for the four sets of samples.
Table 4-3. Measured defects concentration in the differently treated CdTe devices.
Treatment
180 l
720 l
1800 l
Over-treated
Temp.
[K]
200
300
200
300
200
300
200
300
Shallow defect
[cm-3]
-2E13
2E13
7E13
2E13
4E13-2E14
5E13
1E14-9E14
Deep defects
[cm-3]
-<1E13
1E13
7E13
3E13
9E13
1E13
4E14
Electrical characterization of high performance CdTe solar cells.
57
58
-3
10
1800 l:
50 kHz
1 MHz
15
14
10
-
Charge Density [cm 3]
Charge Density [cm ]
Space charge profiling
4
10
5
6
Distance from junction [m]
14
180 l
720 l
1800 l
O.T.
2
4
6
Distance from junction [m]
Figure 4-3. C/V (full dots) and DLCP (open dots) of the 180 l, 720 l, 1800 l and
over-treated samples made at 200 K and 50 kHz. In the inset comparison of 50
kHz and 1 MHz for 1800 µl sample at the same temperature.
10
16
10
15
10
14
1800 l:
50 kHz
1 MHz
-
Charge Density [cm 3]
180 l
720 l
1800 l
O.T.
-3
Charge Density [cm ]
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Effects of the activation treatment
15
10
14
10
0
0
1
2
3
4
Distance from junction [m]
2
4
Distance from junction [m]
5
6
Figure 4-4. C/V (full dots) and DLCP (open dots) of the 180 l, 720 l, 1800 l and
over-treated samples made at 300 K and 50 kHz. In the inset comparison of 50
kHz and 1 MHz for 1800 µl sample at the same temperature.
Electrical characterization of high performance CdTe solar cells.
59
60
Admittance spectroscopy: defects
identification
The dependence of the doping concentration with frequency for the 1800
µl case is shown in the insets of Figure 4-3 and Figure 4-4. It can be seen
that at 200 K the concentration of deep and shallow defects does not
change as it does at 300 K as frequency changes. This suggests that the
defects that are active at 200 K are sufficiently fast for both 50 kHz and 1
MHz while at 300 K most of the active defects are slower [10] and freezeout occurs. Moreover the doping profile of the 1800 l at 1 MHz is similar
to the 720 l one at 50kHz, suggesting that the additional defects provided
by the stronger treatment are the ones that are switched off at higher
frequencies. This same behavior has been registered in the range of
temperatures between 280 K and 320 K.
4.5 Admittance spectroscopy: defects identification
AS measurements have been performed in a range of frequencies between
300 Hz and 1MHz and temperatures between 90 K and 320 K. Each
measurement was repeated applying different DC bias: 0V, -0.5V and +0.5V.
In Figure 4-5 the Arrhenius plots that identify the different defects present
in the various samples are shown. The linear corrections have been
performed by extracting the admittance spectroscopy data as reported in
[11] where the defect energy, Ea, and the capture cross sections, a ,are
calculated as explained in paragraph 2.6.
Extracted values are presented in Table 4-4. Note that the same letter in
defects names indicates the same samples family, whereas the same
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Effects of the activation treatment
number does not indicate the same kind of defect. In the low-treated
sample, 180 l, we registered three defects: a shallow one which is still not
identified, a deep one which is generally attributed to Te2-, probably
generated by the bromine-methanol etch [10][11]. This identification is
supported by the C/V and DLCP profiles in Figure 4-4, where the defects
contribution to the capacitance is placed near the back contact. Finally a
deep defect at 653 eV, could be attributed to the activation treatment as
reported by Beach et al [11].
-1
-1
3
4
5
1000/T[K ]
6
7
8
A1
5
1000/T[K ]
9
10
11
3
4
180l
4
5
2
9
10
11
5
D1
4
3
2
1
0
-1
-1
2
0
-2
-3
-2
A3
-3
5
C1
4
2
C4
2
C2
5
B1
C3
B3
1800 l
4
720l
3
B2
1
2
1
B4
0
0
-1
-2
0V
-0,5V
+0,5V
B5
-3
3
4
5
6
7
8
-1
1000/T[K ]
9
10
11
3
4
5
6
7
8
9
10
2
C5
ln[1/(T )]
ln[1/(T )]
3
-1
ln[1/(T )]
ln[1/(T )]
8
D2
A2
1
7
O.T.
3
2
6
-2
-3
11
-1
1000/T[K ]
Electrical characterization of high performance CdTe solar cells.
61
62
Admittance spectroscopy: defects
identification
Figure 4-5. Arrhenious plots of the different samples identifying the different
defects.
Table 4-4. Extracted defects by AS.
Treatment
Defect
180 l
A1
A2
A3
B1
B2
B3
B4
B5
C1
C2
C3
C4
C5
D1
D2
720 l
1800 l
Overtreated
Ea
[eV]
88
527
653
117
133
457
550
600
116
136
150
460
527
158
330
Error
[eV]
3
11
61
5
4
11
4
10
7
4
1
14
11
4
3
a
[cm-2]
1,35E-17
7,00E-12
6,00E-10
2,80E-16
1,10E-15
3,00E-13
3,00E-12
9,00E-11
4,00E-16
3,00E-15
1,70E-14
1,20E-12
1,00E-11
4,00E-14
1,00E-14
Identification
not reported
Te2- [11]
related with CdCl2 [11]
A-center(VCd-ClTe)[11,12]
VCd ,VTe [10]
not identified [11]
Te2related with CdCl2
A-center (VCd-ClTe)
VCd ,VTe
VCd ,VTe
not identified
Te2VCd ,VTe
TeCd [12]
There are similar defects for samples treated with 720 and with 1800 l of
CdCl2 saturated solution. At low temperatures, in the first case, we
observed two shallow defects connected with A-center Vcd2—Clte+ or the
cadmium vacancy VCd- [12]. At high temperatures, on the other hand, three
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Effects of the activation treatment
deep defects are observed. Again, two are identifiable with ionized Te and
activation treatment, a third one has been observed also by Beach et al.
[11] but not easily attributable.
The same happens with the device treated with 1800 l, with three shallow
defects again connected with A-center and two deep defects as above.
Finally the over-treated sample has similar defects than the last ones but
with an additional dominant defect at high temperatures, which is
attributed to substitutional TeCd [12] or substitutional CuCd [11]. However,
profiles in Figure 4-4 indicate a strong increase in the defects concentration
near the interface decreasing toward the back contact. Therefore supposing
D2 as the responsible for this increase, then it could be mostly attributed to
the TeCd. Moreover the same defect would then alter the recombination,
hence probably the reason for the lower Jsc.
4.6 Conclusions
Four different amount of saturated solution of CdCl2 in methanol have been
deposited on different CdTe solar cells.
The J/V characteristics show that devices have diode behavior at high
temperatures, when the carriers are collected. For the over-treated case,
the ideality factor and the band gap have very much different values from
the expected ones indicating the main transport mechanism as
recombination close to the interface.
The C/V and DLCP profiles show that by increasing the CdCl2 treatment, the
shallow defects concentration increases, but on the other hand also more
deep defects are observed, these last ones also move towards the
CdTe/CdS interface.
Admittance spectroscopy has revealed a general presence of A-center
defects in all the samples (a part of 180 µl), typically considered the dopant
shallow defect of CdTe. Deep defects are similar in 720 µl and 1800 µl, with
an increase near the interface for the latter. In the over-treated case a
different defect (probably due to TeCd) is responsible for the impressive
Electrical characterization of high performance CdTe solar cells.
63
64
References
increase of the deep defects concentration near the interface, probably
affecting the recombination mechanism, which could explain the lower Jsc
for these samples.
4.7 References
[1] B.E. McCandless, Proc. of Mat. Res. Symp., 668, 2001, p. H1.6.1.
[2] S. Pookpanratana, X. Liu , N. R. Paudel, L. Weinhardt, M. Bar, Y.
Zhang, A. Ranasinghe, F. Khan, M. Blum, W. Yang, A. D. Compaan,
C. Heske, Applied Physics Letters, 97, 17, 172109-1 – 17109-3.
[3] A. Romeo, M. Terheggen, D. Abou-Ras, D. L. Batzner, F.-J. Haug, M. Kalin,
D. Rudmann and A. N. Tiwari, Prog. Photovolt: Res. Appl. 12 (2004) 93111.
[4] First Solar Inc., Corporate Overview (2011),
http://www.firstsolar.com/Products-and-Services/ProductDocumentation.
[5] K. Durose, P. R. Edwards, D. P. Halliday, Journal of Crystal Growth 197
(1999) 733-742.
[6] U. Rau, A. Jasenek, H.-W. Schock, F. Engelhardt, and T. Meyer, Thin Solid
Films, 2000, 361-362, 298.
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Effects of the activation treatment
[7] V. Nadenau, U. Rau, A. Jasenek, and H.-W. Schock, J. Appl. Phys., 87(1),
2000, 584.
[8] U. Malm, J. Malmstrom, C. Platzer-Bjorkmann, L. Stolt, Thin Solid Films
480-481 (2005), 208-212.
[9] M. Burgelman, P. Nollet, S. Degrave, Applied Physics A, 69 (2009), 149153.
[10] A. S. Gilmore, V. Kaydanov, T. R. Ohno, D.Rose, S. D. Feldman, P. Erslev,
29th IEEE Photovoltaic Specialists Conference 2002 (2002), 604-607.
[11] J. Beach, F-H Seymour, V. I. Kaydanov and T. R. Ohno, NREL Report 52041097.
[12] A. Castaldini, A. Cavallini, B. Fraboni, P. Fernandez, J. Piqueras, Journal
of Applied Physics, Volume 83, number 4, p 2121-2126.
Electrical characterization of high performance CdTe solar cells.
65
66
References
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Electrical characterization of high performance CdTe solar cells.
67
Chapter 5
Thin CdTe: Physical and electrical
properties.
5.1 Introduction
In the first chapter I have mentioned the main drawbacks of CdTe
technology, among them Te scarcity and Cd toxicity. The latter is a matter
of perception, as there are many scientific papers attesting the absolutely
low environmental impact of this technology [1]. On the other hand the
only way to face Te scarcity is to reduce the absorber thickness to 1.5-1.0
microns [1].
As a matter of fact CdTe solar cells are generally produced with
thicknesses above four microns [2], in order to have a complete light
absorption and no pin-holes. Reducing CdTe thickness would result in less
performing devices [3], usually attributed to a sensible reduction of light
absorption and non homogeneous films, however it is still not completely
understood the physical change which affects the performances.
In this chapter I analyze the physical and electrical properties of CdTe
devices with different absorber thicknesses.
69
70
Current-Voltage (J/V)
5.2 Experimental Details
The base process described in Chapter 1 has been applied to produce
solar cells with thin CdTe layer. All the layers on which the CdTe is
deposited have been prepared according to the standard process, but all
the process steps subsequent to the CdTe deposition have been optimized
depending on the CdTe thickness. In particular: the amount of saturated
solution of CdCl2 , the amount of copper in the back contact and the
annealing temperatures are in general reduced as CdTe thickness reduces.
Within this study many samples with CdTe thickness layers ranging
between 0.7 µm and 7 µm have been prepared and analyzed. In the next
paragraphs I will present only the most interesting results, in particular
comparing samples with 0.7 µm, 1.2 µm and 6 µm.
In addition to the electrical characterization (i.e. J/V, C/V, DLCP and AS)
the crystallization of the CdTe layers, has been analyzed by Atomic Force
Microscopy (AFM) with a NT-MDT Solver Pro in semi-contact mode and by
X-ray diffraction analysis (XRD) by a Thermo ARL X´TRA powder
diffractometer, operating in Bragg-Brentano geometry, equipped with a Cuanode X-ray source (Kα, λ =1.5418 Å) and using a Peltier Si(Li) cooled solid
state detector.
5.3 Current-Voltage (J/V)
In Figure 5-1, J/V characteristics of solar cells with different CdTe
thicknesses are shown.
Efficiencies drop from 13.5 % of the standard thick absorber to 7.4 % of
the ultrathin (0.7 m) absorber device. Anyway efficiencies above 10 % are
typically obtained for CdTe layers above 1.5 m.
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Thin CdTe: Physical and electrical properties.
Thickness Efficiency Voc
[um]
[%]
[mV]
2
Current Density [mA/cm ]
J/Vs also show the progressive reduction of all the parameters as thickness
decreases: Voc, FF, and Jsc decrease of 15%, 17% and 15% respectively,
indicating an absence of a dominant effect on the performance reduction.
This issue is in contrast with the reduced light absorption hypothesis, which
should affect mainly the Jsc.
10
0
-10
0,7
1,0
1,8
6,0
7,4
9,0
11,0
13,5
683
778
782
838
FF
[%]
57,0
64,0
69,0
70,0
Jsc
[mA/cm2]
19,0
18,1
20,5
23,0
0,7 m
1,0 m
1,8 m
6,0 m
-20
0,0
0,5
Voltage [V]
1,0
Figure 5-1. J/V characteristics of different devices with CdTe thickness ranging
between 0,7 and 6 µm.
These cells have been made as described in Chapter 1 optimizing the
amount of copper at the back contact according to the CdTe thickness, in
order to reduce the influence of copper diffusion on the performance. The
lack of Cu emphasizes the roll-over reduction as the absorber thickness
decreases (see Figure 5-2). This was also observed by Hädrich et al. [4] who
explained this effect by the band banding for thin absorbers, reducing the
back contact barrier (Figure 5-3).
Electrical characterization of high performance CdTe solar cells.
71
72
2
Current Density [mA/cm ]
Current-Voltage (J/V)
120
0,7 m
1,0 m
80
40
0
-0,4
0,0
0,4
0,8
Voltage [V]
Figure 5-2. Roll-over reduction in thin CdTe devices
Figure 5-3. Band diagram for thick (top) and thin (bottom) CdTe, showing the back
contact barrier (ϕb) reduction.
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Thin CdTe: Physical and electrical properties.
5.4 Atomic Force Microscopy (AFM)
By AFM we observed morphology and grain size of each differently thick
layer. As thickness increases, grains size increases correspondingly. From
AFM analysis the average size and mean quadratic deviation of asdeposited and treated CdTe layers were extracted with Image Analysis 3.5
(from NT-MDT).
There is a linear direct correspondence between grain size and thickness
for as-deposited layers (not shown here), with a larger difference in size
between small and big grains for thicker samples.
After activation treatment a general increase of grain size and more
compact morphology is observed for all the samples with different
thickness. However, for thin CdTe, an overall increase in the grain size is
observed, whereas for thick CdTe this enlargement is only for small grains
(see Figure 5-4).
5.5 X-Ray Diffraction (XRD)
Crystallization of these layers has been studied analyzing the XRD patterns
in both as-deposited and treated cases.
In the as-deposited case the layers show a very similar crystallization
irrespective of the absorber thickness. In thick CdTe some little peaks on
other orientations are present, suggesting a slightly more randomized
structure.
After the activation treatment the grain orientation, for thin CdTe, is
randomized. However a prominent (111) orientation peak is still present,
which gradually reduces as thickness increases. A highly randomized CdTe,
also reported in literature [2], is actually seen for thicker CdTe.
Electrical characterization of high performance CdTe solar cells.
73
74
X-Ray Diffraction (XRD)
Figure 5-4. Grains morphology of 1 m (top), 1.8 m (center) and 6 m (bottom)
thick CdTe after CdCl2 treatment.
Error! Use the Home tab to apply Titolo 1 to the text that you
want to appear here.
Thin CdTe: Physical and electrical properties.
Intensity (arb. units)
* CdS peaks
+ CdSxTe1-x peaks
0.7 m
6 m
Intensity (arb. units)
Most important, for thin CdTe, CdS peaks are also observed together with
a peak attributed to the intermixed layer of CdS and CdTe. The observed
(Cd5S4Te)0.8 peak suggests that the usual intermixed layer, which is also
present in the standard CdTe devices, is in this case a consistent part of the
solar cell.
(111)
(311)
(422) (511)
(002)*
25
50
75
(311)
(422)
(111)
(331)
(400)
(220)
* +
*
*
(002)
(102)
(103)
25
50
2degrees
(511)
75
Figure 5-5. XRD spectra of CdCl2 treated (top) and as-deposited CdTe (bottom), 6
m (red) and 0.7 m (black).
Furthermore the lattice parameter has been extracted from the positions
of the XRD peaks with Nelson-Taylor plot calculation [5-7]. From this
analysis results a smaller lattice parameter for thin CdTe (6.451 Å)
compared to the standard 6 m (6.487 Å) [7], this effect is generally
attributed to the intermixing layer, supporting the hypothesis of CdTe
completely mixed with CdS along the device.
Electrical characterization of high performance CdTe solar cells.
75
76
Space Charge Profiling
5.6 Space Charge Profiling
The same cells were than analyzed at different temperatures (from 90 K
to 320 K) by means of DLCP (full symbols) and C/V (open symbols) both
shown in Figure 5-6 and Figure 5-7.
-3
Charge Density [cm ]
Samples with 6 m of CdTe (gray symbols) show an U-shape shallow
defects profile exceeding 1015 in the back contact region, 1013 into the bulk
and increasing gradually approaching the junction. On the other hand the
0.7 m devices (black squares) show the same U-shape but drastically
reduced: the space charge density changes from 1016 in the back contact to
1015 and slightly increases close to the junction, suggesting that pure bulk
CdTe region is disappeared.
10
16
10
15
10
14
0.7 m @ 50 kHz and 300 K
6.0 m @ 50 kHz and 300 K
6.0 m @ 1 MHz and 147 K
0
1
2
3
4
5
6
Distance from the junction [m]
Figure 5-6. Comparison between the 0.7 m (black symbols) and 6 m (gray
symbols) samples.
Error! Use the Home tab to apply Titolo 1 to the text that you
want to appear here.
Thin CdTe: Physical and electrical properties.
1 MHz
50 kHz
10
15
10
15
10
14
-3
Charge Density [cm ]
Charge Density [cm-3]
It has been observed also that different absorber thickness results in
different temperature dependence of the C/V and DLCP profiles. In the 6
m sample (Figure 5-7) the shallow defects density increases progressively
with temperature whereas the deep defects contribution (distance
between full and open dots) increases abruptly between 280 K (gray circles)
and 300 K (dark-gray triangles). For the 0.7 m was not possible to register
any difference in shallow and deep defects concentrations at temperatures
below 300 K because the depletion region extends to the back contact for
all possible combinations of DC bias magnitude and AC bias frequency. For
these samples only above room temperature and at relatively low
frequencies it was possible to measure reliable profiles as shown in (Figure
5-7).
1
2
3
4
5
Distance from the junction [m]
10
14
147 K
280 K
300 K
2
3
4
5
6
Distance from the junction [m]
Figure 5-7. Typical 6 µm C/V (open symbols) and DLCP (full symbols) profiles
measured at different temperatures and at constant frequency of 1 MHz. In the
inset, for the same sample, profiles measured at different frequencies and at
constant temperature of 300 K are compared.
Electrical characterization of high performance CdTe solar cells.
77
78
Space charge spectroscopy
Furthermore in the inset of Figure 5-7 the profiles for a thick sample are
compared at different frequencies. It brings out that the contribution of
deep defects (distance between full and open dots) doesn’t depend on
frequency, which indicates fast deep defects. On the other hand shallow
defects profiles are different: at 1 MHz (black full squares) it is constant,
whereas at 50 kHz (full gray circles) it increases toward the junction. This
difference can be explained by slow shallow defects in the proximity of the
junction.
5.7 Space charge spectroscopy
Admittance Spectroscopy has been performed in a range of temperature
between 90 K and 320 K sweeping the frequency from 300 Hz to 1 MHz and
applying three different DC biases, respectively -0.5 V, 0 V and +0.5 V.
As expected, increasing the temperature (or reducing frequency) shrinks
the depletion width (W) as defects are activated, moreover the DC bias
determines the band banding in the main junction resulting in different
depletion width. Figure 5-8 shows the evolution of W depending on
temperature and frequency for 0 V constant DC bias.
Frequency
5
T [K]
4
100
200
300
1,0
3
Frequency
0,9
0,8
2
0,7
Depetion Width [m]
Depletion Width [m]
6
200
T [K]
300
Error! Use the Home tab to apply Titolo 1 to the text that you
want to appear here.
Thin CdTe: Physical and electrical properties.
Figure 5-8. Depletion width extension over temperature and frequency for 6 µm
and 1 µm (inset) samples (DC bias 0 V).
Table 5-1. Depletion region width over absorber thickness for different DC bias at
300 K and 50 kHz.
Thickness
[m]
6
0.7
DC Bias
[V]
+0.5
0
-0.5
+0.5
0
-0.5
Depletion/Thickness
[%]
12%
28%
37%
47%
79%
82%
As far as the ratio between the depletion region width and the absorber
thickness increases the neutral region decreases. Moreover the back diode
depletion region is also present and it could significantly increase these
ratios reducing even more the neutral region extension.
If in the thick samples the SRH recombination in the neutral region should
be the dominant conduction process [8], for thin samples recombination in
the depletion region is probably the dominant conduction process, even at
middle forward bias. This probably changes the dynamic of the transport in
the thin CdTe devices, resulting in different quasi-Fermi-levels splitting,
then in lower Voc.
Furthermore calculating the values of the depletion region width for the
different CdTe thickness at +0.5 V, brings out 720 nm depletion width for
the thick samples and only 329 nm for the thin one. According to the C/V
and DLCP profiles this suggests a possible difference in the intermixed layer
extension and composition. For this reason in order to identify the defects
Electrical characterization of high performance CdTe solar cells.
79
80
Space charge spectroscopy
in the CdTe, the defect activation energy (Ea), and the relative capture cross
sections (a) have been extracted by linear correction as shown in Figure
5-10.
Figure 5-9. Different quasi-Fermi-levels splitting in Thin CdTe
5
A2
A1
C3
4
A3
2
ln[1/(T )]
3
2
B1
D1
1
0
-1
-2
C1
B2
C2
B3
D2
6 m
1 m
-3
3
4
5
6
7
-1
1000/T [K ]
8
9
10
Error! Use the Home tab to apply Titolo 1 to the text that you
want to appear here.
Thin CdTe: Physical and electrical properties.
Figure 5-10. Defect identification by linear correction of AS Arrhenius plot for 6
µm (full dots) and 1 µm (open dots).
Extracted values are presented in Table 5-2. According with the MeyerNelded rule [9], defects lying on the same line have been indicated by the
same caption letter. For 6 m case we have observed three shallow defects
A1, A2, A3 probably connected with A-center VCd, VTe and (VCd-ClTe) [10]. At
high temperatures defects B1, B2 and B3 were observed: B2 and B3
probably related to ionized Te while B1 is not easily attributable, but it has
been observed also by Beach et al. [11].
In the ultra thin absorber (0.7 m), four shallow defects (C1-C4) and two
deep defects (D1, D2) have been observed. The latter are very similar to B2
and B3 previously mentioned, and C1-C4 are probably connected to
impurities as Na [12]. The formation of these shallow defects could be
explained by the impurities diffusion from the substrate, which is a
common soda-lime glass. ZnO film should prevent the contamination from
the glass, but it is possible that a small concentration of Na reaches the
CdTe layer. Moreover, it should be possible that in the thick samples these
defects are not registered because even at low temperature their
concentration is smaller than the typical CdTe shallow defects (A-center).
The lack of A-center is a further confirmation that in thin samples the pure
bulk CdTe is almost absent.
5.8 Conclusions
Solar cells with different absorber layer thickness were prepared and
compared. Devices with very thin absorber layer of 0.7 m CdTe show an
efficiency of more than 7 %. However 10 % efficiencies are obtained when
the thickness is exceeding 1.5 m. The low efficiency of the 0.7 m CdTe
devices could also be connected with the large CdSxTe1-x intermixed part in
the absorber which gives low Voc, as demonstrated by the low lattice
parameter and by the detection of a (Cd5S4Te)0.8 XRD peak.
Electrical characterization of high performance CdTe solar cells.
81
82
Conclusions
J/V analysis reveals a reduction of roll-over as CdTe thickness reduces, this
effect has been reported and explained by other authors [4] as an influence
of the main junction band bending on the back contact barrier, due to the
small absorber thickness.
Table 5-2. Extracted defects of 6 m and 0.7 m CdTe absorbers.
Ea
[meV]
Error a
[meV] [cm2]
A1
116
7. 5
4.1*10-16
A-center [10]
A2
135
4
2.79*10-15
Id.
A3
150
1
1.67*10-14
Id.
B1
460
15
1.22*10-12
Not identified [11]
B2
527
12
7.37*10-12
Ionized Te
B3
543
21
3.54*10-11
Id.
C1
26.2
0.6
1.23*10-20
Impurities (Na) [12]
C2
36.9
1.3
3.58*10-20
Id.
C3
47.52
0.07
1.21*10-19
Id.
C4
75.15
2.4
6.55*10-19
Id.
D1
547.15
8.2
3.08*10-12
Ionized Te
D2
583.2
14.3
1.55*10-11
Id.
Thickness Defect
6 µm
0.7 µm
Identification
A linear increase of CdTe grains size with increasing of CdTe thickness was
observed. As-deposited absorber layers with different thicknesses do not
show any significant difference in calculated lattice parameters and band
gap energies, moreover they all show a strong (111) preferential
orientation in the XRD patterns.
After CdCl2 treatment the CdTe grains size increases in all cases but
substantial difference can be observed. However the XRD patterns of thin
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Thin CdTe: Physical and electrical properties.
CdTe show presence of sulfur and intermixed CdSxTe1-x layer, which takes a
relevant part of the absorber.
C/V and DLCP analysis show evident difference in the charge density
profiles. In 6 m samples the profiles indicate a strong reduction of charge
concentration in the bulk CdTe between the back contact region and the
intermixed layer where it increases dramatically. For 0.7 m this reduction
is not visible indicating a possible absence of pure bulk CdTe.
AS measurements have been used to estimate the ratio between
depletion region width and absorber thickness. Considerable differences
between 6 m and 0.7 m are shown, suggesting a different transport
mechanism: recombination in neutral region in the first case and
recombination in depletion region in the latter, probably resulting in
reduction of FF and Voc.
Furthermore defects energies and capture cross sections have been
extracted. In the first case defects connected to A-center were identified at
low temperature usually suspected to represent doping defects of CdTe. In
the second case this defects were not registered whereas Na impurities are
suspected to play a relevant role in recombination process.
In conclusion preparation of thin CdTe device implies not only issues due
to the optimization of the fabrication process such as lower light absorption
and possible pinholes but especially structural properties like a different
CdTe morphology and grain orientation, different back contact behavior,
different transport mechanisms.
Electrical characterization of high performance CdTe solar cells.
83
84
References
5.9 References
[1] V. Fthenakis, Renewable and Sustainable Energy Reviews. 13 (2009)
2746–2750.
[2] A. Romeo, M. Terheggen, D. Abou-Ras, D. L. Batzner, F.-J. Haug, M. Kalin,
D. Rudmann and A. N. Tiwari, Prog. Photovolt: Res. Appl. 12 (2004) 93111.
[3] A. Bosio, N. Romeo, S. Mazzamuto, V. Canevari, Progress in Crystal
Growth and Characterization of Materials. 52 (2006) 247-279.
[4] M. Hadrich, C. Heisler, U. Reislohner, C. Kraft, H. Metzner, Thin Solid
Films 519 (2011) 7156-7159.
[5] J. B. Nelson and D. P. Riley, Proc. Phys. Soc. 57 (The Physical Society,
London, 1945) p. 160.
[6] A. Taylor and H. Sinclair, Proc. Phys. Soc. 57 (The Physical Society,
London, 1945) p. 126.
[7] H. R. Moutinho, M. M. Al-Jassim, F. A. Abufoltuh, D. H. Levi, P. C. Dippo,
R. G. Dhere, and L. L. Kazmerski, 26th IEEE Photovoltaic Specialists
Conference, Anaheim, CA, September 29 October 1, 30 (1997) 3.
[8] R. Gottschalg, B. Elsworth, D. G. Infield, M. J. Kearney, (1999)
Investigation of the Back Contact of CDTE Solar Cells. In ISES Solar World
Congress, Jerusalem, pp.124-128, ISBN: 0 08 0438954.
Error! Use the Home tab to apply Titolo 1 to the text that you
want to appear here.
Thin CdTe: Physical and electrical properties.
[9]J. Heath, P. Zabierowski, Capacitance spectroscopy of thin film solar cells,
in Advanced Characterization Techniques for Thin-Film Solar Cells (Eds.
U. Rau, T. Kirchartz and D. Abou-Ras), WILEY-VCH, (2011).
[10] A. Castaldini, A. Cavallini, B. Fraboni, P. Fernandez, J. Piqueras, Journal
of Applied Physics, Volume 83, number 4, p 2121-2126.
[11] J. Beach, F-H Seymour, V.I. Kaydanov and T.R. Ohno, NREL Report 52041097.
[12] E. Molva, J. L. Pautra, K. Saminadayar, G. Milchberg, N. Magnea, Phys.
Rev. B, Vol. 30 (1984), p. 3344.
Electrical characterization of high performance CdTe solar cells.
85
86
References
Chapter 6
Ageing of CdTe devices by copper
diffusion
6.1 Introduction
Despite the industrial feasibility and the promising perspectives, CdTe
devices stayed at the laboratory scale for a long time and it took more than
two decades to bring CdTe modules to the market. One of the main reasons
for this is the difficulty in engineering a suitable back contact for CdTe due
to its high electron affinity, which requires a material with a very high work
function (see paragraph 1.3.5).
Nowadays modules based on CdTe technology are produced with back
contacts made by a wide range of materials (e.g. Sb2Te3, As2Te3,…) [1]
ensuring high stability, but usually increasing the series resistance and
consequently the interconnection losses. Usually the best performances are
achieved by addition of copper in the back contact that reduces roll-over
effect and enhances the absorber electrical properties. However it is well
known that copper diffuses through the grain boundaries until it reaches
the CdS/CdTe junction progressively shunting the cell with a consequent
87
88
Experimental
efficiency reduction mainly connected with fill factor (FF) and open circuit
voltage (Voc).
According to the certification protocol IEC 61646 to estimate the
performance degradation, modules are usually tested applying high
temperature (85 °C) and/or irradiation, but no external load is expected.
Laboratory tests often introduce biases to better understand the
degradation process, which is usually connected with Cu migration from the
back contact [2-4].
In our lab several CdTe solar cells with Cu/Au back contact have been
prepared with the same process and, then differently stressed with a
specific chamber where temperature, illumination and bias can be
controlled. A set of cells was stored in dark conditions at room temperature
(RT) while another set was stored in the chamber in light condition (1 sun)
at fixed temperature (80 °C) with no bias and, finally, the third set was
stored in the same chamber but shunting front and back contact.
These sets of cells have been periodically analyzed by J/V, C-V, DLCP and
AS.
6.2 Experimental
Solar cells studied in this work were produced as described in Chapter 1,
and treated by CdCl2 saturated solution. Finally, to form the back contact, 2
nm of copper and 50 nm of gold were deposited by vacuum evaporation
without heating the substrate but with a subsequent annealing in air at 190
°C for 20'. Such small amount of copper is the best trade-off between high
efficiency and stability (copper diffusion). Bigger amount of copper would
reduce the roll-over effect resulting in higher fill factor and higher
efficiency, but providing a higher copper migration from the back contact.
Chapter 6
Ageing of CdTe devices by Cu diffusion
Three different kinds of ageing were performed at different conditions:
 Dark, room temperature and No Bias (DNB),
 Light, high Temperature and No Bias (LTNB),
 Light, high Temperature and Bias (LTB).
In the first case samples were simply stored in a drawer, in the second they
were stored in a metal chamber with halogen lights and equipped with fans
and a temperature controller made to maintain the temperature constant
at 80 °C, and light exposure of 1000 W/m2. In the third case cells were
stored in the same chamber, in same conditions but with front and back
contact shunted, current was controlled by an amperometer.
The 1000 W/m2 irradiation in the ageing chamber has been performed by
halogen lamps calibrated by a silicon solar cell. Since the emission spectrum
of these lamps differs from the solar one, in particular in the ratio between
infrared and visible wavelength, it is possible that using silicon wavelength
as a reference could result in inaccuracy in light intensity exposure.
However the goal of this work is to compare the effects of similar kinds of
stress on devices made by the same production process, not to reproduce
the modules working conditions or to extrapolate a multiplication time
factor.
6.3 Current-Voltage (J/V).
J/V measurements at different ageing time have been performed on
devices stressed as described in previous paragraph. Unfortunately it was
not possible to measure all the samples at the same time, for this reason
time intervals differs, however in Figure 6-1 the stresses effect on the
devices and their differences are clearly shown.
In Figure 6-1 (picture below, right side) the typical efficiency evolution due
to the applied stress is seen. In all cases stress starts after the second point:
pre-stress measurements were performed to check if the cell was stable,
Electrical characterization of high performance CdTe solar cells.
89
90
Current-Voltage (J/V).
10,0
2
0,0
-10,0
0h
312 h
480 h
576 h
745 h
1010 h
Current Density [mA/cm ]
10,0
0,0
-10,0
0h
408 h
576 h
673 h
841 h
1106 h
10,0
0,0
-10,0
-20,0
LTNB
-20,0
0,0
2
DNB
Voltage [V]
0h
144 h
192 h
264 h
312 h
336 h
0,5
1,0
LTB
0,0
Voltage [V]
1,0
0,8
0,6
DNB
LTNB
LTB
0,4
-20,0
0,0
0,5
1,0

Current Density [mA/cm ]
ensuring that the following degradation was connected only to the applied
stress.
Voltage [V]
0,5
1,0
0
200
400
600
Time [h]
800
1000
Figure 6-1. Down right. Normalized efficiency evolution for the different kinds of
stress. η0 represents the efficiency at t=0 h (hour). Others. Typical J/Vs of DNB,
LTNB and LTB at different ageing time.
It is possible to note that for the samples stored in DNB conditions the
degradation trend continues after the second point with no changes. It is
also interesting to note that after more or less 600 h (hour) there is a peak
in efficiency. This peak was registered on 9 cells over 10 that have been
measured and it seems to be driven by similar peak in FF, since Jsc and Voc
do not change significantly. Furthermore DNB J/V characteristics (Figure 6-1
top left) present a progressive reduction in FF and in roll-over, but no
remarkable changes in Voc and Jsc. A possible explanation of this phenomen
Chapter 6
Ageing of CdTe devices by Cu diffusion
could be a migration of copper from back contact increasing the back diode
barrier height and, at the same time, shunting the cell. After around 1000 h
the efficiency decreases from the initial 13.5 % to 11.3 %, with a
performance loss of 16 %.
Cells aged in LTNB conditions show a dramatic efficiency decrease after
first stress application and, further, kind of stabilization of the degradation
trend, which brings to a total loss of 45 % efficiency at the end of the ageing
(1100 h).
In the last case (LTB), the shunt between front and back contact allowed a
continuous current flow close to Jsc value. This stress results to affect much
more the device performance achieving the whole LTNB degradation after
only 360 h instead of 1100 h.
In the bottom left of Figure 6-1 the J/Vs of typical LTB sample are shown.
Pre-stress curves (empty squares and circles) indicate very slow
degradation with slight performance loss mainly due to Voc reduction. After
the stress, degradation is dominated by FF that decreases of -37 % (from
almost 71 % to 44 %), whereas Voc decreases just of -6 % (from 824 to 775
mV) and Jsc increases of +3,5 %. Despite some fluctuations in parameters,
performance remains more or less stable after the first stress, for this
reason, the ageing of these samples was stopped after only 360 h.
6.4 Space Charge Profiling
In order to investigate the suspected migration of Cu from the back
contact along the devices DLCP and C/V profiles have been collected in a
range of temperature between 100 K and 320 K. It is worth to note that
higher temperatures have been avoided to not affect the Cu diffusion from
back contact during the measurements.
Electrical characterization of high performance CdTe solar cells.
91
92
Space Charge Profiling
-3
Charge Density [cm ]
-3
Charge Density [cm ]
All kinds of measurements have been repeated at different cells lifetimes,
along the ageing process, in order to follow the devices performance
degradation.
Measurements have been performed at different frequencies, in particular
10 kHz, 50 kHz, 100 kHz and 1 MHz, to analyze the defects response.
For clarity reasons only the most interesting results are presented.
10
16
10
15
10
14
10
14
Reference 1 MHz
LTNB 840 h 1MHz
0
0
2
4
6
Distance from the junction [m]
Reference 10kHz
LTNB 840 h 10kHz
2
4
6
Distance from the junction [m]
Figure 6-2. Comparisons between DLCP (full symbols) and C-V (open symbols)
profiles of LTNB sample at 300 K and 10 kHz. In the inset a similar comparison
repeated at 1 MHz.
Figure 6-2 shows representative profiles obtained at 300 K and 10 kHz (1
MHz in the inset) of a sample aged in LTNB condition. Black symbols profiles
represent the reference measured in pre-stress time, gray symbols profiles
show the effect of the stress. After 840 h in LTNB conditions both defects
concentrations are sensibly lower than the reference. For example at 2 m,
shallow defect concentration was around 2*1014 before the stress and
1*1014 after the stress. Deep defects contribution decreases from 1,3*1014
to 5*1013. In the proximity of the junction (between 0 and 1 m) in both
Chapter 6
Ageing of CdTe devices by Cu diffusion
cases deep defects are not affecting the charge, while shallow defects
concentrations dramatically increase achieving similar values.
10
16
10
15
10
14
0
-3
Charge Density [cm ]
-3
Charge Density [cm ]
In the inset of Figure 6-2, 1 MHz profiles are shown. If we compare the
ageing profiles with the reference is possible to see that deep defects
contribution does not change after ageing (e.g. at 3 m it is constant
around 7*1013), while shallow defects concentration decreases from 1*1014
to 5*1013.
In general we can conclude that LTNB ageing reduces both shallow and
deep defects densities away from the junction. However, shallow defects
concentration involved in ageing degradation changes with frequency,
yielding defects with different response time. On the other hand deep
defects contribution due to degradation is visible only at low frequency,
indicating that only slow deep defects are involved by this kind of stress.
10
14
Reference 1 MHz
LTB 360 h 1 MHz
0
2
4
Distance from the junction [m]
Reference 10kHz
LTB 360 h 10kHz
2
4
Distance from the junction [m]
6
Figure 6-3. Comparisons between DLCP (full symbols) and C-V (open symbols)
profiles of LTB sample at 300 K and 10 kHz. In the inset a similar comparison
repeated at 1 MHz.
Electrical characterization of high performance CdTe solar cells.
93
94
Space Charge Profiling
Figure 6-3 shows profiles measured at 300 K and 10 kHz (1 MHz in the
inset) of a representative sample before (reference, black symbols) and
after (gray symbols) ageing in LTB condition for 360 h.
The reference profile of this sample is very similar to the one shown in
Figure 6-2, so we are sure that the differences reported are related only
with the different stresses.
Profiles shown in Figure 6-3 and in Figure 6-2, in the junction region are
very similar. Moreover for LTB case, away from the junction, the reduction
of shallow defects density has the same magnitude than in LTNB case (e.g
at 2,5 µm it is 1,5*1014 for the reference profile and around 6*1013 after
360 h). On the other hand, with respect to deep defects, it is possible to see
a sensible difference between LTNB and LTB: if in the first case deep defects
contribution was reduced by the stress, in the latter it increases
dramatically (from 1*1014 to 2*1014).
In the inset of Figure 6-3 the same comparison is presented at 1 MHz,
which brings out the same behavior than at lower frequencies: shallow
defects density decreases (e.g. at 3,5 m from 6*1013 to 2*1013) and deep
defects concentrations increases (e.g. at 3,5 m from 5*1013 to 1,4*1014).
A possible conclusion is that most of deep defects generated by this stress
are fast.
Another consideration is about the influence of back-contact capacitance
on the measurement: if it increases enough to be comparable with the
main junction capacitance they can be considered as two capacitors in
series, this reduces the equivalent circuit capacitance that is no longer
connected with defects concentration in the device. LTB DLCP profiles at 1
MHz (gray symbols in Figure 6-3 inset) extend from 3 m up to 5 m while
in LTNB extend from 2,5 m to 6 m (gray symbols in Figure 6-2 inset). This
means that the LTB back contact capacitance is more pronounced with
respect to the LTNB case. Furthermore this difference is appreciable more
at 1 MHz than at 10 kHz.
Chapter 6
Ageing of CdTe devices by Cu diffusion
From the C/V curves (not shown here) the LTB back contact at 1 MHz seems
to behave in anomalous way and this is the most probable reason for such
short profiles.
-3
Charge Density [cm ]
-3
Charge Density [cm ]
A similar comparison was done for samples aged in DNB conditions for
480 h. It brought out that reference and stressed sample profiles perfectly
coincide either at 10 kHz or 1 MHz (see Figure 6-4). So variation of shallow
and deep defects densities were not registered. Anyway DNB ageing
produces some degradation of performance that can be also related with
some variation of charge profiles, but they are probably too small to be
appreciated by these techniques.
10
16
10
15
10
14
10
14
Reference 1 MHz
DNB 480 h 1MHz
0
0
2
4
Distance from the junction [m]
Reference 10kHz
DNB 480 h 10kHz
2
4
Distance from the junction [m]
6
Figure 6-4. Comparisons between DLCP (full symbols) and C-V (open symbols)
profiles of DNB sample at 300 K and 10 kHz. In the inset a similar comparison
repeated at 1 MHz.
In Figure 6-5 the evolution of shallow and deep defects profiles in
temperature range between 180 K and 300 K for LTB sample is shown. From
180 K to 220 K both shallow and deep defects densities increase sensibly.
Electrical characterization of high performance CdTe solar cells.
95
96
Space Charge Spectroscopy
180 K
220 K
250 K
280 K
300 K
-3
Charge Density [cm ]
From 220 K up to 300 K shallow defects concentration increases gradually,
on the other hand deep defects contribution increases dramatically (e.g.
from 250 K to 280 K deep defects change from 6*10 13 to 2,2*1014).
Moreover close to the back contact, the profile at 220 K (gray circles) are
similar to the ones reported by [2]. This information together with AS
results can help to identify the deep defects responsible of the performance
degradation.
10
15
10
14
10
13
0
2
4
6
Distance from the junction [m]
Figure 6-5. Comparisons between DLCP (full symbols) and C-V (open symbols)
profiles of LTB sample at 10 kHz and in a range of temperature between 180 K to
300 K.
6.5 Space Charge Spectroscopy
Capacitance was measured sweeping the frequency between 300 Hz and 1
MHz in a range of temperatures between 100 K to 320 K. Each
measurement has been repeated with applied direct current bias of 0 V, 0,5 V and +0,5 V.
Chapter 6
Ageing of CdTe devices by Cu diffusion
In high performance cells it is usually possible to identify many defects
active at different temperatures. Unfortunately when the contact degrades
high frequency measurements become noisy preventing a correct
extraction of the defect parameters especially at low temperature. Table
6-1 summarizes the parameters that have been extracted.
For reference we address the defects extracted before applying any
stress. We have reported similar values in previous works [5] and in Chapter
4 and 5 (see Table 5-2 and Table 4-4) .
The A1 is typically connected VCd VTe and (VCd-ClTe) [6][7], A2 not easily
attributable and A3 probably connected with Te- or Te2-[6].
For DNB samples the AS peaks yields exactly the same defects of the
Reference sample.
For the LTNB case, are observed shallow defects never reported before in
CdTe solar cells (B1 and B2), and deep defects B3 and B4, the first probably
not connected with Cu and the second probably connected with CdCl2 [6].
Table 6-1. Activation energy and cross capture section
Sample
Ref.
LTNB
LTB
Ea
[meV]
150
460
527
74
96
500
636
379
421
Error
[meV]
1
14
11
3
3
17
2
2
8
σa
[cm-2]
1,70 x10-14
1,20 x10-12
1,00 x10-11
3,57x10-18
2,64x10-17
3,75x10-12
8,51x10-10
9,83x10-15
3,38x10-13
Defect
Identification
A1
A2
A3
B1
B2
B3
B4
C1
C2
A-center [6][7]
Not identified
Ionized Te [6]
Never reported
Id.
Not identified
Connect with CdCl2[6]
CuCd- [6][7]
Similar to A2
In the LTB samples extraction of shallow defects at low temperature was
too uncertain, but deep defects were clearly extracted at temperatures
Electrical characterization of high performance CdTe solar cells.
97
98
Conclusions
close to 300 K. With respect to C2, also observed by Beach et al. [6], we
avoid any identification because there is not evident match with reported
defects in literature, even though it seems to be quite similar to A2. On the
other hand C1 has been reported by [6][7] and identified as CuCd-, so we can
suppose that the increased deep defects concentration revealed by C/V and
DLCP can be connected with the appearance of this peak in the AS which
was not visible in the other types of samples.
6.6 Conclusions
Three sets of cells have been prepared by the same process with the same
characteristics. The cells were aged applying different stresses (Dark No
Bias, Light high Temperature No Bias, Light high Temperature and Bias) in
order to study copper diffusion from the back contact through the device.
The J/V characteristics show very different effects of the three ageing
stress on the devices performance. The DNB yields a degradation of about
16 % in 1000 h. From 600 to 1000 h the efficiency does not decrease too
much, so in this case it is possible to conclude that after the first loss the
devices stabilize. In case of LTNB the stress application causes a quick
reduction of performances followed by a slower degradation that results in
an overall loss of 45 % in performance in 1100 h. In the last case (LTB) a
similar behavior was registered, the stress application yields an even more
dramatic drop of the efficiencies followed by a similar stabilization of the
degradation trend, resulting in a final efficiency reduction of 45 % in only
360 h.
J/V characteristics analysis brings out that all degradations are mainly
driven by FF losses.
DLCP and C/V profiles have shown evident differences for the three cases.
After 480 h DNB shows identical profiles, whereas LTNB performs a sensible
reduction in shallow and deep defects concentration, probably explained by
Chapter 6
Ageing of CdTe devices by Cu diffusion
compensation. On the other hand in the LTB case the reduction of shallow
defects is confirmed, but deep defects contribution sensibly increases.
In case of LTNB typical CdTe deep defects were registered by AS. Shallow
defects, not present in the reference sample, were registered but not
identified, because, to our knowledge, never reported in literature.
In LTB samples, the shallow defects extraction was not possible probably
due to the strong performance degradation. However two kind of deep
defects were registered. One of these (C2) is very similar to a defect present
in the reference (A2). The other defect (C1) was identified as CuCd- [6][7].
Since it was revealed only for the LTB case, it can be supposed as the
responsible for the increased deep defects concentration carried out by
C/V.
Taking into account that LTB provides the strongest degradation, opposite
of what observed by [2], we conclude that the models proposed are not
suitable for our samples. A possible explanation is that copper, under DNB
conditions, is moved only by the concentration gradient, diffusing slowly
and with no appreciable changes in defects concentration and position.
Under light and temperature stimulation Cu massively diffuses
compensating the absorber. If, in addition to these, an electron flux is
applied, Cu atoms migrate with increased energy, generating deep defects
like CuCd- that result in enhanced recombination, excluding the presence of
positively ionized copper atoms as it was proposed by Corwine et al. [2].
This could be explained by different etching, providing a different
intermixing between copper and CdTe.
Electrical characterization of high performance CdTe solar cells.
99
100
References
6.7 References
[1] A. Romeo, M. Terheggen, D. Abou-Ras, D. L. Batzner, F. J. Haug, M. Kalin,
D. Rudmann and A. N. Tiwari, Prog. Photovolt: Res. Appl. 12 (2004) 93111.
[2] C.R. Corwine*, A.O. Pudov, M. Gloeckler, S. H. Demtsu, J. R. Sites, Solar
Energy Materials & Solar Cells 82 (2004) 481–489.
[3] S. Demtsu, S. Bansal and D. Albin, Photovoltaic Specialists Conference
(PVSC), 2010 35th IEEE, 001161 – 001165.
[4] J.R. Sites, NREL Report 2002, NREL/SR-520-31458.
[5] I. Rimmaudo, A. Salavei and A. Romeo, Thin Solid Films-EMRS2012
Special Issue, accepted for publication.
[6] J. Beach, F-H Seymour, V. I. Kaydanov and T. R. Ohno, NREL Report 52041097.
[7] A. Castaldini, A. Cavallini, B. Fraboni, P. Fernandez, J. Piqueras, Journal of
Applied Physics, Volume 83, number 4, p 2121-2126.
Chapter 7
Final conclusions
An electrical characterization methodology has been used to address the
most important issues connected to CdTe technology, giving a remarkable
contribution to the production process development. In less than three
years an efficiency of than 14 % has been achieved (best cases exceeding 15
%).
7.1 Freon ® vs. CdCl 2 for low temperature deposition
process.
Two different activation treatments have been studied in our laboratory.
The first is based on a mixture of gases Ar and difluorochlorometane
(Freon®), the second is based on a liquid solution of CdCl2 in methanol.
Devices treated by Freon® show a small concentration of shallow defects
resulting in low free carriers concentration. Two deep defects were
identified, the first one present an activation energy of about 600 meV
probably responsible of the charge transport and the second of 700 meV
probably attributable to sulfur diffusion in CdTe. The presence of the typical
CdTe shallow defects was not registered, indicating that Freon® treatment
101
102
Properties of devices based on thin
CdTe layers
is not able to provide them for the low temperature grown CdTe process
(like vacuum evaporation). At the same time an excess of sulfur diffusion
was observed indicating a larger intermixed layer. On the other hand it has
been observed that the initial small crystallization due to the low deposition
temperature is drastically enhanced by the liquid CdCl2 treatment, and most
important also a lower concentration of deep defects is generated.
7.2 CdCl 2 activation treatment effects
The treatment based on liquid CdCl2 has been further investigated
modulating its effectiveness. A strong connection between the treatment
effectiveness (in terms of CdCl2 amount) and the defect concentration in
CdTe crystal has been observed. By increasing the quantity of CdCl2, the
shallow defects concentration increases, but on the other hand also more
deep defects are observed, these last ones also move towards the
CdTe/CdS interface.
CdTe doping increases as more CdCl2 is applied, but at the same time also
the recombination is enhanced as more by deep defects are formed near
the junction, the optimum treatment is achieved by the best tradeoff
between this two aspects.
By excess of CdCl2 the transport mechanism becomes dominated by the
recombination close to the interface in place of the one in the bulk. In these
samples deep defects at the interface have a big impact on the
recombination ratio. Such defects were identified as TeCd.
7.3 Properties of devices based on thin CdTe layers
Solar cells with different absorber layer thicknesses were prepared and
compared. Devices with very thin absorber layer of 0.7 m CdTe show an
efficiency of more than 7 %. However 10 % efficiencies are obtained when
the thickness is exceeding 1.5 m.
Chapter 7
Final conclusions
A linear increase of CdTe grains size with the increase of the CdTe thickness
was observed. The XRD patterns of thin CdTe show presence of sulfur and
intermixed CdSxTe1-x layer which takes a relevant part of the absorber.
The absence of pure CdTe can also explain the differences in the charge
profiles.
The ratio between the depletion region width and the absorber thickness
was calculated, suggesting that the dominant transport mechanism for thin
CdTe is recombination in the depletion region, probably resulting in
reduction of FF and Voc.
Furthermore typical CdTe shallow defects were not registered in thin CdTe
devices whereas Na impurities are suspected to take a relevant part of the
recombination mechanism.
An important reduction of the roll-over in the J/V characteristic as the CdTe
thickness reduces was observed.
In conclusion the preparation of a thin CdTe device implies not only issues
due to the optimization of the fabrication process such as lower light
absorption and possible pinholes but also issues connected with different
materials composition and different transport mechanism.
7.4 Cu diffusion in ageing process
Different thermal, optical and electrical stresses were applied to identical
solar cells, yielding different performance degradation dynamics. We have
observed different deep and shallow defects distributions, indicating that
Cu diffusion can differently affect the electronic structure of the absorber
changing the type of stress. By ageing the samples without any bias brings
to a defects compensation of the CdTe while applying a current deep
defects are generated in the bulk. In the latter case the dominant deep
defect has been identified as CuCd- whose presence was not revealed in the
other cases. Indeed we can conclude that the models proposed in the
literature are not suitable for our samples.
A possible alternative model able to describe the Cu migration for our
samples has been proposed. Cu moves only due to the concentration
Electrical characterization of high performance CdTe solar cells.
103
104
Cu diffusion in ageing process
gradient, diffusing slowly and with no appreciable changes in the absorber
density of states, if any external stress is applied. Under light and
temperature stimulation Cu massively diffuses compensating the absorber
defects. If, in addition to these, an electron flow is applied, Cu atoms
migrate with increased energy, generating deep defects like CuCd- that result
in enhanced recombination, excluding the presence of positively ionized
copper atoms. This could be explained by the different etching, providing a
different intermixing between copper and CdTe.
Appendix A
This appendix contains practical information about measurements
protocols and parameters, in order to make the studies described in the
thesis chapters reproducible.
A.1 Current-Voltage (J/V)
Current-voltage characteristics are performed by a Keitheley 2420
controlled by a specific LabView routine programmed ad hoc.
The sample is placed on a special support which allows to shine it from the
bottom while front and back contact (in the sample upper side) are
connected to the instrument via two probes. For best precision
measurements close to room temperature, a PT-100 stuck with a special
thermal conductive glue on the sample surface and a fan are used to
control the temperature in order to keep it constant.
With regards to the light exposure, we cover the measurement system with
a special black cover which allows dark conditions (Voc=0 V). On the other
hand for measurements in light conditions, the typical 1000 W/m2
irradiation is yielded by a calibrated halogen lamp. Calibration has been
performed by measuring the efficiency of one of our best cells by a PASAN
solar simulator and reproducing that condition by the halogen lamp. The
procedure has been repeated to check the stability of the calibration. Once
the AM 1.5 was reproduced the halogen lamp light intensity has been
measured by a silicon photodiode which current was taken as a reference
for daily calibrations. Before every measurement sessions the halogen lamp
is heated up for more than 30 min to ensure a constant emission spectrum
and afterwards the light intensity is set to the reference. The final efficiency
measurement error has been estimated around ± 0,5 %.
105
106
Cu diffusion in ageing process
J/Vs are performed sweeping the voltage applied to the contacts and
measuring the device output current. The Keitheley 2420 measurements
parameters are set via the LabView interface, which, after the acquisition,
also allows to visualize the output curve together with the process
parameters relative to the sample under test.
Applied voltage is usually swept in the range -0,4 V and 1 V. For our samples
this interval ensures at the same time to not affect the samples and to
extract all the information including roll-over. Bigger voltage intervals can
spoil the sample, depending on the temperature and light conditions. The
software allows also the inverted voltage ramp (from +1 V to -0.4 V) to
check hysteresis effects.
In general J/V curves should be acquired as quick as possible to avoid
unwanted effects (i.e. charge of parasitic capacitances, light soaking,
temperature increase…), but, at the same time, threshold parameter values
(i.e. Voc and Jsc) can be strongly affected by the number of acquired points
(pts). For J/Vs in light conditions the integral acquisition time of the Keithley
2420 is set to Medium which allows to acquire 200 pts in less than 4
seconds. Unfortunately to correctly sense the current in dark conditions the
integration time has to be increased to Normal to reduce the noise.
Measurement time rise to 15 s for 200 pts.
The software extracts Voc and Jsc from the J/V curve, implements eq. 2-1 and
2-2 to calculate Vm and Jm and finally calculates FF and η by eq. 1-7 and 1-9.
Rsh is obtained by linear interpolation of the curve near Jsc. Also Rs is
calculated in a similar manner (by linear interpolation close to Voc) but this
is a rough estimation.
To implement eq. 2-4 2-5 A and J0 are needed. They are extracted by a Java
software kindly provided by Warsaw Univesrity which fits numerically the
single diode equation (eq. 1-4). The graphical extraction described in
paragraph 2.2 are performed by Origin scripts programmed ad hoc.
A.2 Admittance measurements
The admittance measurements described in paragraph 2.3 are performed
by a HP 4284A equipped with a 16048 A test leads. A special box convert
Chapter 7
Final conclusions
the 4 terminals connections to 2 terminals one. Finally this box is connected
with BNC cables to the probes of the measurement system described in the
previous paragraph or to the cryostat described in paragraph A.3.
As described in Chapter 2, admittance techniques are able to provide many
information, but measurements can be tricky resulting in artifacts. To avoid
these is
A.2.1. DLCP and C/V
A.2.2. Admittance Spectroscopy
A.3 Temperature controlling system
Electrical characterization of high performance CdTe solar cells.
107