EEE2135 Digital Logic Design
Chapter 4. Combinational Logic Design
서강대학교
전자공학과
1. Circuit Optimization
1)
Goal: To obtain the simplest implementation for
a given function
Optimization is a more formal approach to
simplification that is performed using a specific
procedure or algorithm
Optimization requires a cost criterion to measure
the simplicity of a circuit
Distinct cost criteria we will use:
2)
3)
4)
a.
b.
c.
#Product terms in 2-level logic implementation
Literal count (for both 2-level and multi-level logics)
#Gates /#Gate inputs
Cost Function - #Product terms
a.
b.
In SOP representation
Primary goal to reduce #product terms by merging
adjacent terms
Cost Function - Literal Count
a.
b.
c.
•
•
•
•
Literal – a variable or it complement
Literal count – #literal appearances in a Boolean
expression corresponding to the logic circuit diagram
Examples:
F = BD + A B’ C + A C’D’
L=8
F = BD + A B’ C + A B’D’ + ABC’
L = 11
F = (A + B)(A + D)(B + C + D’)( B’ + C’ + D) L = 10
Which solution is best?
Cost Function - Gates/#Gate Inputs
a.
b.
#Gates
#Gate inputs -# inputs to the gates in the implementation
corresponding exactly to the given equations.
(G - inverters not counted, GN - inverters counted)
a. For SOP and POS equations, it can be found from the
equation(s) by finding the sum of:
•
All literal appearances
•
#terms excluding terms consisting only of a single literal
(G)
•
Optionally, #distinct complemented single literals (GN).
2. K-Map Method
1)
Karnaugh Map
a.
A modified truth table for minimal SOP, POS expression by
visual inspection
b. Logical adjacency : cell grouping
- Row (column) labels forms a Gray code
c. Minimization procedure
I.
Identify all PIs by encircling appropriate max-sized groups
of 1-cells
II. Select a min set of PI groups that cover all the 1-cells
(when ties , select one that has lowest literals counts)
* A group of 1-cells denoted by a product term and not in a
larger product group is a PI
z1 (a, b, c, d )   m(0,3,4,6,7,11,12,14,15)
d.
e.
Two-level SOP min. problem is solved by a minimal PI cover
EPI : a PI that covers 1-cell or min term that is not covered
by any other PI
Ex)
z1 (a, b, c, d )   m(1,3,5,10,11,12,13,14,15)
f.
Minimization with dc conditions
I.
certain input combinations never occur
II. certain inputs occur only under circumstances s.t. output
will not influence the system
III. Usually dc conditions are not given explicitly
ex) BCD-to-7-segment driver
a
a
b
c
d
e
f
g
w0
w1
w2
w3
f
e
w3 w2 w1 w0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
g
c
d
(a) Code converter
0
0
0
0
0
0
0
0
1
1
b
0
1
0
1
0
1
0
1
0
1
(b) 7-segment display
a
b
c
d
e
f
g
1
0
1
1
0
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
0
1
1
1
1
1
1
1
1
0
1
1
0
1
1
0
1
1
1
0
1
0
0
0
1
0
1
0
1
0
0
0
1
1
1
0
1
1
0
0
1
1
1
1
1
0
1
1
(c) Truth table
2)
Petrick’s Method (for PI selection) : not important
a.
b.
Method for finding a minimal cover
Expresses all the covering conditions that must be satisfied
ex) f   m(1,3,5)   d (11,13)
p  { p1,3 , p1,5 , p5,13 , p3,11}
c  ( p1,3  p1,5 )( p1,3  p3,11 )( p1,5  p5,13 )  p1,3 p1,5  ....  p1,5 p3,11 p5,13


3)
Each term represents a cover of M by p
Select the term with the fewest PIs where literal count is
minimal
Multiple-output Functions
a.
b.
Utilize shared terms - need mot be necessarily
Minimization – complicated
f1 (a, b, c, d )  abc  abc
f z  ab  bc
3. Quine-McCluskey Procedure
1)
Logic Simulation Minimization Programs
a.
b.
for functional correctness
simulation kernel + library + network description + input test
pattern +modeling + simulation control
c.
Minimization programs
I.
for two-level

exact minimization (less than 20 variables) - McBOOLE

approximate minimization - ESPRESSO
II. for multi-level (approximate min.)

ESPRESSO-MV

MIS and SIS
2) Algorithm Sketch
a.
b.
Using code words {0,1,-}
Phase 1: PI identification

Each codeword with k 1’s is compared to all codewords
with matching dashes and k+1 1’s
c. Phase 2: PI selection

cover table or PI table

Row dominance and column dominance
(delete dominated row) (delete dominating column)
3) Quine-McCluskey Method
a.
b.
c.
Uses the logical adjacency property
Compares each term with all the others, combine them if possible
Algorithm description
I.
Phase1 (PI identification): Form a list of all minterms and dc
terms L  L .Divide Li into groups G0 ,..., Gm (Gm contains minterms
& dc terms with m 1’s)
II. Compare each entry in Gh and Gh1 . Merge any two adjacent
terms and add it to group of Gh in Li 1
III. Any unchecked entries in Li are PIs.
Repeat steps II and III until Li 1 is empty
IV. Phase 2 (PI selection)
Set up a cover table T, t ij =1, if p i covers j-th minterm m j
V. Identify essential rows of T and add to solution set S. Reduce T
by removing essential rows, all columns covered by these rows
VI. If T is empty, S is the solution. Otherwise, go to step VII.
VII. Using the branch method, select a minimum-cost subset of the
remaining rows to (PIs) add to S
i
0
Example: f(a, b, c, d) =  m(0,2,4,5,6,9,10) + d(7,11,12,13,14,15)
1) Phase 1: PI Identification
L0
L1
Group0 0  0000
Group0 (0,2)
Group1 2  0010
4
0100
Group1
Group2
5
6
9
10
12
Group2
0101
0110
1001
1010
1100
Group3
7
0111
11 1011
13 1101
14 1110
Group4 15
1111
Group3
00-0
Example: f(a, b, c, d) =  m(0,2,4,5,6,9,10) + d(7,11,12,13,14,15)
L0
L1
Group0 0  0000
Group0 (0,2)
(0,4)
Group1 2  0010
4  0100
Group1
Group2
5
6
9
10
12
0101
0110
1001
1010
1100
Group2
Group3
7
0111
11 1011
13 1101
14 1110
Group4 15
1111
Group3
00-0
0-00
Example: f(a, b, c, d) = m(0,2,4,5,6,9,10) + d(7,11,12,13,14,15)
L0
L1
Group0 0  0000
Group0 (0,2)
(0,4)
00-0
0-00
Group1 2  0010
4  0100
Group1 (2,6)
0-10
Group2
5
6
9
10
12
0101
0110
1001
1010
1100
Group2
Group3
7
0111
11 1011
13 1101
14 1110
Group4 15
1111
Group3
Example: f(a, b, c, d) =  m(0,2,4,5,6,9,10) + d(7,11,12,13,14,15)
L0
L1
Group0 0  0000
Group0 (0,2)
(0,4)
00-0
0-00
Group1 2  0010
4  0100
Group1 (2,6)
(2,10)
0-10
-010
Group2
5
6
9
10 
12
Group2
0101
0110
1001
1010
1100
Group3
7
0111
11 1011
13 1101
14 1110
Group4 15
1111
Group3
Example: f(a, b, c, d) =  m(0,2,4,5,6,9,10) +  d(7,11,12,13,14,15)
L0
L1
Group0 0  0000
Gruop0 (0,2)
(0,4)
00-0
0-00
Group1 2  0010
4  0100
Group1 (2,6)
(2,10)
(4,5)
(4,6)
(4,12)
0-10
-010
01001-0
-100
Group2
(5,7)
(5,13)
(6,7)
(6,14)
(9,11)
(9,13)
(10,11)
(10,14)
(12,13)
(12,14)
01-1
-101
011-110
10-1
1-01
1011-10
11011-0
Group3 (7,15)
(11,15)
(13,15)
(14,15)
-111
1-11
11-1
111-
Group2
5
6
9
10 
12 
0101
0110
1001
1010
1100
Group3
7  0111
11  1011
13  1101
14 1110
Group4 15 1111
Example: f(a, b, c, d) =  m(0,2,4,5,6,9,10) + d(7,11,12,13,14,15)
L0
L1
L2
Group0 0  0000
Gruop0 (0,2)  00-0
(0,4)  0-00
Group1 2  0010
4  0100
Group1 (2,6) 
(2,10) 
(4,5) 
(4,6) 
(4,12) 
Group2
5
6
9
10 
12 
0101
0110
1001
1010
1100
Group3
7  0111
11  1011
13  1101
14 1110
Group4 15 1111
Group2
0-10
-010
01001-0
-100
(5,7)  01-1
(5,13)  -101
(6,7)  011(6,14)  -110
(9,11)  10-1
(9,13)  1-01
(10,11)  101(10,14)  1-10
(12,13)  110(12,14)  11-0
Group3 (7,15)  -111
(11,15)  1-11
(13,15)  11-1
(14,15)  111-
Group0
(0,2,4,6)
0--0
Group1
(2,6,10,14)
(4,5,6,7) 
(4,5,12,13) 
(4,6,12,14) 
--10
01—
-10-1-0
Group2
(5,7,13,15) 
(6,7,14,15) 
(9,11,13,15)
(10,11,14,15)
(12,13,14,15) 
-1-1
-111--1
1-111--
Group3
L3
Group1 (4,5,6,7,12,13,14,15)
-1--
Example: f(a, b, c, d) =  m(0,2,4,5,6,9,10) +  d(7,11,12,13,14,15)
L0
L1
Group0 0  0000
Group1 2  0010
4  0100
Group2
5
6
9
10 
12 
0101
0110
1001
1010
1100
Group3
7  0111
11  1011
13  1101
14 1110
Group4 15 1111
L2
(0,2)  00-0
(0,4)  0-00
(2,6) 
(2,10) 
(4,5) 
(4,6) 
(4,12) 
0-10
-010
01001-0
-100
(5,7)  01-1
(5,13)  -101
(6,7)  011(6,14)  -110
(9,11)  10-1
(9,13)  1-01
(10,11)  101(10,14)  1-10
(12,13)  110(12,14)  11-0
(7,15)  -111
(11,15)  1-11
(13,15)  11-1
(14,15)  111-
L3
(0,2,4,6)
0--0
(2,6,10,14)
(4,5,6,7)
(4,5,12,13)
(4,6,12,14)
--10
01—
-10-1-0
(5,7,13,15)
(6,7,14,15)
(9,11,13,15)
(10,11,14,15)
(12,13,14,15)
-1-1
-111--1
1-111--
PI0
(0,2,4,6)
0--0
PI1
PI2
(2,6,10,14)
(4,5,6,7,12,13,14,15)
--10
-1--
PI3
PI4
(9,11,13,15)
(10,11,14,15)
1--1
1-1-






(4,5,6,7,12,13,14,15) -1--
2) Phase 2: PI Selection
a. Cover Table
PI0(0--0)
PI1(--10)
PI2(-1--)
PI3(1--1)
PI4(1-1-)
m0
m2
x
x
x
m4 m5
x
x
x
m6
x
x
x
m9
m10
x
x
x
b. EPI = PI0 + PI2 + PI3 = a’d’ + b + ad
c. To cover m10, PI1 (=cd’ ) or PI4 (=ac) should be selected
4. Design Procedure
1)
2)
3)
4)
5)
Specification
a. Write a specification for the circuit if not already available
b. Executable specification more desirable
Formulation
- Derive an initial Boolean equations (or TT) that define the
required functions between inputs/outputs
Technology Independent Optimization
a. Apply 2-level and multiple-level optimization
b. Draw a logic diagram or provide a netlist for the resulting
circuit using generic logic gates
Technology Dependent Optimization and Technology Mapping
- Perform technology specific optimization and map the logic
diagram or netlist to the implementation technology selected
Verification
- Verify the correctness of the design
Design Example
1) Specification
a. BCD to Excess-3 code converter
b. Transforms BCD code for the decimal digits to Excess-3
code for the decimal digits
c. BCD code words for digits 0 through 9: 4-bit patterns 0000 to
1001, respectively
d. Excess-3 code words for digits 0 through 9: 4-bit patterns
consisting of 3 (binary 0011) added to each BCD code word
e. Implementation:
I. multiple-level circuit
II. NAND gates (including inverters)
2)
Formulation
a.
b.
c.
d.
Conversion of 4-bit codes can be most easily
formulated by a truth table
Variables
- BCD: A,B,C,D
Input BCD
Output Excess-3
Variables
ABCD
WXYZ
- Excess-3: W,X,Y,Z
0000
0011
0001
0100
Don’t Cares
0010
0101
- BCD 1010 to 1111
0011
0110
0100
0101
0110
0111
1000
1001
0111
1000
1001
1010
1011
1011
3)
Technology Independent Optimization
a. 2-level using K-maps
W = A + BC + BD
z
X = B’C + B’D + BC’D’
Y = CD + C’D’
Z = D’
G = 7 + 10 + 6 + 0 = 23
A
b. Perform extraction, finding factor
T1 = C + D
W = A + BT1
X = B’T1 + BC’D’
x
Y = CD + C’D’
Z = D’
G = 2 + 1 + 4 + 7 + 6 + 0 = 19
c. Additional Transformation
A
T1 ‘ = C’D’
G becomes 16
C
1
1
0
1
3
4
5
7
X
12
1
X
13
8
1
1
X
X
X
X
15
9
y
2
6
1
1
B
0
1
4
5
X
14
11
C
12
A
10
1
X
8
1
1
4
X
12
8
1
5
X
13
1
9
3
2
7
6
X
X
X
X
15
9
B
14
11
10
D
C
1
1
13
D
0
1
3
1
7
X
X
X
X
15
D
11
C
w
2
0
6
4
B
X
14
10
12
A
1
8
1
1
5
X
13
1
9
3
1
7
2
1
X
X
X
X
15
D
11
6
14
10
B
4)
Technology Mapping
- Mapping with a library containing inverters and 2-input NAND,
2-input NOR, and 2-2 AOI gates
A
A
W
B
X
W
B
X
C
C
D
Y
D
Y
Z
Z
5. Technology Mapping
1)
2)
3)
Chip design styles
Cells and cell libraries
Mapping techniques
a.
b.
c.
d.
4)
NAND gates
NOR gates
Multiple gate types
Programmable logic devices
Verification
1) Chip Design Styles
a.
I.
II.
b.
I.
II.
c.
I.
II.
d.
Full custom - the entire design of the chip down to the
smallest detail of the layout is performed
Expensive
Justifiable only for dense, fast chips with high sales volume
Standard cell - blocks have been designed ahead of time or
as part of previous designs
Intermediate cost
Less density and speed compared to full custom
Gate array/Sea-of-Gates: regular patterns of gate transistors
that can be used in many designs built into chip - only the
interconnections between gates are specific to a design
Lower cost
Less density compared to full custom and standard cell
FGPA
2) Cell Libraries
a.
b.
Cell : a pre-designed primitive block
Cell library : a collection of cells available for design using
a particular implementation technology
c.
Cell characterization
I.
II.
d.
A detailed specification of a cell for use by a designer
Often based on actual cell design and fabrication and
measured values
Cells are used for gate array, standard cell, and in some
cases, full custom chip design
e. Typical Cell Characterization Components
I.
II.
Schematic or logic diagram
Area of cell - Often normalized to the area of a common,
small cell such as an inverter
III. Input loading (in standard loads) presented to outputs
driving each of the inputs
IV. Delays from each input to each output
V. One or more cell templates for technology mapping
VI. One or more hardware description language models
VII. If automatic layout is to be used:

Physical layout of the cell circuit

A floorplan layout providing the location of inputs,
outputs, power and ground connections on the cell
Example Cell Library
Typical
Input-toOutput
Delay
Normalized
Area
Typical
Input
Load
Inverter
1.00
1.00
0.04
0.012
1
3 SL
2NAND
1.25
1.00
0.05
0.014
1
3 SL
2NOR
1.25
1.00
0.06
1 0.018 3 SL
2-2 AOI
2.25
0.95
0.07
1 0.019 3 SL
Cell
Name
Cell
Schematic
Basic
Function
Templates
3) Mapping: to NAND gates
a.
Assumptions:
I.
Gate loading and delay are ignored
II.
Cell library contains an inverter and n-input NAND gates,
n = 2, 3, …
III. An AND, OR, inverter schematic for the circuit is available
b.
The mapping is accomplished by:
I.
Replacing AND and OR symbols,
II.
Pushing inverters through circuit fanout points, and
III. Canceling inverter pairs
NAND Mapping Algorithm
a.
Replace ANDs and ORs:
.
.
.
.
.
.
b.
.
.
.
.
.
.
Repeat the following pair of actions until there is at most one
inverter between :
I. A circuit input or driving NAND gate output, and
II. The attached NAND gate inputs.
.
.
.
.
.
.
6. Delay
1) Delay Models
a.
b.
At a net node: Rising/falling delay
Port-to-port:
I.
Transport delay - a change in the output in response to a
change on the inputs occurs after a fixed specified delay
II. Inertial delay - similar to transport delay, except that if the
input changes such that the output is to change twice in a
time interval less than the rejection time, the output
changes do not occur. Due to

Capacitance charge /discharge

Unbalance between rising/falling delay
Models typical electronic circuit behavior, namely, rejects
narrow “pulses” on the outputs
c. Path Delay
2) Delay Model Example
A
B
A B:
No Delay
(ND)
Transport
Delay (TD)
a b
c d e
Inertial
Delay (ID)
0
2
4
6
Propagation Delay = 2.0 ns
8
10
12
14
Rejection Time = 1 .0 ns
16 Time (ns)
Waveforms for logic gates
VDD
Vin
50%
50%
Gnd
Transport delay
Transport delay
VDD
90%
Vout
Gnd
50%
10%
tr
Transport delay
Vin
Vout if delay = 0
Vout
90%
50%
10%
tf
DC Transfer characteristic of a CMOS inverter
Vf
VOH = VDD
Slope = –1
y=x
VDD
2
VOL = 0 V
VT
VIL
VIH
VDD
—
2
(VDD – VT ) VDD
Vx
3) Fanouts
* Fanout can be defined in terms of a standard load
a.
1 standard load equals the load contributed by the input of
one inverter.
b. Transition time -time required for the gate output to change
from H to L tHL, or from L to H, tLH (falling /rising delay)
c. The maximum fanout that can be driven by a gate is the
number of standard loads the gate can drive without
exceeding its specified maximum transition time
d. The fanout loading affects the gate’s propagation delay
e.
Example:
•
One realistic equation for tpd for a NAND gate with 4
inputs is: tpd = 0.07 + 0.021 SL ns
•
SL is the number of standard loads the gate is driving,
i. e., its fanout in standard loads. SL = 4, tpd = 0.151 ns
7. Delay Analysis
1)
Single Component Delay
a.
b.
2)
Rising / falling time
Transport delay and Intrinsic ( inertial ) delay
Multiple Component Delay : Path Delay
a.
Delay for a signal to propagate from a net node to another net
thru gates following a specified path
b. Critical paths/Critical section
I.
paths with the max delay in a circuit
II. Paths whose delays exceed the given specification (max.
allowed delay)
c. Analysis
I.
Signal Ready (Arrival) Time
r (v j )  d j 
max
kK
r (v k )
d j: delay of gate j;
K : set of fanins to gate j
Delay Analysis
II. Slack
- amount of delay that can be added to a node without violating
the given specification (maximum allowed delay)
vk1
vj1
for output nodes
s(vi) = max. allowed delay – r(vi)
for internal nodes
vk2
vk3
vj2
s(vi ) 
min
jJ
[ s (v j ) 
max
kK
{r (vk )}  r (vi )]
J  { j /( vi , v j )  A}
vi
r (v j )  d j 
max
kK
r (vk )
K  {k /(vk , v j )  A, v j  J }
vk: gates that drive the gates (vj) driven by vi
Example: Maximum allowed delay = 11ns
- Numbers inside circles represent the delay (in ns)
associated with the gates
3
va
vd
3
vf
2
4
vb
4
44
5
t=0
vc
vg
ve
3
vh
Solution
I. Signal arrival time
r (v a )  3 r (vb )  4 r (vc )  5
r (vd )  max{ r (va ), r (vb )}  d d  6
r (v f )  max{ r (v d ), r (ve )}  d f  12
r (ve )  max{ r (vb ), r (vc )}  d e  9
r (v g )  r (v d )  d g  10
r (vh )  max{ r (ve ), r (vc )}  d h  12
II. Slack
s(vf) = 11 – 12 = -1, s(vg) = 11 – 10 = 1, s(vh) = 11 – 12 = -1
s(vd) = min s(vf) + max(r(vd), r(ve)) - r(vd) = 2
=1
s(vg) + max(r(vd)) - r(vd) = 1
s(ve) = min s(vf) + max(r(vd), r(ve)) - r(ve) = -1
= -1
s(vh) + max(r(vc), r(ve)) - r(ve) = -1
s(va) = s(vd) + max(3, 4) - 3 = 2
s(vb) = min s(vd) + max(3, 4) - 4 = 0 s(vc) = min s(ve) + max(4, 5) -5 = -1
s(ve) + max(4, 5) - 4
s(vh) + max(9, 5) -5
{
{
{
{
Analysis Results : Critical Section in Red
3
va
vd
3
vf
2
4
vb
4
44
5
t=0
vc
vg
ve
3
vh
Discussions
a. Why do we need path analysis ?
I. Consider the RT model of a digital system
II. The maximum delay of all the combinational circuits in the
datapath determines the maximum clock frequency
- fc, max < 1/ max(dcc) (* This will be refined later)
register
register
CC1
register
CC2
clock
b. We must eliminate the critical sections by
I. Resizing the transistors to reduce the delay of the gates
II. Restructuring/Redesigning