‫מבנה המחשב ‪ +‬מבוא למחשבים ספרתיים‬
‫תרגול ‪#7‬‬
‫‪Addition‬‬
Definition of a binary adder
A binary adder with input length n is a combinational circuit specified as follows:
Input : An - 1 : 0, Bn - 1 : 0 0,1 , and C[0]  0,1.
n
Output : Sn - 1 : 0 0,1 and C[n]  0,1.
n
Functional ity :



n
S  2  Cn  A  B  C0
Claim: the functionality of Adder(n) is well defined.
We show that for every A[n-1:0], B[n-1:0] and C[0] there exists S[n-1:0] and C[n]



such that:
n
S  2  C n  A  B  C 0
An  1 : 0 0,1
An  1 : 0  0,1, ,2 n  1
Bn  1 : 0 0,1
Bn  1 : 0  0,1, ,2 n  1
n
n
C 0 0,1


A  B  C0 
0,1,,2
n 1
 1
S n  1 : 0  0,1,,2 n  1
S n  1 : 0 0,1
n
C n 0,1
if C n  0, then

S  2n  0 
0,1,,2
if C n  1, then

S  2 n 1 
0  2 ,1  2 ,,2

S  2n  Cn 
n
n
 1
n
n
 1  2n 
0,1,,2 1,2 ,2  1,,2
 0,1,,2  1
n
n
n 1
n
n 1
 1
Lower bounds on the cost and delay of combinational circuits
that implements Adder(n)
We would like to show a lower bound of linear cost and logarithmic delay in n.
It’s suffices to show that there exists at least one output, σ, of Adder(n) such that
|cone(σ)| = n with respect to Adder(n) .
We show that the cone size of the carry-out bit C[n] is 2n+1.
Input bit A[i] , 0 ≤ i ≤ n-1, is in the cone of C[n]:
Set A[n-1:i+1] = 0n-i-1, A[i-1:0] = 0i , B[n-1:0] = 1n , and C[0] = 0.
If A[i] = 0, then


A  B  C 0  0  2 n  1  0  2 n  1
Necessarily C[n] = 0, otherwise

S  2 n  C n  2 n  1 a contradiction.
If A[i] = 1, then


A  B  C 0  2 i  2 n  1  0  2 n
Necessarily C[n] = 1, otherwise

S  2 n  C n  2 n  1 a contradiction.
By symmetry, every bit in the string B[n-1:0] is also in the cone of C[n].
The carry-in bit C[0] is like A[0], therefore C[0] is also in the cone of C[n].
ConeCnwith respect to Adder(n)   An  1 : 0, Bn  1 : 0, C0
Cost  Adder n   n 
Delay Addern  log n
Note that the same setting also proves:
0  j  n  1. ConeC j  1  ConeS  j   A j : 0, B j : 0, C0
Conditional Sum Adder – CSA(n)
Correctness Proof
The proof is by induction on n.
The induction basis, for n = 1, follows directly from the definition of a
Full-Adder.
The induction hypothesis, for m < n, is:
Am  1 : 0  Bm  1 : 0  C 0  2 m  C m  S m  1 : 0
Induction step, we prove for n:
hypothesis
induction


(1)
Ak  1 : 0  Bk  1 : 0  C 0  2 k  C k   S k  1 : 0
hypothesis
induction


(2a)
An  1 : k   Bn  1 : k   C0 n  S0 n  1: k 
(2b)
An  1 : k   Bn  1 : k   2k  C1n  S1n  1: k 
If Ck   0 , then Sn - 1 : k   S0 n - 1 : k  and Cn  C0 n
(1) (2a) 
Ak  1 : 0  Bk  1 : 0  C0  An  1 : k   Bn  1 : k 
 2 k  0  S k  1 : 0  2 n  C0 n  S 0 n  1 : k 

An  1 : 0  Bn  1 : 0  C 0  2 n  C n  S n  1 : 0
If Ck   1 , then Sn -1 : k   S1n -1 : k  and Cn  C1n
(1) (2b) 
Ak  1 : 0  Bk  1 : 0  C 0  An  1 : k   Bn  1 : k   2 k 1
 2 k 1  S k  1 : 0  2 n  C1 n  S1 n  1 : k 

An  1 : 0  Bn  1 : 0  C 0  2 n  C n  S n  1 : 0
QED
CSA(n) - Delay and Cost analysis under fan-out limitations
n–k+1
1
Assume that n = 2l and set k = n/2,
if n  1
d  FA 
d CSAn   
n
n
d CSA 2   log 2   d buf   d MUX  otherwise
if n  1
c FA 
cCSAn   
n
n
3  cCSA 2   n   cbuf    2  1  cMUX  otherwise
n  2l ,
for simplicity : d  FA   d MUX   d buf   1
d n   d  n2   log n2   1
 d  n2   logn   log2  1
 d  n2   logn 
 d 1  logn   log n2   log n4     log2ni     log2nl 
 1  l  l  1    1  0
 l 2 
 log 2 n 
cn   3  c n2    n2  1  cMUX   n   cbuf 
cn   3  c n2   n 
Master Theorem for recurrences provides:
cn   n log 2 3   n1.58 
We didn’t take into account the fan-out of the input gates.
Is it justified in the case of CSA(n)?
Cost:
Note that all input gates feed Full-Adder circuits only.
How much FAs are there in CSA(n)?
f n   3  f  n2   3log 2  n   n log 2 3  n1.58
 The fan-out of all input gates together is Θ(n1.58).
 The total cost needed for buffers is Θ(n1.58).
Delay:
The MSBs A[n-1] and B[n-1] have the maximum fan-out.
fan  out  An  1  fan  out Bn  1  2log2 n
The input gates’ fan-out in the case of CLA(n) is counted only once
and it is at most:
log 2 n
log2
  log n
2
To conclude, in CSA(n) design:
• No change in cost asymptotics due to fan-out limitations.
• Quadratic increase in delay asymptotics due to fan-out limitations.