Recall Last Lecture
• The MOSFET has only one current, ID
• Operation of MOSFET
– NMOS and PMOS
– For NMOS,
• VGS > VTN
• VDS sat = VGS – VTN
– For PMOS
• VSG > |VTP|
• VSD sat = VSG + VTP
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• ID versus VDS (NMOS) or ID versus VSD (PMOS)
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• PMOS
• NMOS
o VTN is POSITIVE
o VGS > VTN to turn on
o Triode/nonsaturation region
2
I D  K n [2VGS  VTN VDS  VDS ]
o Saturation region
I D  Kn VGS  VTN 
2
o VDSsat = VGS - VTN
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o VTP is NEGATIVE
o VSG > |VTP| to turn on
o Triode/nonsaturation region
2
I D  K p [2VSG  VTP VSD  VSD ]
o Saturation region
I D  K p VSG  VTP 
2
o VSDsat = VSG + VTP
DC analysis of FET
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MOSFET DC Circuit Analysis - NMOS

The source terminal is at
ground and common to
both input and output
portions of the circuit.

The CC acts as an open
circuit to dc but it allows
the signal voltage to the
gate of the MOSFET.

In the DC equivalent circuit, the gate current into the transistor is
zero, the voltage at the gate is given by a voltage divider principle:
VG = VTH =
R2
R1 + R2
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VDD
MOSFET DC Circuit Analysis - NMOS
1. Calculate the value of VGS
2.
Assume the transistor is biased in the saturation
region, the drain current:
I D  Kn VGS  VTN 
2
3. Use KVL at DS loop
IDRD + VDS – VDD = 0
VDS = VDD - IDRD
4.
Calculate VDSsat = VGS - VTN
5.
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Confirm your assumption:
If VDS > VDS(sat) = VGS – VTN, then the transistor is biased in the saturation
region. If VDS < VDS(sat), then the transistor is biased in the nonsaturation region.
EXAMPLE:
Calculate the drain current and drain to source voltage of a common source circuit
with an n-channel enhancement mode MOSFET. Assume that R1 = 30 k, R2 = 20 k,
RD = 20 k, VDD = 5V, VTN = 1V and Kn = 0.1 mA/V2
1. Calculate the value of VGS
2.
Assume the transistor is biased in the saturation
region, the drain current:
I D  K n VGS  VTN 
2
I D  0.1(2  1) 2  0.1mA
3. Use KVL at DS loop
IDRD + VDS – VDD = 0
VDS = VDD – IDRD = 3 V
4.
5.
Calculate VDSsat = VGS – VTN = 2 – 1 = 1V
Confirm your assumption: VDS > VDSsat, our assumption that the transistor is
in saturation region is correct
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EXAMPLE
• The transistor has parameters
VTN = 2V and Kn = 0.25mA/V2.
• Find ID and VDS
R1 = 280k
R2 = 160k
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VDD = 10V
RD = 10k
Solution
1. Calculate the value of VGS
KVL at GS loop: VGS – VTH + 0 = 0  VGS = VTH
2.
Assume the transistor is biased in the saturation region, the drain current:
I D  K n VGS  VTN 
2
I D  0.25(3.636  2) 2  0.669mA
3. Use KVL at DS loop
IDRD + VDS – VDD = 0
VDS = VDD – IDRD = 3.31 V
4.
Calculate VDSsat = VGS – VTN = 3.636 – 2 = 1.636 V
5.
Confirm your assumption: VDS > VDSsat, our assumption that the transistor is
in saturation region is correct
Answer: ID = 0.669 mA and VDS = 3.31 V
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MOSFET DC Circuit Analysis - PMOS
Different notation:
VSG and VSD
Threshold Voltage = - VTP
VDD
R1
ID
VSG
-
+
+
VSD
-
R2
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RD
ID
Calculate the drain current and source to drain voltage of a common source circuit with
an p-channel enhancement mode MOSFET.
Also find the power dissipation. Assume that, VTP = -1.1V and Kp = 0.3 mA/V2
5V
1. Calculate the value of V
SG
VTH = 2.5 V
Use KVL at SG loop:
VSG + 0 +2.5 – 5 = 0
VSG = 5 – 2.5 = 2.5 V
2.
Assume the transistor is biased in the saturation
region, the drain current:
2
I D  K p VSG  VTP 
I D  0.3(2.5  1.1) 2  0.588mA
50 k
50 k
7.5 k
3. Use KVL at SD loop
IDRD + VSD – VDD = 0
VSD = VDD – IDRD = 0.584 V
4.
5.
Calculate VSDsat = VSG +VTP = 2.5 – 1.1 = 1.4 V
Confirm your assumption: VSD < VSD sat , so our assumption that the transistor is
in saturation region is incorrect
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That means our transistor is in non-saturation mode: Go back to step 2
I D  K p [2VSG  VTP VSD  VSD ]
2
ID = 0.3 2 ( 1.4 ) (5 – IDRD) – (5 – IDRD)2
ID = 0.3 2.8 (5 – 7.5 ID) – (5 - 7.5 ID)2
ID = 0.3 14 – 21 ID – (25 – 75ID + 56.25 ID2)
ID = 0.3 14 – 21 ID -25 +75 ID – 56.25 ID2
ID = 4.2 – 6.3 ID – 7.5 +22.5 ID – 16.875 ID2
ID = 0.536 mA
16.875 ID2 – 15.2 ID + 3.3 = 0
ID = 0.365 mA
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ID = 0.536 mA
VSD = 5 – IDRD = 0.98 V
ID = 0.365 mA
VSD = 5 – IDRD = 2.26 V
VSD sat = VSG + VTP = 2.5 – 1.1 = 1.4V
0.98V < 1.4V
Smaller than VSD sat : non saturation
Answer: ID = 0.536 mA and VSD = 0.98V
Power dissipation = ID x VSD = 0.525 mW
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2.26V > 1.4V
Bigger than VSD sat : saturation
LOAD LINE, ID versus VDS
• Common source configuration i.e source is
grounded.
• It is the linear equation of ID versus VDS
• Use KVL
• VDS = VDD – IDRD
• ID = -VDS + VDD
RD
RD
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ID (mA)
y-intercept
ID
Q-POINTS
VDS
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VGS
x-intercept
VDS (V)
• DC Analysis where source is NOT GROUNDED
For the NMOS transistor in the circuit below, the parameters are VTN = 1V and
Kn = 0.5 mA/V2.
+5V
RD = 2 k
-1V
RG = 24 k
RS = 1 k
-5V
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+5V
1. Calculate the value of VGS
KVL at GS loop:
2.
0 + VGS+ 1(ID) -5 +1 = 0
VGS = 4 - ID
Assume the transistor is biased in the saturation
region, the drain current:
I D  K n VGS  VTN 
2
ID
RG =24 k
1V
I D  0.5(4  I D  1) 2  0.5(3  I D ) 2
2I D  9 – 6I D  I D
RD =2 k
ID
RS = 1 k
2
5V
I D – 8I D  9  0
2
ID = 6.646 mA
ID = 1.354 mA
Replace in VGS
equation in step 1
VGS = 4 - ID
Why choose VGS = 2.646 V ?
Because it is bigger than VTN
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VGS= -2. 646 V
VGS = 2.646 V
+5V
3. Use KVL at DS loop
IDRD + VDS + IDRS – 5 – 5 = 0
1.354 (2) + VDS + 1.354 – 10 = 0
VDS = 10 – 1.354 – 2.708 = 5.938 V
ID
RD =2 k
RG =24 k
1V
ID
RS = 1 k
5V
4.
Calculate VDSsat = VGS – VTN = 2.646 – 1 = 1.646 V
5.
Confirm your assumption: VDS > VDS sat , our assumption is correct
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EXERCISE 1
• The transistor parameters are VTN = 0.4 V, Kn = 3 mA/V2.
The value of the current, ID = 0.35 mA
i.
ii.
Calculate value of VDS and VGS
Calculate VDSsat . Is the transistor in saturation?
I D  Kn VGS  VTN 
ID
2
I D  K n [2VGS  VTN VDS  VDS ]
2
Answers:
Part (i)
VDS = 1.1 V
VGS = 0.742 V
Part (ii)
VDS sat = 0.342 V
YES
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EXERCISE 2
Assume that the transistor parameters are VTN = 0.8 V and
Kn = 0.80 mA/V2. Given VDD = 5V and R1+ R2 = 670 kΩ,
design the circuit such that ID = 0.88 mA and VDS = 2.5 V.
Confirm any assumptions you make during your analysis.
Answers:
R1 = 422 kΩ
R2 = 248 kΩ
RD = 2.84 kΩ
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