CHAPTER 2
P2.1. a) The solution for the NMOS case is based on Example 2.4:
The equation for VT0 is: VT 0  VFB  2F 
QB
COX
Calculate each individual component.
Fp
ni
kT
3 1017

ln
 0.026 ln
 0.44 V
q
NA
1.4 1010
GC  Fp  G ( gate )  0.44  0.55  0.99 V
 OX  4 0  3.5 1013 F/cm
7
QB 0  3 10 C / cm
2
COX  1.6 106 F/cm 2
QB 0
3 107

 0.188 V
COX 1.6 106
QOX 6 1011 1.6 1019

 0.06 V
COX
1.6 106
VTO  0.99  (0.88)  (0.188)  0.060  0.018 V
For the PMOS device:
Fn 
kT N D
3 1017
ln
 0.026 ln
 0.44 V
q
ni
1.4 1010
GC  Fn  G ( gate )  0.44  0.55  0.99 V
QB 0  3 107 C / cm 2
QB 0
3 107

 0.188 V
COX 1.6 106
QOX 6 1011 1.6 1019

 0.06 V
COX
1.6 106
VTO  0.99  (0.88)  (0.188)  0.060  0.138 V
b) The magnitude of VT0 would be higher. Since the device is PMOS this means that VT0 is
lowered. Since the only thing that’s been changed is the doping of the gate, only G changes.
The new VT0 then becomes:
VT 0  0.11  0.88  0.188  0.6  1.24V
c) Since VT0 will be adjusted with implanted charge (QI):
QI
 0.4  0.018
COX
QI
 0.382V
COX
QI  (1.6 106 )(0.382V )
To calculate the threshold implant level NI:
qN I  QI
NI 
QI
q
For the NMOS device from part(a):
NI  
QI
0.6 106

 3.82 1012 ions / cm2 (p-type)
19
q
1.6 10
For the PMOS device from part(a):
NI  
QI
(1.6 106 )(0.4  0.138)

 2.62 1012 ions / cm2 (n-type)
19
q
1.6 10
For the PMOS device from part(b):
QI
(1.6 106 )(1.24  0.4)
NI  

 8.4 1012 ions / cm2 (p-type)
19
q
1.6 10
d) The advantage of having the gate doping be n+ for NMOS and p+ for PMOS could be
seen from analysis above. Doping the gates in such a way leads to devices with lower
threshold voltages, but enables the implant adjustment with the same kind of impurities
that used in the bulk (p-type for NMOS and n-type for PMOS). If we were to use the
same kind of doping in gate as in the body (i.e. n+ for PMOS and p+ for NMOS) that
would lead to higher un-implanted threshold voltages. Adjusting them to the required
lower threshold voltage would necessitate implantation of the impurities of the opposite
type near the oxide-Si interface. This is not desirable. Also, the doping of the poly gate
can be carried out at the same time as the source and drain and therefore does not require
an extra step.
P2.2. First, convert tox to units of cm:
tox  22Å
100cm
 22 108 cm
10
10 Å
Now, using the mobility equation:
ep 
0 p
 V V 
1   GS T 
  tox 
n

130 cm2 / V  s
1.85


0.8

1 
  4 106  22 108  


 70
V
cm
P2.3. a) For each transistor, derive the region of operation. In our case, for VGS  0V,0.4V , the
transistor is in the cutoff region and there is no current. For VGS  0.8V,1.2V , first
calculate the saturation voltage VDsat using:
VDSAT 
VGS  VT  EC L
VGS  VT  EC L
For our transistors, this would be:
NMOS
PMOS
VGS  0.8V
0.24V
0.35V
VGS  1.2V
0.34V
0.61V
Next, we derive the IV characteristics using the linear and saturation current equations,
we get the graphs shown below.
IV Characteristic of NMOS
70
Current (uA)
60
50
40
Vgs = 1.2V
30
Vgs = 0.8V
20
10
0
0
0.2
0.4
0.6
Volts (V)
0.8
1
1.2
IV Characteristic of PMOS
0
-1.2
-1
-0.8
-0.6
-0.4
-0.2
-5
Current (uA)
-1.4
0
-10
Vgs = -1.2V
Vgs = -0.8V
-15
-20
-25
-30
Volts (V)
To plot I DS vs. VGS , first identify the region of operation of the transistor. For VGS  VT , the
transistor is in the cutoff region, and there is negligible current. For VGS  VT and VGS  VDS , the
transistor is in the saturation region and saturation current expression should be used. The graph
is shown below. Clearly, it is closer to the linear model.
Ids vs. Vgs of NMOS
70
60
Ids (V)
50
40
30
20
10
0
0
0.2
0.4
0.6
0.8
Vgs (V)
1
1.2
1.4
P2.4. For each transistor, first determine if the transistor is in cutoff by checking to see if VGS is
less than or greater than VT. VT may have to be recalculated if the source of the transistor
isn’t grounded. If VGS is less than VT, then it is in cutoff, otherwise, it is in either triode or
saturation.
To determine if it is in the triode saturation region, check to see if VDS is less than or
greater than VDSAT. If VDS is less than VDSAT, then it is in triode, otherwise, it is in
saturation.
a. Cutoff
VGS  VG  VS  0.2  0  0.2V
VT  VT 0  0.4V
VGS  VT
b. Cutoff
VGS  VG  VS  1.2  1.2  0V
VT  VT 0  0.4V
VGS  VT
c. Linear
VGS  VG  VS  1.2  0  1.2V
VT  VT 0  0.4V
VGS  VT
The transistor is not in the cutoff region.
VDSAT 
VGS  VT  EC L  1.2  0.4  6  0.2   0.48V
VGS  VT  EC L 1.2  0.4   6  0.2 
VDS  0.2V
VDS  VDSAT
d. Saturation: In this case, because VD  VG the transistor is in the saturation region. To
see this, recognize that in a long-channel transistor if VD  VG , the transistor is in
saturation. Since the saturation drain voltage VDsat is smaller in a velocity-saturated
transistor than in a long-channel transistor, if the long-channel saturation region
equation produces a saturated transistor, than the velocity-saturated saturation region
equation will also.
P2.5. In both cases, the first step it to calculate the maximum value of VX given VG . If the
voltage at the drain is higher than this maximum value, then VX  VX ,max , otherwise,
VX  VD . The maximum value of VX is VG  VT but VT  VT 0 because of body effect and
we consider its effect.

VX ,max  VG  VT  VG  VT 0  
 VG  VT 0  


VSB  2  F  2  F
VX ,max  2  F  2  F


 VG  VT 0   VX ,max  2  F   2  F
 1.2  0.4  0.2 VX ,max  0.88  0.2 0.88
 0.988  0.2 VX ,max  0.88
There are two ways to calculate this, either through iteration or through substitution.
Iteration:
For the iteration method, we need a starting value for VX,max. A good starting value would
be VG  VT 0  1.2  0.4  0.8V . We plug this value on the RHS of the equation, calculate a
new VX,max and repeat until we reach a satisfactory converged value.
Old Vx,max New Vx,max
0.800
0.728
0.728
0.734
0.734
0.734
In this, only three iterations are needed to reach 0.734V.
Substitution:
The
VX ,max  0.88 term makes things a bit tricky, we get around this by making the
following substitution:
x 2  V X ,max  0.88

VX ,max  x 2  0.88
Therefore:
VX ,max  0.988  0.2 VX ,max  0.88
x 2  0.88  0.988  0.2 x 2
0  x 2  0.2 x  1.87
2
b  b2  4ac 0.2  0.2  4 1 1.87 
x

 1.27, 1.47
2a
2 1
VX ,max  x 2  0.88  0.733, 1.28
We use the first value since second value is above VDD.
a. Since VD  VX ,max , VX  VX ,max  0.733V .
b. Since VD  VX ,max , VX  VX ,max  0.6V .
P2.6.
a. Initially, when Vin  0V , the transistor is in the cutoff region and VX  0V . This
value is constant until Vin exceeds Vt0. From then, VX  Vin  VT and body effect must
be taken into account. This trend continues until VX  VD  0.7V , and the value of Vin
at that point must be calculated. From then on, VX  VD  0.7V .
To plot VX in the second region, we first derive an expression for VX vs. Vin.

VX ,max  VG  VT  VG  VT 0  
 Vin  VT 0  


VSB  2  F  2  F
VX ,max  2  F  2  F

 Vin  VT 0   VX ,max  2  F   2  F
 Vin  0.4  0.2 VX ,max  0.88  0.2 0.88
 Vin  0.212  0.2 VX ,max  0.88
Substituting:
x 2  V X ,max  0.88

VX ,max  x 2  0.88
Therefore:
VX ,max  Vin  0.212  0.2 VX ,max  0.88
x 2  0.88  Vin  0.212  0.2 x 2
0  x 2  0.2 x  Vin  0.66

2
b  b2  4ac 0.2  0.2  4 1 Vin  0.66 
x

2a
2 1

0.2  4Vin  2.71
2
2
 0.2  4Vin  2.71 
VX  x  0.88  
  0.88

2


2
Since this is a quadratic function, there will be two graphs of VX. Only one of these
graphs intersects with VX in the first region. In this case, plug Vin  0.4 and see which
one gives 0V. In our case, it would be the ‘+’ version of the quadratic.
To see where region 3 begins, we simply isolate Vin:
2
 0.2  4Vin  2.71 
VX  
  0.88

2


Vin
2


2

2
VX  0.88  0.2  2.71
4

2


2
0.7  0.88  0.2  2.71
4
2
0.7  0.88  0.2  2.71
4
 1.16V
The final graph is shown in Figure P2.6a:
Vx vs. Vin
Vx (V)
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0
0.2
0.4
0.6
0.8
1
1.2
1.4
Vin (V)
Figure P2.6a
b. In this question VX  Vin until VX  VX ,max . To calculate VX,max, we can use the
equation from P2.6a.
2
VX ,max
 0.2  4VG  2.71 

  0.88

2


2
 0.2  4 1  2.71 
  0.88  0.549, 1.066



2


The second value is invalid because it is higher than the gate voltage. The plot is
shown below.
Vx vs. Vin
0.6
Vx (V)
0.5
0.4
0.3
0.2
0.1
0
0
0.2
0.4
0.6
0.8
1
1.2
Vin (V)
P2.7. First, let’s convert the units into terms of fF and μm.
106 μm
 0.1μm
109 nm
106 μm
W  400nm  9
 0.4μm
10 nm
106 μm
Y  300nm  9
 0.3μm
10 nm
106 μm
x j  65nm  9
 0.065μm
10 nm
L  100nm 
2
F 1015 fF  100cm 
fF
Cox  1.6  10

 6
 16 2

2
cm
1F
μm
 10 μm 
6
Now we can calculate the capacitances.
CG  CoxWL  16 0.4  0.1  0.64fF
CJ  KeqC jb Y  x j W   0.81.6 0.3  0.065 0.4   0.19fF
1.4
P2.8. (a) Transistor is in cutoff. IDS=Isub.
(b) Transistor is in cutoff. IDS=Isub.
(c) Transistor is in the linear region.
I DS 
I DS  4 
eCox
V
W

(VGS  VT  DS )VDS
L (1  VDS )
2
Ec L
270(1.6 106 )
0.2
(1.2  0.4 
)0.2  181 A
0.2
2
(1 
)
0.6
(d) Transistor is in the saturation region.
I DS  W sat Cox
(VGS  VT ) 2
(VGS  VT )  Ec L
I DS  (0.4)104 (8 106 )(1.6 106 )
(0.8  0.4)2
 82 A
(0.8  0.4)  0.6
P2.9. Since the lengths are the same, the saturation voltage VDsat will be the same.
VDsat 
VGS  VT  EC L  1.2  0.4  6 0.1  0.34V
VGS  VT  EC L 1.2  0.4   6  0.1
The graphs of the two transistors are shown in Figure P2.9. Notice that the main
difference between the two curves is that when we double the width, we double the
current.
Ids vs. Vds
250.00
Ids (uA)
200.00
Idsa Linear
150.00
Idsa Saturation
100.00
Idsb Linear
Idsb Saturation
50.00
0.00
0
0.2
0.4
0.6
0.8
Vds (uA)
1
1.2
1.4
P2.10. a) The values of Ks and α can be calculated using the current values in the saturation
region. Since the alpha-power model equation ( I DS  K s WL (VGS  VT ) ) only contains two
unknowns, we need two equations. From P2.3:
NMOS
PMOS
VGS  0.8V
58.51μA
24.09μA
VGS  1.2V
20.48μA
6.83μA
Table Error! Reference source not found.P2.10: Saturation Voltage
For the NMOS:
58.51  K s WL (1.2  0.4)  K s WL (0.8)
20.48  K s WL (0.8  0.4)  K s WL (0.4)
Dividing the two produces   1.51 .
Now plugging α into one of the equations:
1.51
58.51  K s  0.1
0.1  (0.8)
K s  82.04
For the PMOS:
24.09  K s WL (1.2  0.4)  K s WL (0.8)
6.82  K s WL (0.8  0.4)  K s WL (0.4)
Dividing the two produces   1.82 .
Now plugging α into one of the equations:
1.82
24.09  K s  0.1
0.1  (0.8)
K s  36.16
b) For the linear region, we can model I DS using the following equation
W
I DS  K L (VGS  VT ) VDS
L
K L can be calculated by measuring I DS in the linear region ( VDS  VDSat ) and plugging
I DS ,VDS into the above equation. However, to validate the model, you should get a reasonable
VDSat at the boundary of the two regions (i.e., VDSat derived in 3c) should be close to VDSat
predicted by velocity saturated model). Be sure to check the model against experimental data
(SPICE curves) for several values of I DS in linear region.A reasonable value for K L is
200 A / V 2 ; other values are acceptable as long they are in the same range. Equating the two
expressions for I DS at the boundary of linear and saturation region, we get the formula for VDSat ;
K
VDSat  S (VGS  VT ) 1  0.45(VGS  VT )0.25
KL