®
BuildGates
Scott McClure
Greg Edmiston
August 2004
Tutorial
Tutorial Disclaimer

This tutorial includes one way of synthesizing in
BuildGates. This is not necessarily the best way
of synthesizing, depending on your
requirements. This tutorial is a simple stepthrough designed to familiarize the user with
BuildGates, and thus is basic in nature. More
advance methods of the synthesis procedure
are not found in this tutorial.
Create New Directory
Create a new directory in your home
directory called “example”
 Create and Save the following files in the
“example” directory
 my_design.v, ff.v, mux.v, full_adder.v

**Reference Bindal, San Jose State University
Top Module
Flip Flop Module
Full Adder Module
Mux Module
Generate “setup.tcl” file
Create file with following text
 Save as “setup.tcl”

Launching PKS (BuildGates)

In a terminal window type “pks_shell –gui &”

Source the setup file inside the pks_shell by typing
“source setup.tcl”
Run the setup by typing “setup”

BuildGates Command Procedure

Run the following lines at the shell prompt
inside BuildGates
 set
top my_design
 read_verilog my_design.v full_adder.v mux.v ff.v
 do_build_generic –module my_design

When generic synthesis is complete then double
click on the my_design module to view its
schematic
Generic Build (my_design Schematic)
Full Adder Sub-Module
Flip-Flop Sub-Module
Mux Sub-Module
Timing verification file

Construct the following file and save it as
“timing.tcl”
BuildGates Command Procedure

Run the following lines at the shell prompt
inside BuildGates
 set_top_timing_module
$top
 set_current_module $top
 source timing.tcl
 timing
Create Report File

Create the following file and save it as
“report.tcl”
Create Reports

From the BuildGates command line run
the following two commands
 source


report.tcl
report
Upon completion of these steps, verify that
the files in your newly created report
directories are the same as the following
files
Timing Report
Area Report
BuildGates Generated NetList
Ambit Library File (ALF)
File >> Open
Select “Ambit Library”
In this example “xatl.alf” is used for the Ambit Library File
NOTE: You may select your known working Ambit Library File
Setting Technology & Optimizing

Commands >> Set
Target Technology
 Select
Technology for
corresponding ALF File

Commands >>
Optimize
 Choose
optimize
options similar to
screenshot
Full Adder Post-Optimization (using
xatl.alf)
With this window active select File>>Save, Choose Verilog, save as
“full_adder_opt.v”
Full Adder Output Verilog (xatl.alf)
(Your file should resemble this)
Mux Post-Optimization (using
xatl.alf)
With this window active select File>>Save, Choose Verilog, save as “mux_opt.v”
FF Post-Optimization (using
xatl.alf)
With this window active select File>>Save, Choose Verilog, save as “ff_opt.v”
Verilog File Save
Double click on the my_design module
and save Verilog as with the other
modules
 Save this file as “my_design_opt.v”

my_design_opt.v Verilog File
Your “my_design_opt.v” file should resemble this. Your alf file may change the
module names. Make sure that the modules called in this file are defined in
the other module files (make sure modules mux, full_adder, and ff are defined
accordingly).
Verilog Code Concatenation
•Concatenate all of your
files (my_design_opt.v,
ff_opt.v, full_adder_opt.v,
mux_opt.v) into one file
called “maincomb.v”
•Make sure the my_design
module is the last defined in
the file
Importing into ICFB
•Import your file into ICFB by choosing
File>>Import>>Verilog from the CIW
•Under the Target Library Name enter
the NCSU_Digital_Parts
•Make sure the NCSU_Digital_Parts
library is listed under the Reference
Libraries
•Highlight the “maincomb.v” file and
press the add button on “Verilog Files to
Import”
•Note: If you are using another
synthesis library, substitute that library’s
name for the NCSU_Digital_Parts
Main Module Import
The log file for the Verilog input should resemble the log file shown above.
If you have a parts library that is properly linked to the synthesis library
used in BuildGates then you will not receive the error shown above on the
first line of the log file.
Verify File Import

Verify that your imported modules resemble the
following screens by viewing the schematic of
each in the Library Manager
ICFB Schematic View of Full Adder
ICFB Schematic of Mux
ICFB Flip-Flop Schematic
Top Level Module Schematic
Top Level (Zoom)
From Here…
Assuming proper parts libraries are
available (Synthesis library with
corresponding schematic and layout parts
library) you can continue to schematic
simulations and/or layout place and route
from here.
 Hint: Cadence Ensemble

References

Synthesis and Timing Verification
Tutorial
 Dr.
Ahmet Bindal
 Computer Engineering Department, San
Jose State University

http://www.engr.sjsu.edu/abindal/synth_tim
ing_ver_tutorial.pdf