Supplementary Materials for “Geometric and chemical components of the giant
piezoresistance in silicon nanowires” by M. M. McClarty et al.
1. Nanowire fabrication
Step 1 Commercial silicon-on-insulator (SOI) wafers (Soitec S.A., France) are used for the fabrication
of the samples. The silicon device layer (DL) has a thickness of 300±22 nm, the buried oxide (BOX)
layer has a thickness of 3±0.072 µm and the silicon handle wafer has a thickness of 675±15 µm. The
orientation of the device layer and the handle wafer is (100). The silicon device layer and handle wafer
have a nominal resistivity of >1000 Ω cm.
Step 2 The chip layout, containing top-down silicon nanowires and on-chip strain gages, was designed
using commercial software (Layout Editor). Each rectangular chip measures about 2 cm by 1.3 cm.
The chips contain four nanowires having a width (and height) of 300 nm and a length of 1 µm. The
chips contain four on-chip strain gages having lateral dimensions of 20×200 µm. These gages are used
to monitor the externally applied stress during the piezoresistance measurements. The chips are
fabricated using the planar lithographic approach – known as a top-down approach. This involves
several steps such as: doping, masking, deposition, etching, cleaning and dicing.
Step 3 The DL of the SOI wafers is doped p-type using boron ion implantation (GA 3204, EatonAxcelis). The intended doping was 4×1018 cm-3. The implantation dose is calculated using commercial
software (SRIM). The 300 nm thick DL is implanted with two doping spikes. The SOI wafer is
subsequently annealed at high temperature (900°C) in an inert gas atmosphere. The electrical
resistivity of the DL was measured to be 0.18×10-2 ohm cm using a four point probe technique –
corresponding to ~ 3.8×1018 cm-3.
Step 4 Metallization of alignment marks, ohmic contacts, device leads and contact pads. Electron
beam (ebeam) lithography is used to produce masks for the metallization of the samples. Ebeam
lithography allows a very high resolution of pattern definition – as low as 10 nm. It enables a high
alignment precision from mask to mask – something that is very important in nanometre scale
lithography involving several steps. The alignment marks, Ohmic contacts, device leads and contact
pads are all defined using a bilayer ebeam resist (COPO/PMMA). The Ohmic contacts are formed
using a 50 nm thick patterned evaporated/lift-off platinum layer which is subsequently annealed in an
inert atmosphere to for a silicide-based (Pt-Si) Ohmic contact.
Step 5 Definition of nanowires. The nanowires are defined using a chlorine-based dry etch. In order to
do this a suitable ebeam masking material is required – a 500 nm thick layer of 2020 AZnLOF
(Microchemicals, USA) diluted with propylene glycol monomethyl ether acetate (PGMEA) (SigmaAldrich, USA) is used for this. The nLOF is a negative tone ebeam resist, once the resist is exposed a
postbake anneal is required. Following this a suitable developer solution removes the unwanted nLOF
to leave the mask. The nanowires are defined using a commercial chlorine-based dry etcher (Oxford
Instruments, UK) – calibration and optimization of the etch parameter enables the verticality of the
nanowires sides to be maximized. The DL is etched to the BOX layer – i.e. 300 nm. The cross-linked
nLOF mask is then removed using a suitable resist stripper at 70°C.
Step 5 Chip dicing. In order to complete the first phase of the fabrication, the individual chips are then
diced using a diamond tipped saw.
Step 6 Nanowire releasing. The nanowires are released by plunging the chips into a concentrated
hydrofluoric acid (50%) wet etch. The 3 µm thick BOX is removed in ~140 s, i.e. an etch rate of 21.4
nm s-1. All areas of the chip are masked except in the vicinity of the nanowires using a 1 µm thick
layer positive photoresist (AZ1518) which is patterned using a physical photomask – this is performed
one chip at a time. The HF etch is stopped using a deionized water rinse and the positive photoresist is
removed using an acetone-isopropyl alcohol-water cleaning. The chips are dried using dry nitrogen.
Stiction related problems are not observed as the BOX is thick (3000 nm) compared to the width (300
nm) of the nanowires.
2. Use of micro-Raman spectroscopy for the determination of the stress concentration
factor, b
In the Raman spectrometer the sample is scanned laterally under a ×100 microscope objective yielding
an image like that shown in the inset of Fig. 2(b) in the manuscript. Since this image shows only the
intensity of the silicon 520 cm-1 Raman line, it does not reveal anything about the local stress in the
nanowire. It is included to prove that it is possible to identify the Raman signal from a single nanowire
(despite its small size) with a diffraction limited micro-Raman spectrometer. The pixel size in the
image is 0.3 × 0.3 micrometres and the nanowire therefore typically consists of 3 to 4 pixels, and
hence 3 to 4 individual Raman spectra can be analyzed per nanowire. Since the neighboring strain
gage is macroscopically large, many more pixels can be used to obtain multiple Raman spectra, but
typically image a 3×3 pixel square is used, resulting in 9 individual Raman spectra to analyze.
The upper panel of Figure S1(a) shows 9 Raman spectra obtained from an unstrained strain gage. A
standard Voigt function fit to each spectrum yields the peak position, from which an average position
can be found (this is shown as the vertical, solid line). Note that the standard deviation in the
distribution of peak positions can also be obtained, and that this will be used to estimate the horizontal
error bars shown in Fig. 2(b) and in Fig. 4(b) of the main article. The same result obtained using 3
pixels in the Raman map on a neighboring, unstrained, released nanowire is shown in the upper panel
of Fig. S1(b).
The wafer is then statically strained via bending so that the nanowires and gages on the wafer
experience the same external, uniaxial tensile stress. The same procedure is then repeated to obtain the
Raman spectra shown in the bottom panels of Fig. S1(a) and Fig. S1(b) for the strain gage and
nanowire respectively. In both cases a change, , in the Raman shift to lower wavenumbers is
observed, consistent with an applied tensile stress [1,2]. However, the shift observed on the strain gage
( = -0.075 cm-1) is smaller than that observed in the nanowire ( = -1.04 cm-1) indicating that the
local stress in the released nanowire is larger than that in the strain gage. The stress concentration
factor is the ratio of these two shifts, b = -1.04/-0.075 = 13.8. This is the raw data for a released
nanowire used to obtain the b = 13.8 point in Fig. 4(b) of the main article. The horizontal error bars on
this point are obtained from the standard deviation in the Raman peak positions (strained and
unstrained gages, and strained and unstrained nanowires) determined from the fitting procedure with
the Voigt functions.
Note that only a single value of stress, whose magnitude can be estimated from the measured value of
 on the strain gage, is applied. This typically is of the order of 50 MPa so that in the released
nanowires, the local stress during the Raman measurement is of the order of 500 MPa, significantly
larger than the applied stresses used for the piezoresistance measurements. Since b is a geometric
factor that is stress independent in elastic materials like silicon, the experimentally obtained values can
be used to understand stress concentration effects on the apparent piezoresistance at much lower
stresses. Long integration times and long term experimental instability preclude us from studying the
Raman shift as a function of applied stress, but this is not in any case necessary for an experimental
determination of b.
Fig. S1: (a) The top panel shows 9 Raman spectra obtained from neighboring pixels on an unstrained strain gage.
A Voigt fit to each spectrum yields an average peak position indicated by the solid, vertical line. When the wafer
is statically stressed via bending, the Raman spectra in the bottom panel are obtained. The same fitting procedure
yields an average peak position which is shifted by -0.075 cm-1 relative to the unstrained case, consistent with an
applied uniaxial tensile stress. (b) The same curves obtained on a mechanically released nanowire where the
stress-induced shift in the peak position is much larger (-1.04 cm-1) due to stress concentration. The ratio of these
two shifts, -1.04/-0.075 = 13.8, is the stress concentration factor (b) for this nanowire.
3. Stress concentration in nanowires with different geometries
The level of stress concentration, as characterized by the parameter b, depends sensitively on
geometry, and specifically on the aspect ratio of the nanowires and their height above the handle wafer
as is shown here. Finite element calculations of the stress/strain relationship were performed on a
variety of nanowires with different aspect ratios, and also for different heights above the handle of an
SOI wafer (i.e. different BOX thicknesses), the results of which are shown in Fig. S2.
The black dots in Fig. S2(a) show the estimated value of b prior to release for a 300 nm × 300 nm × l
nanowire and a BOX thickness of 3 m. The length l = 1 m corresponds to the actual, pre-released
nanowires that were fabricated using the process outlined above, and studied in the main article. In the
finite element calculation l is varied in one micrometer steps from 1 to 5 microns. For l = 1 m it is
seen that b = 1.9 as discussed in the main article. As l increases b gradually drops to approximately 1.3
for l = 5 m. The red dots in Fig. S2(a) show the values of b for the released structures on the same
BOX thickness. The general conclusion is the same, with b dropping from 9 for l = 1 m (i.e. the
samples for which the results are shown in Fig. 3 and Fig. 4 of the main article) to 3.2 for l = 5 m. In
Fig. S2(b), the BOX thickness is increased to 6 m while the released nanowire dimensions are
unchanged. In this case b is much larger as the green dots show, dropping from almost 14 for l = 1 m
to 5.5 for l = 5 m.
From these results it is clear that the general concept of stress concentration holds for all aspect ratios
but the effect is largest in smaller aspect ratio objects that are suspended higher above the substrate. As
an aside, this is why significant stress concentration effects were not observed in previous works
where the nanowires were ‘long and low’ [3].
In considering whether stress concentration may have been important in mechanically released, bottom
up structures like those studied elsewhere [4], it is important to note that there is no BOX – the
nanowires are grown directly across a trench etched into a bulk silicon substrate. Fig. S2(c) shows a
calculation of b for a 300 nm × 300 nm × l nanowire suspended 6 m above the bottom of the trench.
Since silicon is twice as rigid as its oxide, the stress concentration in this type of object is significantly
higher. While b still drops for increasing aspect ratios, it does so from 26 at l = 1 m to 10 for l = 5
m. While the exact nanowire lengths and heights in other works are not known, this would suggest
that stress concentration accounts for a significant part of the giant piezoresistance observed, for
example, by He et al. [4] in suspended, bottom-up nanowires.
Fig. S2: Stress concentration factor, b, as a function of nanowire geometry for a fixed 300 nm × 300 nm
nanowire cross section. Small aspect ratio, mechanically released, nanowires suspended high above a substrate
have the highest stress concentration factors. (a) The case of non-released nanowires on a 3 m thick BOX
(black dots, left axis) and of the equivalent dimension nanowires after release (red dots, right axis). (b) The same
case as the red dots in (a), but with the BOX thickness increased to 6 m (green dots). (c) The same dimensions
as in (b) with the BOX replaced by silicon. This represents the situation encountered by bottom-up nanowires
grown across a trench etched into a bulk silicon wafer. In this case the stress concentration can increase the
apparent PZR by more than an order of magnitude, even for higher aspect ratio nanowires.
4. Variation in PZR response after nanowire release in concentrated HF
After the 2 minute 20 second etch in concentrated HF, and following a reoxidation in air, the
resistance of the nanowires was found to have increased by up to 5 orders of magnitude relative to its
value in the as fabricated nanowires. This phenomenon is tentatively ascribed to the neutralization of
Boron acceptors by protons accelerated into the silicon by the surface depletion layer electric field [5].
In some cases the resulting resistance exceeded 1 G – PZR however is reported only from those
nanowires with resistances lower than this threshold since the extremely small currents in the higher
resistance wires makes reliable measurement difficult. Fig. S3 shows data from 4 nanowires after HF
treatment. The data shown in Fig. S3(a), (b) and (d) is that which appears in the main manuscript (Fig.
3). Plots of the response of individual nanowires in this fashion is perhaps somewhat clearer than the
composite Fig. 3 of the main manuscript, and highlights the similarity between the measured PZR and
that expected based on the stress concentration boosted bulk value (gray lines), with the only deviation
occurring in one of the four cases (Fig. S3(c)).
Fig. S3: PZR measured on nanowires after natural reoxidation following mechanical release using
concentrated HF. Data in (a), (b) and (d) is also shown in Fig. 3 of the main manuscript. In the
majority of cases the PZR is close to the bulk value multiplied by the stress concentration factor, b
(gray lines). In one case (c) the PZR is somewhat larger than this.
The gating effects used to determine the doping type of the silicon nanowires after treatment with
concentrated HF and after subsequent treatment with HNO3 are observed to be similar across the
devices on which the gating effect was measured (2 n-type and 2 p-type cases). The trend is always
towards larger currents at more positive gate biases for the n-type cases, while the reverse is true for
the HNO3 treated p-type cases. Note that while the gate effect is particularly inefficient due to the
thick BOX layer (typical ‘subthreshold slopes’ are of the order of 1500 V/dec. which is orders of
magnitude higher than in optimized field effect transistors), it is sufficient to estimate the doping type.
Fig. S4: (Left column) Variation in current through nanowires after a concentrated HF etch followed
by a subsequent HNO3 dip. The decrease in current with increasingly positive gate bias indicates ptype conduction. (Right column) Variation in current through nanowires directly after a concentrated
HF etch. The increase in current with increasingly positive gate bias indicates n-type conduction.
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