Computer Systems Architectures Mock Theory Test
1. If the CPU’s data bus is 7 bits wide
A) What is the minimum and maximum unsigned integer the machine can store. Show them in
decimal and binary format. [ /4]
An unsigned integer, a number that not (-) in nature. If the data bus is 7 bits wide, there
are 7 places to put a 0 or 1 in each bit. In an unsigned integer, the smallest number it
can hold is 0000000 which is 0 and the largest number it can hold is 1111111 or 127
(2size - 1).
B) What is the minimum and maximum two’s complement number the machine can store. Show
them in signed decimal and two’s complement representation. [ /6]
For a 2's complement number, the most significant bit is the sign bit and the rest of the
bits are used for the number portion. The smallest number is 1111111 which is -64
while the largest number is 0111111 which is +63.
2. Develop a logic circuit that can be used to check if two 3-bit binary numbers are equal. [ /10]
To compare two 3-bit binary numbers. Suppose that abc is the bits of number 1 and def
is the bits of number 2. In order for these two to be equal, these must be true: a = d, b =
e, and c = f. All of these must be true in order for this to result in 1, which means a AND
d should result 1 otherwise 0 and the same will be done for b, e and c, f:
E = (a AND d) AND (b AND e) AND (c AND f)
a
b
c
d
e
E
f
3. Using only Boolean algebra (and not a Karnaugh map or truth table), prove that z = bd+cd [
/10]
To solve this problem with Boolean Algebra, the goal is to first find terms that either
match up or can cancel. In this problem, there are a couple of terms that have common
terms. Terms 1 and 4 have everything the same except for a, Terms 2 and 3 have
everything the same except for c, and Terms 5 and 6 have everything the same except
for c.
𝑧 = 𝑎̅ ∙ 𝑏̅ ∙ 𝑐 ∙ 𝑑 + 𝑎̅ ∙ 𝑏 ∙ 𝑐̅ ∙ 𝑑 + 𝑎̅ ∙ 𝑏 ∙ 𝑐 ∙ 𝑑 + 𝑎 ∙ 𝑏̅ ∙ 𝑐 ∙ 𝑑 + 𝑎 ∙ 𝑏 ∙ 𝑐̅ ∙ 𝑑 + 𝑎 ∙ 𝑏 ∙ 𝑐 ∙ 𝑑
𝑧 = (𝑎̅ ∙ 𝑏̅ ∙ 𝑐 ∙ 𝑑 + 𝑎 ∙ 𝑏̅ ∙ 𝑐 ∙ 𝑑) + (𝑎̅ ∙ 𝑏 ∙ 𝑐̅ ∙ 𝑑 + 𝑎̅ ∙ 𝑏 ∙ 𝑐 ∙ 𝑑) + (𝑎 ∙ 𝑏 ∙ 𝑐̅ ∙ 𝑑 + 𝑎 ∙ 𝑏 ∙ 𝑐 ∙ 𝑑)
The first () can factor out the 𝑏̅ ∙ 𝑐 ∙ 𝑑, the second can factor out 𝑎̅ ∙ 𝑏 ∙ 𝑑, and the third can
factor out 𝑎 ∙ 𝑏 ∙ 𝑑. This gives terms inside of the () to cancel out as they are valued at 1.
𝑧 = 𝑏̅ ∙ 𝑐 ∙ 𝑑(𝑎̅ + 𝑎) + 𝑎̅ ∙ 𝑏 ∙ 𝑑(𝑐̅ + 𝑐) + 𝑎 ∙ 𝑏 ∙ 𝑑(𝑐̅ + 𝑐)
𝑧 = 𝑏̅ ∙ 𝑐 ∙ 𝑑 + 𝑎̅ ∙ 𝑏 ∙ 𝑑 + 𝑎 ∙ 𝑏 ∙ 𝑑
Next step is to factor out the bd and eliminating the a's.
𝑧 = 𝑏̅ ∙ 𝑐 ∙ 𝑑 + 𝑏 ∙ 𝑑(𝑎̅ + 𝑎)
𝑧 = 𝑏̅ ∙ 𝑐 ∙ 𝑑 + 𝑏 ∙ 𝑑
Factoring d out gives:
𝑧 = 𝑑(𝑏̅ ∙ 𝑐 + 𝑏)
The next step is to use DeMorgan's Law of the term inside the ().
̅̅̅̅̅̅̅̅̅
̅̅̅̅̅
̅ ∙ 𝑐 ∙ 𝑏̅)
𝑧 = 𝑑(𝑏
Changing the ̅̅̅̅̅
𝑏̅ ∙ 𝑐 term gives 𝑏 + 𝑐̅.
̅̅̅̅̅̅̅̅̅̅̅̅̅
𝑧 = 𝑑((𝑏
+ 𝑐̅) ∙ 𝑏̅)
And then factor back in the 𝑏̅.
̅̅̅̅̅̅̅̅̅̅̅̅̅̅
𝑧 = 𝑑(𝑏
∙ 𝑏̅ + 𝑐̅ ∙ 𝑏̅)
The value of 𝑏 ∙ 𝑏̅ = 0, thus:
𝑧 = 𝑑(𝑐̅̅̅̅̅̅
∙ 𝑏̅)
Undoing the DeMorgan's Law, gives:
𝑧 = 𝑑(𝑐 + 𝑏) = 𝑏𝑑 + 𝑐𝑑
4. This is the Karnaugh map of a logic expression.
cd\ab
00
01
11
10
00
1
0
0
1
01
0
1
0
0
11
0
1
0
0
10
1
0
0
1
A. Draw the corresponding logic circuit before simplification [ /7]
To find the logic circuit before simplification, wherever there is a 1 in the K-Map, that
value is put into the unsimplified expression. For instance in the corners, there are 1's,
and from there we look at the values of the input abcd. That spot is 0000. For the top
right corner it is 1000, bottom left corner is 0010, and the bottom right corner is 1010.
The two values in the middle are 0101 and 1101. Where there is a 1 in each expression
it is that variable and when there is a 0 it is the not form of that variable.
̅ ∙ 𝑐̅ ∙ 𝑑
̅
̅∙𝑏
0000 = 𝑎
̅
̅
1000 = 𝑎 ∙ 𝑏 ∙ 𝑐̅ ∙ 𝑑
̅∙𝑐∙𝑑
̅
̅∙𝑏
0010 = 𝑎
̅
̅
1010 =𝑎 ∙ 𝑏 ∙ 𝑐 ∙ 𝑑
̅ ∙ 𝑏 ∙ 𝑐̅ ∙ 𝑑
0101 = 𝑎
1101 = 𝑎 ∙ 𝑏 ∙ 𝑐̅ ∙ 𝑑
Once the values are found, they are then added together.
̅ ∙ 𝑐̅ ∙ 𝑑
̅+𝑎∙𝑏
̅ ∙ 𝑐̅ ∙ 𝑑
̅+𝑎
̅∙𝑐∙𝑑
̅+𝑎∙𝑏
̅∙𝑐∙𝑑
̅+𝑎
̅∙𝑏
̅∙𝑏
̅ ∙ 𝑏 ∙ 𝑐̅ ∙ 𝑑 + 𝑎 ∙ 𝑏 ∙ 𝑐̅ ∙ 𝑑
𝑧=𝑎
B. Draw the corresponding logic circuit after simplification using the Karnaugh Map [ /8]
To find the simplified circuit of this problem, the goal is to circle in groups of multiples
of 2. Don't forget that the corners are also a choice too.
cd\ab
00
01
11
10
00
1
0
0
1
01
0
1
0
0
11
0
1
0
0
10
1
0
0
1
Looking at the values that are circled in each circle, the green values are the same
for each bit, which gives:
0000
1000
0010
1010
4-bit Circle
0101
1101
2-bit Circle
The terms that are in green are the ones we have to put as our new expression. For the
4-bit Circle, bits 2 and 4 (b and d) are the same thus they are kept for the expression:
𝑏̅ ∙ 𝑑̅. For the 2-bit circle b, c, and d are the same where b = d = 1 and c = 0, thus this
expression is: 𝑏 ∙ 𝑐̅ ∙ 𝑑. Thus the final expression is:
𝑧 = 𝑏̅ ∙ 𝑑̅ + 𝑏 ∙ 𝑐̅ ∙ 𝑑
5. Draw the timing diagram for an SR latch (cross coupled NORS), showing the following event
sequence. (S = 1, R = 0), (S = 0, R = 0), (S = 0, R = 0), (S = 0, R = 1). At the initial state of the latch,
S+R = 0, Q = 0, Q bar = 1. [ /15]
For this problem, the timing diagram starts with 4 dotted lines one for each event
sequence and then at each point when S or R changes that should put S/R up if it is a 1 or
down if it is a 0. For each Q and Q' (not Q) are also shown in this problem as well with
the values starting in this problem at Q = 0 and Q' = 1.
S = 1, R = 0
S = 0, R = 0
S = 0, R = 0
S = 0, R = 1
S
R
The next step is to draw Q and Q'. Remember that SR latches have the following
properties.
S
0
0
1
1
R Q Q'
Name
0 Q Q'
Hold
1 0 1
Reset
0 1 0
Set
1 -- -- Not Used
For the starting state (problem) the Q = 0 and Q' = 1. Thus it now looks like this up to the
first dotted line.
S = 1, R = 0
S = 0, R = 0
S = 0, R = 0
S = 0, R = 1
S
R
Q
Q'
When S = 1 and R = 0 (first line), Q will set to 1 and Q' will be 0. When S = 0, R = 0 the
state will hold at 1 and 0 respectfully (for both situations). And then when S = 0, R = 1
the state will reset for Q = 0 and Q' = 1.
S = 1, R = 0
S = 0, R = 0
S = 0, R = 0
S = 0, R = 1
S
R
Q
Q'
6. A) Draw a flowchart to compute 1+2+3+4+5+ ...+1000 using a loop. [ /5]
To draw a flowchart in general, the starting circle will always be the same for each
problem. If you need to do something with the variables (operations that will be in
boxes) and if you need input from the user, that will be parallelogram. To sum a group of
numbers, you need to start a counter at 1 and sum = 0 and then using a loop while the
counter (i) is <= that value (1000) then add i to that sum and then increment i by 1.
Start
Let Sum = 0, i = 1
Is i <= 1000
Output Sum
Add i to sum
Add 1 to i
B) Draw a flowchart to compute 1+2+3+4+5+ ...+1000 without using any loop.
(Hint: 1+1000 = 2+999 = 3+998 = …) [ /5]
To do this without any loop, notice that the sum of 1+1000, 2+999, 3+998 = 1001. If we
take that value and multiply by the number of terms / 2 (500), we can get the result
without a loop.
Start
Let Sum = 1001
Multiply Sum by
500
Output Sum
C) Draw a flowchart to compute the sum of n numbers without using any loop [ /10]
For the general formula for sum of the numbers from 1...n, it is n(n + 1) / 2. Thus it is the
following for the flowchart. The steps are to start with n, and then get Sum = n + 1, then
multiply Sum by n and then divide by 2.
Start
Let N = value
Let Sum = N + 1
Multiply Sum by
N
Divide Sum by 2
Output Sum
7. Draw a state transition diagram and State Table that reads a string of four characters (‘A’, ‘C’,
‘G’ and ‘T’) and asserts an output if it finds the sequence ‘ATG’. [ /20]
To draw a state transition diagram, we use nodes to represent the states for this
situations. The first state is the starting state but before we can move onto state
2, we need to see a 'A'. So all other characters will circle back to this state. At this
point we could see AA, AT, AC, and AG. If we see AT we move onto State 3. If we
see AC or AG, then it will not be a match at all so we start over at State 1. If
however we have AA, we could possibly see ATG IF the answer is AATG or
AAATG or even further. Thus when we see successive A's we need to stay at State
2 to see if ATG is at the end of the A's. Now at State 3 we could see ATA, ATC, ATT
or ATG. If ATA appears we could see an ATG if it appears like ATATG, thus we
need to start at State 2 if the input comes up as ATA. If it's ATC or ATT, neither of
these could look like ATG, so we have to start over and of course ATG will go to
State 4. At State 4, ATG has appeared and we print it and then the next input will
be A, T, C, or G. If it is A then we can start at State 2 because ATG could appear
back to back after another ATG like ATGATG. In any other case, we start over at
State 1. The state transition diagram of the written description here is:
T, C, G
Print
T, C, G
S1
S4
A
Start
A
C, G
G
T, C
T
S3
S2
A
A
The State Table describes what states you go to if a certain input is given. Rows
will be the state and the columns will be the input. The values inside of the table
will be the state that you go to. So for S1, under inputs T, C, and G, since the
values are looped back to S1, we put S1 in the table. And under A since we go to
2, S2 is put in the table. Doing that for all States gives:
S1
S2
S3
S4
A
S2
S2
S2
S2
C
S1
S1
S1
S1
T
S1
S3
S1
S1
G
S1
S1
S4
S1
When the state table is read, if we're at State 1, if we read A then going to [S1, A]
we get S2. That will be the next state to go to. Now we're at State 2, if we read A
then going to [S2, A] will give S2. etc.