Chapter 7 -- Modular Sequential Logic
Serial-in, Serial-out Shift Register
xn
Cell n
Serial in
xi
Cell i
xi-1
Cell i-1
x1
Cell 1
Serial out
M
S
M
S
Shift
control
pulse
M
S
M
S
(a)
Serial in
Serial out
S
S
Q
CK
R
Q
S
CK
R
Q
Shift
(b)
Q
CK
Q
R
Q
Generic Shift Register
Parallel in (Y)
Parallel out (X)
Serial in
n-Bit shift
register
Serial out
Preset control
Shift pulse
Clear control
(a)
Parallel out (X)
Parallel in (Y)
Serial out
n-Bit shift
register
Serial in
n-Bit shift
register
Preset control
(b)
Shift pulse
Shift pulse
Clear control
Clear control
(c)
SN74164 Serial-in, Serial-out Shift Register
(9)
Clear
(8)
Clock
Serial A
inputs B
(1)
Clear
R
QA
Clear
R
QB
CK
(2)
S
Clear
R
QC
CK
S
QA
(3)
Output
QA
Clear
R
QD
CK
QB
(4)
Output
QB
S
Clear
R
QE
CK
S
QC
(5)
Output
QC
CK
QD
S
(6)
Output
QD
(a)
Clear
Serial A
inputs B
Clock
QA
Outputs
QB
QC
QD
QE
QF
QG
Clear
(b)
Clear
R
QF
Clear
Clear
R
QG
CK
QE
S
(10)
Output
QE
Clear
R
QH
CK
QF
S
(11)
Output
QF
CK
QG
S
(12)
Output
QG
QH
(13)
Output
QH
(Serial output)
SN74164 Function Table and Package
Inputs
Clear
L
H
H
H
H
Clock
´
L
-
Outputs
A
´
´
H
L
´
B
QA
QB
´ L L
´ QA0 QB0
H H QAn
´ L QAn
L L QAn
É
QH
L
QH0
QGn
QGn
QGn
QA0, QB0, QH0 = levels of QA, QB, QH, respectively,
before the indicated steady-state input conditions are established.
QAn, QGn = levels of QA, QG, respectively, before the most
recent - transition of the clock (1-bit shift)
(c)
A
1
14
VCC
B
2
13
QH
QA
3
12
QG
QB
4
11
QF
QC
5
10
QE
QD
6
9
Clear
GND
7
8
Clock
(d)
SN74165 8-bit Serial-In, Serial-out Shift register
Parallel inputs
A
Shift/Load
Clock inhibit
Clock
Serial
B
(11)
(1)
C
(12)
D
(13)
E
(14)
F
(3)
G
(4)
H
(5)
(6)
(15)
(2)
(10)
S
CK
S
CK
D
S
CK
D
R
S
CK
D
R
S
CK
D
R
S
CK
D
R
S
CK
D
R
D
R
A
Shift/Load
Clock inhibit
Clock
Serial
(11)
(1)
(15)
(2)
S
CK
(10)
D
R
(b)
Inputs
Shift/
load
Clock
inhibit
Clock
L
H
H
H
H
´
L
L
L
H
´
L
´
Parallel
Serial A...H
´
´
H
L
´
a...h
´
´
´
´
(c)
Internal
outputs
QA
QB
a
QA0
H
L
QA0
b
QB0
QAn
QAn
QB0
Output
QH
h
QH0
QGn
QGn
QH0
(9)
QH
(7)
QH
D
R
(a)
S
CK
R
SN74165 Timing Diagram
Clock
Clock inhibit
Serial input
L
Shift/load
A
B
C
D
H
L
H
L
Data
E
H
F
L
G
H
H
H
Output QH
Output QH
H
H
L
H
L
H
L
H
L
L
H
L
H
L
H
L
Serial shift
Load
Inhibit
(d)
Parallel Accumulator
xn
x2
x1
...
FA
Q
FA
D
CK
CLR
Q
...
HA
D
Q
CK
CLR
CK
CLR
...
zn+1 zn
D
Clear
Accumulate
z2
z1
(b)
Synchronous Binary Counter
Xn
X3
X2
X1
...
Overflow
Q
J
Q
CK
Q
J
Q
CK
K
Q
CLR
J
Q
CK
K
Q
CLR
K
CLR
J
1
CK
Q
K
CLR
...
Clear
...
Count
Inhibit
(a)
Xn
X3
X2
X1
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
1
0
1
0
1
0
(b)
Recycles
SN74163 Synchronous Binary Counter
Load
(9)
J
Q
(14)
QA
CK
Data A
(3)
K
J
Q
(13)
QB
CK
Data B
Clock
(4)
K
(2)
J
Q
(12)
QC
CK
Data C
(5)
K
J
Q
(11)
QD
CK
Data D
Clear
ENP
ENT
(6)
K
(1)
(7)
(15)
(10)
(a)
Inputs
Clear Load ENT
L
´
´
H
L
´
H
H
H
H
H
L
H
H
ґ
ENP
´
´
H
ґ
L
(b)
Mode
Synchronous clear
Synchronous load
Count
Hold
Hold
RCO
SN74163 Timing Diagram
Clear
Load
A
Data
inputs
B
C
D
Clock
ENP
ENT
QA
QB
Outputs
QC
QD
RCO
12 13 14
Sync
clear
15
Count
Sync
load
(c)
0
1
2
Inhibit
Asynchronous Down Counter
Xn
...
X3
X2
X1
Xn
...
X3
X2
X1
1
...
1
1
1
0
...
0
0
0
0
...
0
0
0
1
...
1
1
1
0
...
0
0
1
1
...
1
1
0
0
...
0
1
0
1
...
1
0
1
0
...
0
1
1
1
...
1
0
0
0
...
1
0
Up count mode
0
1
...
0
1
Down count mode
1
(a)
Xn
X2
X1
...
Q
J
Q
J
...
CK
Q
Count
K
CK
Q
CLR
Q
J
CK
K
CLR
Q
K
CLR
...
Clock
Clear
(b)
Synchronous Up/Down Counter
Xn
X2
X1
...
...
Q
Up
overflow
J
Up/down
Q
CK
Q
J
Q
CK
K
Q
CLR
K
CLR
J
1
CK
Q
K
CLR
...
...
Down
overflow
...
Clock
...
Clear
SN74160 Synchronous Decade Counter
(1)
Clear
Clock
1
16
2
15
VCC
RCO
Clear
'160
CTRDIV 10
CT = 0
(9)
Load
M1
M2
A
3
14
QA
ENT
B
4
13
QB
ENP
C
5
12
QC
D
6
11
QD
ENP
7
10
ENT
Clock
A
B
C
GND
8
9
(a)
Load
(10)
(7)
(2)
(3)
(4)
(5)
(6)
D
3CT = 9
(15)
G3
RCO
G4
G5/2,3,4+
1,5D (1)
(2)
(4)
(8)
(b)
(14)
(13)
(12)
QA
QB
QC
(11)
QD
SN74160 Logic Diagram
Load
(9)
J
Q
(14)
QA
CK
Data A
(3)
K CLR
J
Q
(13)
QB
CK
Data B
Clock
(4)
K
CLR
(2)
J
Q
(12)
QC
CK
Data C
(5)
K
CLR
J
Q
(11)
QD
CK
Data D
Clear
ENP
ENT
(6)
K
CLR
Q
(1)
(7)
(15)
(10)
(c)
RCO
SN74160 Timing Diagram
Clear
Load
A
Data
inputs
B
C
D
Clock
ENP
ENT
QA
QB
Outputs
QC
QD
RCO
Async
clear
7
8
9
0
1
Count
Sync
load
(d)
2
3
Inhibit
Asynchronous BCD Counter
X3
X2
X1
X0
Count
S
S
Q
J
J
CK
Q
S
Q
CK
K
Q
J
Q
CK
K
R
S
Q
Q
R
J
CK
K
Q
R
Clock
K
R
Clear
(a)
0
1
0
2
10
8
3
9
2
0
4
8
0
4
5
7
6
6
4
(b)
Digital Timer Block Diagram
Minutes
Seconds
1 Pulse/hour
1 Pulse/minute
¸6
¸ 10
¸6
¸5
¸ 12
¸ 10
Clear
Start/Stop
Pulse
generator
1 Pulse/second
Power line
Figure 7.22
SN7492A Asynchronous Counter
Clock B
1
14
J
Clock A
Clock A
NC
2
13
NC
NC
3
12
QA
NC
4
11
QB
VCC
5
(14)
Q
(12)
QA
Q
(11)
QB
Q
(9)
QC
CK
K
J
10
GND
(1)
Clock B
RO(1)
6
9
QC
RO(2)
7
8
QD
CK
K
(a)
J
CK
'92
(6)
&
RO(1)
CTR
(7)
CT = 0
(14)
DIV 2
K
Q
J
Q
RO(2)
ClockA
ClockB
(1)
+
DIV 3
+
4+
CT
DIV 2
(b)
(12)
0
1Z4
11
(9)
(8)
QA
CK
QB
K
QC
QD
R0(1)
R0(2)
(6)
(7)
(a)
(8)
QD
SN7492A Timing Diagram
Clock B
R0(1) = R0(2)
QB
0
1
0
0
QC
0
0
1
0
JB = QC
1
1
0
1
KB
1
1
1
1
JC = QB
0
1
0
0
1
1
1
1
KC
(d)
SN7492A State Diagrams
0
8
1
12
0
2
13
3
2
12
4
10
11
5
10
4
8
9
0
8
(e)
8
1
12
0
2
0
14
4
13
5
12
6
8
10
9
4
8
0
(f)
Modulo-N Asynchronous Counter
X0
X1
Xn- 1
Count
control
J
Q
J
K
Q
K
R
R
State detection
logic
J
Q
CK
CK
CK
Q
S
S
S
Q
Count
pulse
K
Q
R
Clear
control
SN74293 Asynchronous Binary Counter
J
Input A
(10)
QA
(9)
QA
0
CK
8
K
1
0
2
12
3
14
J
Input B
QB
(5)
2
QB
15
(11)
0
CK
4
K
14
5
J
QC
(4)
12
13
QC
4
CK
6
12
K
8
J
CK
QD
(8)
QD
10
7
11
6
4
10
K
R0(1)
R0(2)
9
8
8
(12)
(13)
(a)
(b)
0
Modulo-13 Counter Design -- Example 7.1
74293
Clock
Input A
QA
Input B
QB
QC
QD
R0(1)
R0(2)
7411/3
7432/4
Clear
(a)
0
13
1
0
2
12
8
3
10
2
11
0
4
10
5
8
9
6
8
7
6
0
4
(b)
4